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Searched refs:UVD_LMI_CTRL2__STALL_ARB_UMC_MASK (Results 1 – 24 of 24) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v7_0.c876 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, in uvd_v7_0_sriov_start()
877 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_sriov_start()
933 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); in uvd_v7_0_sriov_start()
989 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, in uvd_v7_0_start()
990 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_start()
1040 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_start()
1152 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, in uvd_v7_0_stop()
1153 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_stop()
1166 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_stop()
Dvcn_v1_0.c903 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v1_0_start_spg_mode()
1175 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, in vcn_v1_0_stop_spg_mode()
1176 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v1_0_stop_spg_mode()
Dvcn_v5_0_0.c797 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v5_0_0_start()
976 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v5_0_0_stop()
Dvcn_v4_0_5.c1039 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v4_0_5_start()
1242 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v4_0_5_stop()
Dvcn_v4_0_3.c1125 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v4_0_3_start()
1331 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v4_0_3_stop()
Dvcn_v2_0.c1047 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v2_0_start()
1204 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v2_0_stop()
Dvcn_v4_0.c1127 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v4_0_start()
1579 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v4_0_stop()
Dvcn_v2_5.c1104 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v2_5_start()
1456 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v2_5_stop()
Dvcn_v3_0.c1178 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v3_0_start()
1597 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v3_0_stop()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h481 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Duvd_3_1_sh_mask.h309 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 macro
Duvd_4_0_sh_mask.h312 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L macro
Duvd_4_2_sh_mask.h309 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 macro
Duvd_5_0_sh_mask.h341 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 macro
Duvd_6_0_sh_mask.h343 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h999 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Dvcn_2_5_sh_mask.h3310 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Dvcn_2_0_0_sh_mask.h2072 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Dvcn_2_6_0_sh_mask.h899 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Dvcn_3_0_0_sh_mask.h4622 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Dvcn_5_0_0_sh_mask.h4190 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Dvcn_4_0_5_sh_mask.h4618 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Dvcn_4_0_0_sh_mask.h4775 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
Dvcn_4_0_3_sh_mask.h4818 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro