Searched refs:UTMIP_PLL_CFG1 (Results 1 – 3 of 3) sorted by relevance
183 #define UTMIP_PLL_CFG1 0x484 macro1174 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()1184 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()1797 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1808 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1817 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1820 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
170 #define UTMIP_PLL_CFG1 0x484 macro2836 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2847 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2850 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2853 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2868 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2871 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
94 #define UTMIP_PLL_CFG1 0x804 macro532 val = readl_relaxed(base + UTMIP_PLL_CFG1); in utmi_phy_power_on()537 writel_relaxed(val, base + UTMIP_PLL_CFG1); in utmi_phy_power_on()