Searched refs:UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (Results 1 – 2 of 2) sorted by relevance
200 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) macro2888 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; in tegra210_utmi_param_configure()2987 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE)) in tegra210_init_pllu()
212 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) macro1837 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; in clk_pllu_tegra114_enable()