1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _umc_6_7_0_SH_MASK_HEADER
24 #define _umc_6_7_0_SH_MASK_HEADER
25 
26 
27 // addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map
28 //MCA_UMC_UMC0_MCUMC_STATUST0
29 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT                                                         0x0
30 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT                                                      0x10
31 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT                                                          0x16
32 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT                                                           0x18
33 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT                                                          0x1e
34 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT                                                         0x20
35 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT                                                          0x26
36 #define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT                                                             0x28
37 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT                                                          0x29
38 #define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT                                                            0x2b
39 #define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT                                                          0x2c
40 #define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT                                                              0x2d
41 #define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT                                                              0x2e
42 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT                                                          0x2f
43 #define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT                                                       0x34
44 #define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT                                                             0x35
45 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT                                                          0x36
46 #define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT                                                               0x37
47 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT                                                      0x38
48 #define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT                                                               0x39
49 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT                                                             0x3a
50 #define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT                                                             0x3b
51 #define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT                                                                0x3c
52 #define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT                                                                0x3d
53 #define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT                                                          0x3e
54 #define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT                                                               0x3f
55 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK                                                           0x000000000000FFFFL
56 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK                                                        0x00000000003F0000L
57 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK                                                            0x0000000000C00000L
58 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK                                                             0x000000003F000000L
59 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK                                                            0x00000000C0000000L
60 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK                                                           0x0000003F00000000L
61 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK                                                            0x000000C000000000L
62 #define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK                                                               0x0000010000000000L
63 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK                                                            0x0000060000000000L
64 #define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK                                                              0x0000080000000000L
65 #define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK                                                            0x0000100000000000L
66 #define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK                                                                0x0000200000000000L
67 #define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK                                                                0x0000400000000000L
68 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK                                                            0x000F800000000000L
69 #define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK                                                         0x0010000000000000L
70 #define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK                                                               0x0020000000000000L
71 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK                                                            0x0040000000000000L
72 #define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK                                                                 0x0080000000000000L
73 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK                                                        0x0100000000000000L
74 #define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK                                                                 0x0200000000000000L
75 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK                                                               0x0400000000000000L
76 #define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK                                                               0x0800000000000000L
77 #define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK                                                                  0x1000000000000000L
78 #define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK                                                                  0x2000000000000000L
79 #define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK                                                            0x4000000000000000L
80 #define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK                                                                 0x8000000000000000L
81 //MCA_UMC_UMC0_MCUMC_ADDRT0
82 #define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT                                                           0x0
83 #define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT                                                            0x38
84 #define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK                                                             0x00FFFFFFFFFFFFFFL
85 #define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK                                                              0xFF00000000000000L
86 
87 
88 // addressBlock: umc_w_phy_umc0_umcch0_umcchdec
89 //UMCCH0_0_BaseAddrCS0
90 #define UMCCH0_0_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
91 #define UMCCH0_0_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
92 #define UMCCH0_0_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
93 #define UMCCH0_0_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
94 //UMCCH0_0_AddrMaskCS01
95 #define UMCCH0_0_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
96 #define UMCCH0_0_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
97 //UMCCH0_0_AddrSelCS01
98 #define UMCCH0_0_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
99 #define UMCCH0_0_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
100 #define UMCCH0_0_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
101 #define UMCCH0_0_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
102 #define UMCCH0_0_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
103 #define UMCCH0_0_AddrSelCS01__RowLo__SHIFT                                                                    0x18
104 #define UMCCH0_0_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
105 #define UMCCH0_0_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
106 #define UMCCH0_0_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
107 #define UMCCH0_0_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
108 #define UMCCH0_0_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
109 #define UMCCH0_0_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
110 #define UMCCH0_0_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
111 #define UMCCH0_0_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
112 //UMCCH0_0_AddrHashBank0
113 #define UMCCH0_0_AddrHashBank0__XorEnable__SHIFT                                                              0x0
114 #define UMCCH0_0_AddrHashBank0__ColXor__SHIFT                                                                 0x1
115 #define UMCCH0_0_AddrHashBank0__RowXor__SHIFT                                                                 0xe
116 #define UMCCH0_0_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
117 #define UMCCH0_0_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
118 #define UMCCH0_0_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
119 //UMCCH0_0_AddrHashBank1
120 #define UMCCH0_0_AddrHashBank1__XorEnable__SHIFT                                                              0x0
121 #define UMCCH0_0_AddrHashBank1__ColXor__SHIFT                                                                 0x1
122 #define UMCCH0_0_AddrHashBank1__RowXor__SHIFT                                                                 0xe
123 #define UMCCH0_0_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
124 #define UMCCH0_0_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
125 #define UMCCH0_0_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
126 //UMCCH0_0_AddrHashBank2
127 #define UMCCH0_0_AddrHashBank2__XorEnable__SHIFT                                                              0x0
128 #define UMCCH0_0_AddrHashBank2__ColXor__SHIFT                                                                 0x1
129 #define UMCCH0_0_AddrHashBank2__RowXor__SHIFT                                                                 0xe
130 #define UMCCH0_0_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
131 #define UMCCH0_0_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
132 #define UMCCH0_0_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
133 //UMCCH0_0_AddrHashBank3
134 #define UMCCH0_0_AddrHashBank3__XorEnable__SHIFT                                                              0x0
135 #define UMCCH0_0_AddrHashBank3__ColXor__SHIFT                                                                 0x1
136 #define UMCCH0_0_AddrHashBank3__RowXor__SHIFT                                                                 0xe
137 #define UMCCH0_0_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
138 #define UMCCH0_0_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
139 #define UMCCH0_0_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
140 //UMCCH0_0_AddrHashBank4
141 #define UMCCH0_0_AddrHashBank4__XorEnable__SHIFT                                                              0x0
142 #define UMCCH0_0_AddrHashBank4__ColXor__SHIFT                                                                 0x1
143 #define UMCCH0_0_AddrHashBank4__RowXor__SHIFT                                                                 0xe
144 #define UMCCH0_0_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
145 #define UMCCH0_0_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
146 #define UMCCH0_0_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
147 //UMCCH0_0_AddrHashBank5
148 #define UMCCH0_0_AddrHashBank5__XorEnable__SHIFT                                                              0x0
149 #define UMCCH0_0_AddrHashBank5__ColXor__SHIFT                                                                 0x1
150 #define UMCCH0_0_AddrHashBank5__RowXor__SHIFT                                                                 0xe
151 #define UMCCH0_0_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
152 #define UMCCH0_0_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
153 #define UMCCH0_0_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
154 //UMCCH0_0_UMC_CONFIG
155 #define UMCCH0_0_UMC_CONFIG__DDR_TYPE__SHIFT                                                                  0x0
156 #define UMCCH0_0_UMC_CONFIG__BurstLength__SHIFT                                                               0x8
157 #define UMCCH0_0_UMC_CONFIG__BurstCtrl__SHIFT                                                                 0xa
158 #define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT                                                                 0x1f
159 #define UMCCH0_0_UMC_CONFIG__DDR_TYPE_MASK                                                                    0x00000007L
160 #define UMCCH0_0_UMC_CONFIG__BurstLength_MASK                                                                 0x00000300L
161 #define UMCCH0_0_UMC_CONFIG__BurstCtrl_MASK                                                                   0x00000C00L
162 #define UMCCH0_0_UMC_CONFIG__DramReady_MASK                                                                   0x80000000L
163 //UMCCH0_0_EccCtrl
164 #define UMCCH0_0_EccCtrl__WrEccEn__SHIFT                                                                      0x0
165 #define UMCCH0_0_EccCtrl__EccReplayEn__SHIFT                                                                  0x1
166 #define UMCCH0_0_EccCtrl__UCFatalEn__SHIFT                                                                    0x8
167 #define UMCCH0_0_EccCtrl__RdEccEn__SHIFT                                                                      0xa
168 #define UMCCH0_0_EccCtrl__PoisonFatalDis__SHIFT                                                               0xc
169 #define UMCCH0_0_EccCtrl__PoisonInhibit__SHIFT                                                                0xd
170 #define UMCCH0_0_EccCtrl__WrEccEn_MASK                                                                        0x00000001L
171 #define UMCCH0_0_EccCtrl__EccReplayEn_MASK                                                                    0x00000002L
172 #define UMCCH0_0_EccCtrl__UCFatalEn_MASK                                                                      0x00000100L
173 #define UMCCH0_0_EccCtrl__RdEccEn_MASK                                                                        0x00000400L
174 #define UMCCH0_0_EccCtrl__PoisonFatalDis_MASK                                                                 0x00001000L
175 #define UMCCH0_0_EccCtrl__PoisonInhibit_MASK                                                                  0x00002000L
176 //UMCCH0_0_UmcLocalCap
177 #define UMCCH0_0_UmcLocalCap__EccDis__SHIFT                                                                   0x0
178 #define UMCCH0_0_UmcLocalCap__Spare__SHIFT                                                                    0x1
179 #define UMCCH0_0_UmcLocalCap__WrDis__SHIFT                                                                    0x1f
180 #define UMCCH0_0_UmcLocalCap__EccDis_MASK                                                                     0x00000001L
181 #define UMCCH0_0_UmcLocalCap__Spare_MASK                                                                      0x0000003EL
182 #define UMCCH0_0_UmcLocalCap__WrDis_MASK                                                                      0x80000000L
183 //UMCCH0_0_EccErrCntSel
184 #define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
185 #define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
186 #define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
187 #define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
188 #define UMCCH0_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
189 #define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
190 //UMCCH0_0_EccErrCnt
191 #define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
192 #define UMCCH0_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
193 //UMCCH0_0_PerfMonCtlClk
194 #define UMCCH0_0_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
195 #define UMCCH0_0_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
196 #define UMCCH0_0_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
197 #define UMCCH0_0_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
198 #define UMCCH0_0_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
199 #define UMCCH0_0_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
200 #define UMCCH0_0_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
201 #define UMCCH0_0_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
202 #define UMCCH0_0_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
203 #define UMCCH0_0_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
204 #define UMCCH0_0_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
205 #define UMCCH0_0_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
206 //UMCCH0_0_PerfMonCtrClk_Lo
207 #define UMCCH0_0_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
208 #define UMCCH0_0_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
209 //UMCCH0_0_PerfMonCtrClk_Hi
210 #define UMCCH0_0_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
211 #define UMCCH0_0_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
212 #define UMCCH0_0_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
213 #define UMCCH0_0_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
214 //UMCCH0_0_PerfMonCtl1
215 #define UMCCH0_0_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
216 #define UMCCH0_0_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
217 #define UMCCH0_0_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
218 #define UMCCH0_0_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
219 #define UMCCH0_0_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
220 #define UMCCH0_0_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
221 #define UMCCH0_0_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
222 #define UMCCH0_0_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
223 #define UMCCH0_0_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
224 #define UMCCH0_0_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
225 #define UMCCH0_0_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
226 #define UMCCH0_0_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
227 #define UMCCH0_0_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
228 #define UMCCH0_0_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
229 #define UMCCH0_0_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
230 #define UMCCH0_0_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
231 //UMCCH0_0_PerfMonCtr1_Lo
232 #define UMCCH0_0_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
233 #define UMCCH0_0_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
234 //UMCCH0_0_PerfMonCtr1_Hi
235 #define UMCCH0_0_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
236 #define UMCCH0_0_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
237 #define UMCCH0_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
238 #define UMCCH0_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
239 #define UMCCH0_0_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
240 #define UMCCH0_0_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
241 #define UMCCH0_0_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
242 #define UMCCH0_0_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
243 //UMCCH0_0_PerfMonCtl2
244 #define UMCCH0_0_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
245 #define UMCCH0_0_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
246 #define UMCCH0_0_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
247 #define UMCCH0_0_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
248 #define UMCCH0_0_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
249 #define UMCCH0_0_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
250 #define UMCCH0_0_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
251 #define UMCCH0_0_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
252 #define UMCCH0_0_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
253 #define UMCCH0_0_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
254 #define UMCCH0_0_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
255 #define UMCCH0_0_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
256 #define UMCCH0_0_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
257 #define UMCCH0_0_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
258 #define UMCCH0_0_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
259 #define UMCCH0_0_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
260 //UMCCH0_0_PerfMonCtr2_Lo
261 #define UMCCH0_0_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
262 #define UMCCH0_0_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
263 //UMCCH0_0_PerfMonCtr2_Hi
264 #define UMCCH0_0_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
265 #define UMCCH0_0_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
266 #define UMCCH0_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
267 #define UMCCH0_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
268 #define UMCCH0_0_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
269 #define UMCCH0_0_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
270 #define UMCCH0_0_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
271 #define UMCCH0_0_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
272 //UMCCH0_0_PerfMonCtl3
273 #define UMCCH0_0_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
274 #define UMCCH0_0_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
275 #define UMCCH0_0_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
276 #define UMCCH0_0_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
277 #define UMCCH0_0_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
278 #define UMCCH0_0_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
279 #define UMCCH0_0_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
280 #define UMCCH0_0_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
281 #define UMCCH0_0_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
282 #define UMCCH0_0_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
283 #define UMCCH0_0_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
284 #define UMCCH0_0_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
285 #define UMCCH0_0_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
286 #define UMCCH0_0_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
287 #define UMCCH0_0_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
288 #define UMCCH0_0_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
289 //UMCCH0_0_PerfMonCtr3_Lo
290 #define UMCCH0_0_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
291 #define UMCCH0_0_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
292 //UMCCH0_0_PerfMonCtr3_Hi
293 #define UMCCH0_0_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
294 #define UMCCH0_0_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
295 #define UMCCH0_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
296 #define UMCCH0_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
297 #define UMCCH0_0_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
298 #define UMCCH0_0_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
299 #define UMCCH0_0_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
300 #define UMCCH0_0_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
301 //UMCCH0_0_PerfMonCtl4
302 #define UMCCH0_0_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
303 #define UMCCH0_0_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
304 #define UMCCH0_0_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
305 #define UMCCH0_0_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
306 #define UMCCH0_0_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
307 #define UMCCH0_0_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
308 #define UMCCH0_0_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
309 #define UMCCH0_0_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
310 #define UMCCH0_0_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
311 #define UMCCH0_0_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
312 #define UMCCH0_0_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
313 #define UMCCH0_0_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
314 #define UMCCH0_0_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
315 #define UMCCH0_0_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
316 #define UMCCH0_0_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
317 #define UMCCH0_0_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
318 //UMCCH0_0_PerfMonCtr4_Lo
319 #define UMCCH0_0_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
320 #define UMCCH0_0_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
321 //UMCCH0_0_PerfMonCtr4_Hi
322 #define UMCCH0_0_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
323 #define UMCCH0_0_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
324 #define UMCCH0_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
325 #define UMCCH0_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
326 #define UMCCH0_0_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
327 #define UMCCH0_0_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
328 #define UMCCH0_0_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
329 #define UMCCH0_0_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
330 //UMCCH0_0_PerfMonCtl5
331 #define UMCCH0_0_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
332 #define UMCCH0_0_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
333 #define UMCCH0_0_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
334 #define UMCCH0_0_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
335 #define UMCCH0_0_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
336 #define UMCCH0_0_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
337 #define UMCCH0_0_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
338 #define UMCCH0_0_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
339 #define UMCCH0_0_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
340 #define UMCCH0_0_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
341 #define UMCCH0_0_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
342 #define UMCCH0_0_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
343 #define UMCCH0_0_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
344 #define UMCCH0_0_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
345 #define UMCCH0_0_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
346 #define UMCCH0_0_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
347 //UMCCH0_0_PerfMonCtr5_Lo
348 #define UMCCH0_0_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
349 #define UMCCH0_0_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
350 //UMCCH0_0_PerfMonCtr5_Hi
351 #define UMCCH0_0_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
352 #define UMCCH0_0_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
353 #define UMCCH0_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
354 #define UMCCH0_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
355 #define UMCCH0_0_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
356 #define UMCCH0_0_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
357 #define UMCCH0_0_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
358 #define UMCCH0_0_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
359 //UMCCH0_0_PerfMonCtl6
360 #define UMCCH0_0_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
361 #define UMCCH0_0_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
362 #define UMCCH0_0_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
363 #define UMCCH0_0_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
364 #define UMCCH0_0_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
365 #define UMCCH0_0_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
366 #define UMCCH0_0_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
367 #define UMCCH0_0_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
368 #define UMCCH0_0_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
369 #define UMCCH0_0_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
370 #define UMCCH0_0_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
371 #define UMCCH0_0_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
372 #define UMCCH0_0_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
373 #define UMCCH0_0_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
374 #define UMCCH0_0_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
375 #define UMCCH0_0_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
376 //UMCCH0_0_PerfMonCtr6_Lo
377 #define UMCCH0_0_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
378 #define UMCCH0_0_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
379 //UMCCH0_0_PerfMonCtr6_Hi
380 #define UMCCH0_0_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
381 #define UMCCH0_0_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
382 #define UMCCH0_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
383 #define UMCCH0_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
384 #define UMCCH0_0_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
385 #define UMCCH0_0_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
386 #define UMCCH0_0_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
387 #define UMCCH0_0_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
388 //UMCCH0_0_PerfMonCtl7
389 #define UMCCH0_0_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
390 #define UMCCH0_0_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
391 #define UMCCH0_0_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
392 #define UMCCH0_0_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
393 #define UMCCH0_0_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
394 #define UMCCH0_0_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
395 #define UMCCH0_0_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
396 #define UMCCH0_0_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
397 #define UMCCH0_0_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
398 #define UMCCH0_0_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
399 #define UMCCH0_0_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
400 #define UMCCH0_0_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
401 #define UMCCH0_0_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
402 #define UMCCH0_0_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
403 #define UMCCH0_0_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
404 #define UMCCH0_0_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
405 //UMCCH0_0_PerfMonCtr7_Lo
406 #define UMCCH0_0_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
407 #define UMCCH0_0_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
408 //UMCCH0_0_PerfMonCtr7_Hi
409 #define UMCCH0_0_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
410 #define UMCCH0_0_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
411 #define UMCCH0_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
412 #define UMCCH0_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
413 #define UMCCH0_0_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
414 #define UMCCH0_0_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
415 #define UMCCH0_0_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
416 #define UMCCH0_0_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
417 //UMCCH0_0_PerfMonCtl8
418 #define UMCCH0_0_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
419 #define UMCCH0_0_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
420 #define UMCCH0_0_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
421 #define UMCCH0_0_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
422 #define UMCCH0_0_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
423 #define UMCCH0_0_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
424 #define UMCCH0_0_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
425 #define UMCCH0_0_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
426 #define UMCCH0_0_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
427 #define UMCCH0_0_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
428 #define UMCCH0_0_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
429 #define UMCCH0_0_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
430 #define UMCCH0_0_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
431 #define UMCCH0_0_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
432 #define UMCCH0_0_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
433 #define UMCCH0_0_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
434 //UMCCH0_0_PerfMonCtr8_Lo
435 #define UMCCH0_0_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
436 #define UMCCH0_0_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
437 //UMCCH0_0_PerfMonCtr8_Hi
438 #define UMCCH0_0_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
439 #define UMCCH0_0_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
440 #define UMCCH0_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
441 #define UMCCH0_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
442 #define UMCCH0_0_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
443 #define UMCCH0_0_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
444 #define UMCCH0_0_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
445 #define UMCCH0_0_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
446 
447 
448 // addressBlock: umc_w_phy_umc0_umcch1_umcchdec
449 //UMCCH1_0_BaseAddrCS0
450 #define UMCCH1_0_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
451 #define UMCCH1_0_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
452 #define UMCCH1_0_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
453 #define UMCCH1_0_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
454 //UMCCH1_0_AddrMaskCS01
455 #define UMCCH1_0_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
456 #define UMCCH1_0_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
457 //UMCCH1_0_AddrSelCS01
458 #define UMCCH1_0_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
459 #define UMCCH1_0_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
460 #define UMCCH1_0_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
461 #define UMCCH1_0_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
462 #define UMCCH1_0_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
463 #define UMCCH1_0_AddrSelCS01__RowLo__SHIFT                                                                    0x18
464 #define UMCCH1_0_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
465 #define UMCCH1_0_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
466 #define UMCCH1_0_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
467 #define UMCCH1_0_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
468 #define UMCCH1_0_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
469 #define UMCCH1_0_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
470 #define UMCCH1_0_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
471 #define UMCCH1_0_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
472 //UMCCH1_0_AddrHashBank0
473 #define UMCCH1_0_AddrHashBank0__XorEnable__SHIFT                                                              0x0
474 #define UMCCH1_0_AddrHashBank0__ColXor__SHIFT                                                                 0x1
475 #define UMCCH1_0_AddrHashBank0__RowXor__SHIFT                                                                 0xe
476 #define UMCCH1_0_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
477 #define UMCCH1_0_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
478 #define UMCCH1_0_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
479 //UMCCH1_0_AddrHashBank1
480 #define UMCCH1_0_AddrHashBank1__XorEnable__SHIFT                                                              0x0
481 #define UMCCH1_0_AddrHashBank1__ColXor__SHIFT                                                                 0x1
482 #define UMCCH1_0_AddrHashBank1__RowXor__SHIFT                                                                 0xe
483 #define UMCCH1_0_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
484 #define UMCCH1_0_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
485 #define UMCCH1_0_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
486 //UMCCH1_0_AddrHashBank2
487 #define UMCCH1_0_AddrHashBank2__XorEnable__SHIFT                                                              0x0
488 #define UMCCH1_0_AddrHashBank2__ColXor__SHIFT                                                                 0x1
489 #define UMCCH1_0_AddrHashBank2__RowXor__SHIFT                                                                 0xe
490 #define UMCCH1_0_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
491 #define UMCCH1_0_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
492 #define UMCCH1_0_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
493 //UMCCH1_0_AddrHashBank3
494 #define UMCCH1_0_AddrHashBank3__XorEnable__SHIFT                                                              0x0
495 #define UMCCH1_0_AddrHashBank3__ColXor__SHIFT                                                                 0x1
496 #define UMCCH1_0_AddrHashBank3__RowXor__SHIFT                                                                 0xe
497 #define UMCCH1_0_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
498 #define UMCCH1_0_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
499 #define UMCCH1_0_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
500 //UMCCH1_0_AddrHashBank4
501 #define UMCCH1_0_AddrHashBank4__XorEnable__SHIFT                                                              0x0
502 #define UMCCH1_0_AddrHashBank4__ColXor__SHIFT                                                                 0x1
503 #define UMCCH1_0_AddrHashBank4__RowXor__SHIFT                                                                 0xe
504 #define UMCCH1_0_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
505 #define UMCCH1_0_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
506 #define UMCCH1_0_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
507 //UMCCH1_0_AddrHashBank5
508 #define UMCCH1_0_AddrHashBank5__XorEnable__SHIFT                                                              0x0
509 #define UMCCH1_0_AddrHashBank5__ColXor__SHIFT                                                                 0x1
510 #define UMCCH1_0_AddrHashBank5__RowXor__SHIFT                                                                 0xe
511 #define UMCCH1_0_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
512 #define UMCCH1_0_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
513 #define UMCCH1_0_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
514 //UMCCH1_0_UMC_CONFIG
515 #define UMCCH1_0_UMC_CONFIG__DDR_TYPE__SHIFT                                                                  0x0
516 #define UMCCH1_0_UMC_CONFIG__BurstLength__SHIFT                                                               0x8
517 #define UMCCH1_0_UMC_CONFIG__BurstCtrl__SHIFT                                                                 0xa
518 #define UMCCH1_0_UMC_CONFIG__DramReady__SHIFT                                                                 0x1f
519 #define UMCCH1_0_UMC_CONFIG__DDR_TYPE_MASK                                                                    0x00000007L
520 #define UMCCH1_0_UMC_CONFIG__BurstLength_MASK                                                                 0x00000300L
521 #define UMCCH1_0_UMC_CONFIG__BurstCtrl_MASK                                                                   0x00000C00L
522 #define UMCCH1_0_UMC_CONFIG__DramReady_MASK                                                                   0x80000000L
523 //UMCCH1_0_EccCtrl
524 #define UMCCH1_0_EccCtrl__WrEccEn__SHIFT                                                                      0x0
525 #define UMCCH1_0_EccCtrl__EccReplayEn__SHIFT                                                                  0x1
526 #define UMCCH1_0_EccCtrl__UCFatalEn__SHIFT                                                                    0x8
527 #define UMCCH1_0_EccCtrl__RdEccEn__SHIFT                                                                      0xa
528 #define UMCCH1_0_EccCtrl__PoisonFatalDis__SHIFT                                                               0xc
529 #define UMCCH1_0_EccCtrl__PoisonInhibit__SHIFT                                                                0xd
530 #define UMCCH1_0_EccCtrl__WrEccEn_MASK                                                                        0x00000001L
531 #define UMCCH1_0_EccCtrl__EccReplayEn_MASK                                                                    0x00000002L
532 #define UMCCH1_0_EccCtrl__UCFatalEn_MASK                                                                      0x00000100L
533 #define UMCCH1_0_EccCtrl__RdEccEn_MASK                                                                        0x00000400L
534 #define UMCCH1_0_EccCtrl__PoisonFatalDis_MASK                                                                 0x00001000L
535 #define UMCCH1_0_EccCtrl__PoisonInhibit_MASK                                                                  0x00002000L
536 //UMCCH1_0_UmcLocalCap
537 #define UMCCH1_0_UmcLocalCap__EccDis__SHIFT                                                                   0x0
538 #define UMCCH1_0_UmcLocalCap__Spare__SHIFT                                                                    0x1
539 #define UMCCH1_0_UmcLocalCap__WrDis__SHIFT                                                                    0x1f
540 #define UMCCH1_0_UmcLocalCap__EccDis_MASK                                                                     0x00000001L
541 #define UMCCH1_0_UmcLocalCap__Spare_MASK                                                                      0x0000003EL
542 #define UMCCH1_0_UmcLocalCap__WrDis_MASK                                                                      0x80000000L
543 //UMCCH1_0_EccErrCntSel
544 #define UMCCH1_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
545 #define UMCCH1_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
546 #define UMCCH1_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
547 #define UMCCH1_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
548 #define UMCCH1_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
549 #define UMCCH1_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
550 //UMCCH1_0_EccErrCnt
551 #define UMCCH1_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
552 #define UMCCH1_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
553 //UMCCH1_0_PerfMonCtlClk
554 #define UMCCH1_0_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
555 #define UMCCH1_0_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
556 #define UMCCH1_0_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
557 #define UMCCH1_0_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
558 #define UMCCH1_0_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
559 #define UMCCH1_0_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
560 #define UMCCH1_0_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
561 #define UMCCH1_0_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
562 #define UMCCH1_0_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
563 #define UMCCH1_0_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
564 #define UMCCH1_0_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
565 #define UMCCH1_0_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
566 //UMCCH1_0_PerfMonCtrClk_Lo
567 #define UMCCH1_0_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
568 #define UMCCH1_0_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
569 //UMCCH1_0_PerfMonCtrClk_Hi
570 #define UMCCH1_0_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
571 #define UMCCH1_0_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
572 #define UMCCH1_0_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
573 #define UMCCH1_0_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
574 //UMCCH1_0_PerfMonCtl1
575 #define UMCCH1_0_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
576 #define UMCCH1_0_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
577 #define UMCCH1_0_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
578 #define UMCCH1_0_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
579 #define UMCCH1_0_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
580 #define UMCCH1_0_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
581 #define UMCCH1_0_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
582 #define UMCCH1_0_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
583 #define UMCCH1_0_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
584 #define UMCCH1_0_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
585 #define UMCCH1_0_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
586 #define UMCCH1_0_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
587 #define UMCCH1_0_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
588 #define UMCCH1_0_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
589 #define UMCCH1_0_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
590 #define UMCCH1_0_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
591 //UMCCH1_0_PerfMonCtr1_Lo
592 #define UMCCH1_0_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
593 #define UMCCH1_0_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
594 //UMCCH1_0_PerfMonCtr1_Hi
595 #define UMCCH1_0_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
596 #define UMCCH1_0_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
597 #define UMCCH1_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
598 #define UMCCH1_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
599 #define UMCCH1_0_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
600 #define UMCCH1_0_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
601 #define UMCCH1_0_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
602 #define UMCCH1_0_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
603 //UMCCH1_0_PerfMonCtl2
604 #define UMCCH1_0_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
605 #define UMCCH1_0_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
606 #define UMCCH1_0_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
607 #define UMCCH1_0_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
608 #define UMCCH1_0_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
609 #define UMCCH1_0_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
610 #define UMCCH1_0_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
611 #define UMCCH1_0_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
612 #define UMCCH1_0_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
613 #define UMCCH1_0_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
614 #define UMCCH1_0_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
615 #define UMCCH1_0_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
616 #define UMCCH1_0_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
617 #define UMCCH1_0_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
618 #define UMCCH1_0_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
619 #define UMCCH1_0_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
620 //UMCCH1_0_PerfMonCtr2_Lo
621 #define UMCCH1_0_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
622 #define UMCCH1_0_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
623 //UMCCH1_0_PerfMonCtr2_Hi
624 #define UMCCH1_0_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
625 #define UMCCH1_0_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
626 #define UMCCH1_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
627 #define UMCCH1_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
628 #define UMCCH1_0_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
629 #define UMCCH1_0_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
630 #define UMCCH1_0_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
631 #define UMCCH1_0_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
632 //UMCCH1_0_PerfMonCtl3
633 #define UMCCH1_0_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
634 #define UMCCH1_0_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
635 #define UMCCH1_0_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
636 #define UMCCH1_0_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
637 #define UMCCH1_0_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
638 #define UMCCH1_0_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
639 #define UMCCH1_0_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
640 #define UMCCH1_0_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
641 #define UMCCH1_0_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
642 #define UMCCH1_0_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
643 #define UMCCH1_0_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
644 #define UMCCH1_0_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
645 #define UMCCH1_0_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
646 #define UMCCH1_0_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
647 #define UMCCH1_0_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
648 #define UMCCH1_0_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
649 //UMCCH1_0_PerfMonCtr3_Lo
650 #define UMCCH1_0_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
651 #define UMCCH1_0_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
652 //UMCCH1_0_PerfMonCtr3_Hi
653 #define UMCCH1_0_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
654 #define UMCCH1_0_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
655 #define UMCCH1_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
656 #define UMCCH1_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
657 #define UMCCH1_0_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
658 #define UMCCH1_0_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
659 #define UMCCH1_0_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
660 #define UMCCH1_0_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
661 //UMCCH1_0_PerfMonCtl4
662 #define UMCCH1_0_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
663 #define UMCCH1_0_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
664 #define UMCCH1_0_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
665 #define UMCCH1_0_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
666 #define UMCCH1_0_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
667 #define UMCCH1_0_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
668 #define UMCCH1_0_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
669 #define UMCCH1_0_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
670 #define UMCCH1_0_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
671 #define UMCCH1_0_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
672 #define UMCCH1_0_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
673 #define UMCCH1_0_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
674 #define UMCCH1_0_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
675 #define UMCCH1_0_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
676 #define UMCCH1_0_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
677 #define UMCCH1_0_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
678 //UMCCH1_0_PerfMonCtr4_Lo
679 #define UMCCH1_0_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
680 #define UMCCH1_0_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
681 //UMCCH1_0_PerfMonCtr4_Hi
682 #define UMCCH1_0_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
683 #define UMCCH1_0_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
684 #define UMCCH1_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
685 #define UMCCH1_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
686 #define UMCCH1_0_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
687 #define UMCCH1_0_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
688 #define UMCCH1_0_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
689 #define UMCCH1_0_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
690 //UMCCH1_0_PerfMonCtl5
691 #define UMCCH1_0_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
692 #define UMCCH1_0_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
693 #define UMCCH1_0_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
694 #define UMCCH1_0_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
695 #define UMCCH1_0_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
696 #define UMCCH1_0_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
697 #define UMCCH1_0_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
698 #define UMCCH1_0_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
699 #define UMCCH1_0_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
700 #define UMCCH1_0_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
701 #define UMCCH1_0_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
702 #define UMCCH1_0_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
703 #define UMCCH1_0_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
704 #define UMCCH1_0_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
705 #define UMCCH1_0_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
706 #define UMCCH1_0_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
707 //UMCCH1_0_PerfMonCtr5_Lo
708 #define UMCCH1_0_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
709 #define UMCCH1_0_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
710 //UMCCH1_0_PerfMonCtr5_Hi
711 #define UMCCH1_0_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
712 #define UMCCH1_0_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
713 #define UMCCH1_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
714 #define UMCCH1_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
715 #define UMCCH1_0_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
716 #define UMCCH1_0_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
717 #define UMCCH1_0_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
718 #define UMCCH1_0_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
719 //UMCCH1_0_PerfMonCtl6
720 #define UMCCH1_0_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
721 #define UMCCH1_0_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
722 #define UMCCH1_0_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
723 #define UMCCH1_0_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
724 #define UMCCH1_0_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
725 #define UMCCH1_0_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
726 #define UMCCH1_0_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
727 #define UMCCH1_0_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
728 #define UMCCH1_0_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
729 #define UMCCH1_0_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
730 #define UMCCH1_0_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
731 #define UMCCH1_0_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
732 #define UMCCH1_0_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
733 #define UMCCH1_0_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
734 #define UMCCH1_0_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
735 #define UMCCH1_0_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
736 //UMCCH1_0_PerfMonCtr6_Lo
737 #define UMCCH1_0_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
738 #define UMCCH1_0_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
739 //UMCCH1_0_PerfMonCtr6_Hi
740 #define UMCCH1_0_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
741 #define UMCCH1_0_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
742 #define UMCCH1_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
743 #define UMCCH1_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
744 #define UMCCH1_0_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
745 #define UMCCH1_0_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
746 #define UMCCH1_0_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
747 #define UMCCH1_0_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
748 //UMCCH1_0_PerfMonCtl7
749 #define UMCCH1_0_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
750 #define UMCCH1_0_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
751 #define UMCCH1_0_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
752 #define UMCCH1_0_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
753 #define UMCCH1_0_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
754 #define UMCCH1_0_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
755 #define UMCCH1_0_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
756 #define UMCCH1_0_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
757 #define UMCCH1_0_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
758 #define UMCCH1_0_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
759 #define UMCCH1_0_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
760 #define UMCCH1_0_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
761 #define UMCCH1_0_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
762 #define UMCCH1_0_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
763 #define UMCCH1_0_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
764 #define UMCCH1_0_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
765 //UMCCH1_0_PerfMonCtr7_Lo
766 #define UMCCH1_0_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
767 #define UMCCH1_0_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
768 //UMCCH1_0_PerfMonCtr7_Hi
769 #define UMCCH1_0_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
770 #define UMCCH1_0_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
771 #define UMCCH1_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
772 #define UMCCH1_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
773 #define UMCCH1_0_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
774 #define UMCCH1_0_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
775 #define UMCCH1_0_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
776 #define UMCCH1_0_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
777 //UMCCH1_0_PerfMonCtl8
778 #define UMCCH1_0_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
779 #define UMCCH1_0_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
780 #define UMCCH1_0_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
781 #define UMCCH1_0_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
782 #define UMCCH1_0_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
783 #define UMCCH1_0_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
784 #define UMCCH1_0_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
785 #define UMCCH1_0_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
786 #define UMCCH1_0_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
787 #define UMCCH1_0_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
788 #define UMCCH1_0_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
789 #define UMCCH1_0_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
790 #define UMCCH1_0_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
791 #define UMCCH1_0_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
792 #define UMCCH1_0_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
793 #define UMCCH1_0_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
794 //UMCCH1_0_PerfMonCtr8_Lo
795 #define UMCCH1_0_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
796 #define UMCCH1_0_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
797 //UMCCH1_0_PerfMonCtr8_Hi
798 #define UMCCH1_0_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
799 #define UMCCH1_0_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
800 #define UMCCH1_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
801 #define UMCCH1_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
802 #define UMCCH1_0_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
803 #define UMCCH1_0_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
804 #define UMCCH1_0_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
805 #define UMCCH1_0_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
806 
807 
808 // addressBlock: umc_w_phy_umc0_umcch2_umcchdec
809 //UMCCH2_0_BaseAddrCS0
810 #define UMCCH2_0_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
811 #define UMCCH2_0_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
812 #define UMCCH2_0_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
813 #define UMCCH2_0_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
814 //UMCCH2_0_AddrMaskCS01
815 #define UMCCH2_0_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
816 #define UMCCH2_0_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
817 //UMCCH2_0_AddrSelCS01
818 #define UMCCH2_0_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
819 #define UMCCH2_0_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
820 #define UMCCH2_0_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
821 #define UMCCH2_0_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
822 #define UMCCH2_0_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
823 #define UMCCH2_0_AddrSelCS01__RowLo__SHIFT                                                                    0x18
824 #define UMCCH2_0_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
825 #define UMCCH2_0_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
826 #define UMCCH2_0_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
827 #define UMCCH2_0_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
828 #define UMCCH2_0_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
829 #define UMCCH2_0_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
830 #define UMCCH2_0_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
831 #define UMCCH2_0_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
832 //UMCCH2_0_AddrHashBank0
833 #define UMCCH2_0_AddrHashBank0__XorEnable__SHIFT                                                              0x0
834 #define UMCCH2_0_AddrHashBank0__ColXor__SHIFT                                                                 0x1
835 #define UMCCH2_0_AddrHashBank0__RowXor__SHIFT                                                                 0xe
836 #define UMCCH2_0_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
837 #define UMCCH2_0_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
838 #define UMCCH2_0_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
839 //UMCCH2_0_AddrHashBank1
840 #define UMCCH2_0_AddrHashBank1__XorEnable__SHIFT                                                              0x0
841 #define UMCCH2_0_AddrHashBank1__ColXor__SHIFT                                                                 0x1
842 #define UMCCH2_0_AddrHashBank1__RowXor__SHIFT                                                                 0xe
843 #define UMCCH2_0_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
844 #define UMCCH2_0_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
845 #define UMCCH2_0_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
846 //UMCCH2_0_AddrHashBank2
847 #define UMCCH2_0_AddrHashBank2__XorEnable__SHIFT                                                              0x0
848 #define UMCCH2_0_AddrHashBank2__ColXor__SHIFT                                                                 0x1
849 #define UMCCH2_0_AddrHashBank2__RowXor__SHIFT                                                                 0xe
850 #define UMCCH2_0_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
851 #define UMCCH2_0_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
852 #define UMCCH2_0_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
853 //UMCCH2_0_AddrHashBank3
854 #define UMCCH2_0_AddrHashBank3__XorEnable__SHIFT                                                              0x0
855 #define UMCCH2_0_AddrHashBank3__ColXor__SHIFT                                                                 0x1
856 #define UMCCH2_0_AddrHashBank3__RowXor__SHIFT                                                                 0xe
857 #define UMCCH2_0_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
858 #define UMCCH2_0_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
859 #define UMCCH2_0_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
860 //UMCCH2_0_AddrHashBank4
861 #define UMCCH2_0_AddrHashBank4__XorEnable__SHIFT                                                              0x0
862 #define UMCCH2_0_AddrHashBank4__ColXor__SHIFT                                                                 0x1
863 #define UMCCH2_0_AddrHashBank4__RowXor__SHIFT                                                                 0xe
864 #define UMCCH2_0_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
865 #define UMCCH2_0_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
866 #define UMCCH2_0_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
867 //UMCCH2_0_AddrHashBank5
868 #define UMCCH2_0_AddrHashBank5__XorEnable__SHIFT                                                              0x0
869 #define UMCCH2_0_AddrHashBank5__ColXor__SHIFT                                                                 0x1
870 #define UMCCH2_0_AddrHashBank5__RowXor__SHIFT                                                                 0xe
871 #define UMCCH2_0_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
872 #define UMCCH2_0_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
873 #define UMCCH2_0_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
874 //UMCCH2_0_UMC_CONFIG
875 #define UMCCH2_0_UMC_CONFIG__DDR_TYPE__SHIFT                                                                  0x0
876 #define UMCCH2_0_UMC_CONFIG__BurstLength__SHIFT                                                               0x8
877 #define UMCCH2_0_UMC_CONFIG__BurstCtrl__SHIFT                                                                 0xa
878 #define UMCCH2_0_UMC_CONFIG__DramReady__SHIFT                                                                 0x1f
879 #define UMCCH2_0_UMC_CONFIG__DDR_TYPE_MASK                                                                    0x00000007L
880 #define UMCCH2_0_UMC_CONFIG__BurstLength_MASK                                                                 0x00000300L
881 #define UMCCH2_0_UMC_CONFIG__BurstCtrl_MASK                                                                   0x00000C00L
882 #define UMCCH2_0_UMC_CONFIG__DramReady_MASK                                                                   0x80000000L
883 //UMCCH2_0_EccCtrl
884 #define UMCCH2_0_EccCtrl__WrEccEn__SHIFT                                                                      0x0
885 #define UMCCH2_0_EccCtrl__EccReplayEn__SHIFT                                                                  0x1
886 #define UMCCH2_0_EccCtrl__UCFatalEn__SHIFT                                                                    0x8
887 #define UMCCH2_0_EccCtrl__RdEccEn__SHIFT                                                                      0xa
888 #define UMCCH2_0_EccCtrl__PoisonFatalDis__SHIFT                                                               0xc
889 #define UMCCH2_0_EccCtrl__PoisonInhibit__SHIFT                                                                0xd
890 #define UMCCH2_0_EccCtrl__WrEccEn_MASK                                                                        0x00000001L
891 #define UMCCH2_0_EccCtrl__EccReplayEn_MASK                                                                    0x00000002L
892 #define UMCCH2_0_EccCtrl__UCFatalEn_MASK                                                                      0x00000100L
893 #define UMCCH2_0_EccCtrl__RdEccEn_MASK                                                                        0x00000400L
894 #define UMCCH2_0_EccCtrl__PoisonFatalDis_MASK                                                                 0x00001000L
895 #define UMCCH2_0_EccCtrl__PoisonInhibit_MASK                                                                  0x00002000L
896 //UMCCH2_0_UmcLocalCap
897 #define UMCCH2_0_UmcLocalCap__EccDis__SHIFT                                                                   0x0
898 #define UMCCH2_0_UmcLocalCap__Spare__SHIFT                                                                    0x1
899 #define UMCCH2_0_UmcLocalCap__WrDis__SHIFT                                                                    0x1f
900 #define UMCCH2_0_UmcLocalCap__EccDis_MASK                                                                     0x00000001L
901 #define UMCCH2_0_UmcLocalCap__Spare_MASK                                                                      0x0000003EL
902 #define UMCCH2_0_UmcLocalCap__WrDis_MASK                                                                      0x80000000L
903 //UMCCH2_0_EccErrCntSel
904 #define UMCCH2_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
905 #define UMCCH2_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
906 #define UMCCH2_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
907 #define UMCCH2_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
908 #define UMCCH2_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
909 #define UMCCH2_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
910 //UMCCH2_0_EccErrCnt
911 #define UMCCH2_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
912 #define UMCCH2_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
913 //UMCCH2_0_PerfMonCtlClk
914 #define UMCCH2_0_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
915 #define UMCCH2_0_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
916 #define UMCCH2_0_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
917 #define UMCCH2_0_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
918 #define UMCCH2_0_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
919 #define UMCCH2_0_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
920 #define UMCCH2_0_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
921 #define UMCCH2_0_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
922 #define UMCCH2_0_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
923 #define UMCCH2_0_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
924 #define UMCCH2_0_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
925 #define UMCCH2_0_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
926 //UMCCH2_0_PerfMonCtrClk_Lo
927 #define UMCCH2_0_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
928 #define UMCCH2_0_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
929 //UMCCH2_0_PerfMonCtrClk_Hi
930 #define UMCCH2_0_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
931 #define UMCCH2_0_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
932 #define UMCCH2_0_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
933 #define UMCCH2_0_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
934 //UMCCH2_0_PerfMonCtl1
935 #define UMCCH2_0_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
936 #define UMCCH2_0_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
937 #define UMCCH2_0_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
938 #define UMCCH2_0_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
939 #define UMCCH2_0_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
940 #define UMCCH2_0_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
941 #define UMCCH2_0_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
942 #define UMCCH2_0_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
943 #define UMCCH2_0_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
944 #define UMCCH2_0_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
945 #define UMCCH2_0_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
946 #define UMCCH2_0_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
947 #define UMCCH2_0_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
948 #define UMCCH2_0_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
949 #define UMCCH2_0_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
950 #define UMCCH2_0_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
951 //UMCCH2_0_PerfMonCtr1_Lo
952 #define UMCCH2_0_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
953 #define UMCCH2_0_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
954 //UMCCH2_0_PerfMonCtr1_Hi
955 #define UMCCH2_0_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
956 #define UMCCH2_0_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
957 #define UMCCH2_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
958 #define UMCCH2_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
959 #define UMCCH2_0_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
960 #define UMCCH2_0_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
961 #define UMCCH2_0_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
962 #define UMCCH2_0_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
963 //UMCCH2_0_PerfMonCtl2
964 #define UMCCH2_0_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
965 #define UMCCH2_0_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
966 #define UMCCH2_0_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
967 #define UMCCH2_0_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
968 #define UMCCH2_0_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
969 #define UMCCH2_0_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
970 #define UMCCH2_0_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
971 #define UMCCH2_0_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
972 #define UMCCH2_0_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
973 #define UMCCH2_0_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
974 #define UMCCH2_0_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
975 #define UMCCH2_0_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
976 #define UMCCH2_0_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
977 #define UMCCH2_0_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
978 #define UMCCH2_0_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
979 #define UMCCH2_0_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
980 //UMCCH2_0_PerfMonCtr2_Lo
981 #define UMCCH2_0_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
982 #define UMCCH2_0_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
983 //UMCCH2_0_PerfMonCtr2_Hi
984 #define UMCCH2_0_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
985 #define UMCCH2_0_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
986 #define UMCCH2_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
987 #define UMCCH2_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
988 #define UMCCH2_0_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
989 #define UMCCH2_0_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
990 #define UMCCH2_0_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
991 #define UMCCH2_0_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
992 //UMCCH2_0_PerfMonCtl3
993 #define UMCCH2_0_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
994 #define UMCCH2_0_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
995 #define UMCCH2_0_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
996 #define UMCCH2_0_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
997 #define UMCCH2_0_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
998 #define UMCCH2_0_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
999 #define UMCCH2_0_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
1000 #define UMCCH2_0_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
1001 #define UMCCH2_0_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
1002 #define UMCCH2_0_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
1003 #define UMCCH2_0_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
1004 #define UMCCH2_0_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
1005 #define UMCCH2_0_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
1006 #define UMCCH2_0_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
1007 #define UMCCH2_0_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
1008 #define UMCCH2_0_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
1009 //UMCCH2_0_PerfMonCtr3_Lo
1010 #define UMCCH2_0_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
1011 #define UMCCH2_0_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
1012 //UMCCH2_0_PerfMonCtr3_Hi
1013 #define UMCCH2_0_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
1014 #define UMCCH2_0_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
1015 #define UMCCH2_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
1016 #define UMCCH2_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
1017 #define UMCCH2_0_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
1018 #define UMCCH2_0_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
1019 #define UMCCH2_0_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1020 #define UMCCH2_0_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1021 //UMCCH2_0_PerfMonCtl4
1022 #define UMCCH2_0_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
1023 #define UMCCH2_0_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
1024 #define UMCCH2_0_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
1025 #define UMCCH2_0_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
1026 #define UMCCH2_0_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
1027 #define UMCCH2_0_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
1028 #define UMCCH2_0_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
1029 #define UMCCH2_0_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
1030 #define UMCCH2_0_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
1031 #define UMCCH2_0_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
1032 #define UMCCH2_0_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
1033 #define UMCCH2_0_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
1034 #define UMCCH2_0_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
1035 #define UMCCH2_0_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
1036 #define UMCCH2_0_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
1037 #define UMCCH2_0_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
1038 //UMCCH2_0_PerfMonCtr4_Lo
1039 #define UMCCH2_0_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
1040 #define UMCCH2_0_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
1041 //UMCCH2_0_PerfMonCtr4_Hi
1042 #define UMCCH2_0_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
1043 #define UMCCH2_0_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
1044 #define UMCCH2_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
1045 #define UMCCH2_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
1046 #define UMCCH2_0_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
1047 #define UMCCH2_0_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
1048 #define UMCCH2_0_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1049 #define UMCCH2_0_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1050 //UMCCH2_0_PerfMonCtl5
1051 #define UMCCH2_0_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
1052 #define UMCCH2_0_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
1053 #define UMCCH2_0_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
1054 #define UMCCH2_0_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
1055 #define UMCCH2_0_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
1056 #define UMCCH2_0_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
1057 #define UMCCH2_0_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
1058 #define UMCCH2_0_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
1059 #define UMCCH2_0_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
1060 #define UMCCH2_0_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
1061 #define UMCCH2_0_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
1062 #define UMCCH2_0_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
1063 #define UMCCH2_0_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
1064 #define UMCCH2_0_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
1065 #define UMCCH2_0_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
1066 #define UMCCH2_0_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
1067 //UMCCH2_0_PerfMonCtr5_Lo
1068 #define UMCCH2_0_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
1069 #define UMCCH2_0_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
1070 //UMCCH2_0_PerfMonCtr5_Hi
1071 #define UMCCH2_0_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
1072 #define UMCCH2_0_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
1073 #define UMCCH2_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
1074 #define UMCCH2_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
1075 #define UMCCH2_0_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
1076 #define UMCCH2_0_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
1077 #define UMCCH2_0_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1078 #define UMCCH2_0_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1079 //UMCCH2_0_PerfMonCtl6
1080 #define UMCCH2_0_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
1081 #define UMCCH2_0_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
1082 #define UMCCH2_0_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
1083 #define UMCCH2_0_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
1084 #define UMCCH2_0_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
1085 #define UMCCH2_0_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
1086 #define UMCCH2_0_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
1087 #define UMCCH2_0_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
1088 #define UMCCH2_0_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
1089 #define UMCCH2_0_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
1090 #define UMCCH2_0_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
1091 #define UMCCH2_0_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
1092 #define UMCCH2_0_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
1093 #define UMCCH2_0_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
1094 #define UMCCH2_0_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
1095 #define UMCCH2_0_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
1096 //UMCCH2_0_PerfMonCtr6_Lo
1097 #define UMCCH2_0_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
1098 #define UMCCH2_0_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
1099 //UMCCH2_0_PerfMonCtr6_Hi
1100 #define UMCCH2_0_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
1101 #define UMCCH2_0_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
1102 #define UMCCH2_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
1103 #define UMCCH2_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
1104 #define UMCCH2_0_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
1105 #define UMCCH2_0_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
1106 #define UMCCH2_0_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1107 #define UMCCH2_0_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1108 //UMCCH2_0_PerfMonCtl7
1109 #define UMCCH2_0_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
1110 #define UMCCH2_0_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
1111 #define UMCCH2_0_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
1112 #define UMCCH2_0_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
1113 #define UMCCH2_0_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
1114 #define UMCCH2_0_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
1115 #define UMCCH2_0_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
1116 #define UMCCH2_0_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
1117 #define UMCCH2_0_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
1118 #define UMCCH2_0_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
1119 #define UMCCH2_0_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
1120 #define UMCCH2_0_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
1121 #define UMCCH2_0_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
1122 #define UMCCH2_0_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
1123 #define UMCCH2_0_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
1124 #define UMCCH2_0_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
1125 //UMCCH2_0_PerfMonCtr7_Lo
1126 #define UMCCH2_0_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
1127 #define UMCCH2_0_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
1128 //UMCCH2_0_PerfMonCtr7_Hi
1129 #define UMCCH2_0_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
1130 #define UMCCH2_0_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
1131 #define UMCCH2_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
1132 #define UMCCH2_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
1133 #define UMCCH2_0_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
1134 #define UMCCH2_0_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
1135 #define UMCCH2_0_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1136 #define UMCCH2_0_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1137 //UMCCH2_0_PerfMonCtl8
1138 #define UMCCH2_0_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
1139 #define UMCCH2_0_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
1140 #define UMCCH2_0_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
1141 #define UMCCH2_0_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
1142 #define UMCCH2_0_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
1143 #define UMCCH2_0_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
1144 #define UMCCH2_0_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
1145 #define UMCCH2_0_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
1146 #define UMCCH2_0_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
1147 #define UMCCH2_0_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
1148 #define UMCCH2_0_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
1149 #define UMCCH2_0_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
1150 #define UMCCH2_0_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
1151 #define UMCCH2_0_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
1152 #define UMCCH2_0_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
1153 #define UMCCH2_0_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
1154 //UMCCH2_0_PerfMonCtr8_Lo
1155 #define UMCCH2_0_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
1156 #define UMCCH2_0_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
1157 //UMCCH2_0_PerfMonCtr8_Hi
1158 #define UMCCH2_0_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
1159 #define UMCCH2_0_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
1160 #define UMCCH2_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
1161 #define UMCCH2_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
1162 #define UMCCH2_0_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
1163 #define UMCCH2_0_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
1164 #define UMCCH2_0_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1165 #define UMCCH2_0_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1166 
1167 
1168 // addressBlock: umc_w_phy_umc0_umcch3_umcchdec
1169 //UMCCH3_0_BaseAddrCS0
1170 #define UMCCH3_0_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
1171 #define UMCCH3_0_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
1172 #define UMCCH3_0_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
1173 #define UMCCH3_0_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
1174 //UMCCH3_0_AddrMaskCS01
1175 #define UMCCH3_0_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
1176 #define UMCCH3_0_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
1177 //UMCCH3_0_AddrSelCS01
1178 #define UMCCH3_0_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
1179 #define UMCCH3_0_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
1180 #define UMCCH3_0_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
1181 #define UMCCH3_0_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
1182 #define UMCCH3_0_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
1183 #define UMCCH3_0_AddrSelCS01__RowLo__SHIFT                                                                    0x18
1184 #define UMCCH3_0_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
1185 #define UMCCH3_0_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
1186 #define UMCCH3_0_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
1187 #define UMCCH3_0_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
1188 #define UMCCH3_0_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
1189 #define UMCCH3_0_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
1190 #define UMCCH3_0_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
1191 #define UMCCH3_0_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
1192 //UMCCH3_0_AddrHashBank0
1193 #define UMCCH3_0_AddrHashBank0__XorEnable__SHIFT                                                              0x0
1194 #define UMCCH3_0_AddrHashBank0__ColXor__SHIFT                                                                 0x1
1195 #define UMCCH3_0_AddrHashBank0__RowXor__SHIFT                                                                 0xe
1196 #define UMCCH3_0_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
1197 #define UMCCH3_0_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
1198 #define UMCCH3_0_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
1199 //UMCCH3_0_AddrHashBank1
1200 #define UMCCH3_0_AddrHashBank1__XorEnable__SHIFT                                                              0x0
1201 #define UMCCH3_0_AddrHashBank1__ColXor__SHIFT                                                                 0x1
1202 #define UMCCH3_0_AddrHashBank1__RowXor__SHIFT                                                                 0xe
1203 #define UMCCH3_0_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
1204 #define UMCCH3_0_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
1205 #define UMCCH3_0_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
1206 //UMCCH3_0_AddrHashBank2
1207 #define UMCCH3_0_AddrHashBank2__XorEnable__SHIFT                                                              0x0
1208 #define UMCCH3_0_AddrHashBank2__ColXor__SHIFT                                                                 0x1
1209 #define UMCCH3_0_AddrHashBank2__RowXor__SHIFT                                                                 0xe
1210 #define UMCCH3_0_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
1211 #define UMCCH3_0_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
1212 #define UMCCH3_0_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
1213 //UMCCH3_0_AddrHashBank3
1214 #define UMCCH3_0_AddrHashBank3__XorEnable__SHIFT                                                              0x0
1215 #define UMCCH3_0_AddrHashBank3__ColXor__SHIFT                                                                 0x1
1216 #define UMCCH3_0_AddrHashBank3__RowXor__SHIFT                                                                 0xe
1217 #define UMCCH3_0_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
1218 #define UMCCH3_0_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
1219 #define UMCCH3_0_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
1220 //UMCCH3_0_AddrHashBank4
1221 #define UMCCH3_0_AddrHashBank4__XorEnable__SHIFT                                                              0x0
1222 #define UMCCH3_0_AddrHashBank4__ColXor__SHIFT                                                                 0x1
1223 #define UMCCH3_0_AddrHashBank4__RowXor__SHIFT                                                                 0xe
1224 #define UMCCH3_0_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
1225 #define UMCCH3_0_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
1226 #define UMCCH3_0_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
1227 //UMCCH3_0_AddrHashBank5
1228 #define UMCCH3_0_AddrHashBank5__XorEnable__SHIFT                                                              0x0
1229 #define UMCCH3_0_AddrHashBank5__ColXor__SHIFT                                                                 0x1
1230 #define UMCCH3_0_AddrHashBank5__RowXor__SHIFT                                                                 0xe
1231 #define UMCCH3_0_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
1232 #define UMCCH3_0_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
1233 #define UMCCH3_0_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
1234 //UMCCH3_0_UMC_CONFIG
1235 #define UMCCH3_0_UMC_CONFIG__DDR_TYPE__SHIFT                                                                  0x0
1236 #define UMCCH3_0_UMC_CONFIG__BurstLength__SHIFT                                                               0x8
1237 #define UMCCH3_0_UMC_CONFIG__BurstCtrl__SHIFT                                                                 0xa
1238 #define UMCCH3_0_UMC_CONFIG__DramReady__SHIFT                                                                 0x1f
1239 #define UMCCH3_0_UMC_CONFIG__DDR_TYPE_MASK                                                                    0x00000007L
1240 #define UMCCH3_0_UMC_CONFIG__BurstLength_MASK                                                                 0x00000300L
1241 #define UMCCH3_0_UMC_CONFIG__BurstCtrl_MASK                                                                   0x00000C00L
1242 #define UMCCH3_0_UMC_CONFIG__DramReady_MASK                                                                   0x80000000L
1243 //UMCCH3_0_EccCtrl
1244 #define UMCCH3_0_EccCtrl__WrEccEn__SHIFT                                                                      0x0
1245 #define UMCCH3_0_EccCtrl__EccReplayEn__SHIFT                                                                  0x1
1246 #define UMCCH3_0_EccCtrl__UCFatalEn__SHIFT                                                                    0x8
1247 #define UMCCH3_0_EccCtrl__RdEccEn__SHIFT                                                                      0xa
1248 #define UMCCH3_0_EccCtrl__PoisonFatalDis__SHIFT                                                               0xc
1249 #define UMCCH3_0_EccCtrl__PoisonInhibit__SHIFT                                                                0xd
1250 #define UMCCH3_0_EccCtrl__WrEccEn_MASK                                                                        0x00000001L
1251 #define UMCCH3_0_EccCtrl__EccReplayEn_MASK                                                                    0x00000002L
1252 #define UMCCH3_0_EccCtrl__UCFatalEn_MASK                                                                      0x00000100L
1253 #define UMCCH3_0_EccCtrl__RdEccEn_MASK                                                                        0x00000400L
1254 #define UMCCH3_0_EccCtrl__PoisonFatalDis_MASK                                                                 0x00001000L
1255 #define UMCCH3_0_EccCtrl__PoisonInhibit_MASK                                                                  0x00002000L
1256 //UMCCH3_0_UmcLocalCap
1257 #define UMCCH3_0_UmcLocalCap__EccDis__SHIFT                                                                   0x0
1258 #define UMCCH3_0_UmcLocalCap__Spare__SHIFT                                                                    0x1
1259 #define UMCCH3_0_UmcLocalCap__WrDis__SHIFT                                                                    0x1f
1260 #define UMCCH3_0_UmcLocalCap__EccDis_MASK                                                                     0x00000001L
1261 #define UMCCH3_0_UmcLocalCap__Spare_MASK                                                                      0x0000003EL
1262 #define UMCCH3_0_UmcLocalCap__WrDis_MASK                                                                      0x80000000L
1263 //UMCCH3_0_EccErrCntSel
1264 #define UMCCH3_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
1265 #define UMCCH3_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
1266 #define UMCCH3_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
1267 #define UMCCH3_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
1268 #define UMCCH3_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
1269 #define UMCCH3_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
1270 //UMCCH3_0_EccErrCnt
1271 #define UMCCH3_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
1272 #define UMCCH3_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
1273 //UMCCH3_0_PerfMonCtlClk
1274 #define UMCCH3_0_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
1275 #define UMCCH3_0_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
1276 #define UMCCH3_0_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
1277 #define UMCCH3_0_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
1278 #define UMCCH3_0_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
1279 #define UMCCH3_0_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
1280 #define UMCCH3_0_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
1281 #define UMCCH3_0_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
1282 #define UMCCH3_0_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
1283 #define UMCCH3_0_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
1284 #define UMCCH3_0_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
1285 #define UMCCH3_0_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
1286 //UMCCH3_0_PerfMonCtrClk_Lo
1287 #define UMCCH3_0_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
1288 #define UMCCH3_0_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
1289 //UMCCH3_0_PerfMonCtrClk_Hi
1290 #define UMCCH3_0_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
1291 #define UMCCH3_0_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
1292 #define UMCCH3_0_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
1293 #define UMCCH3_0_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
1294 //UMCCH3_0_PerfMonCtl1
1295 #define UMCCH3_0_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
1296 #define UMCCH3_0_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
1297 #define UMCCH3_0_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
1298 #define UMCCH3_0_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
1299 #define UMCCH3_0_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
1300 #define UMCCH3_0_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
1301 #define UMCCH3_0_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
1302 #define UMCCH3_0_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
1303 #define UMCCH3_0_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
1304 #define UMCCH3_0_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
1305 #define UMCCH3_0_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
1306 #define UMCCH3_0_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
1307 #define UMCCH3_0_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
1308 #define UMCCH3_0_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
1309 #define UMCCH3_0_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
1310 #define UMCCH3_0_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
1311 //UMCCH3_0_PerfMonCtr1_Lo
1312 #define UMCCH3_0_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
1313 #define UMCCH3_0_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
1314 //UMCCH3_0_PerfMonCtr1_Hi
1315 #define UMCCH3_0_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
1316 #define UMCCH3_0_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
1317 #define UMCCH3_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
1318 #define UMCCH3_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
1319 #define UMCCH3_0_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
1320 #define UMCCH3_0_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
1321 #define UMCCH3_0_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1322 #define UMCCH3_0_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1323 //UMCCH3_0_PerfMonCtl2
1324 #define UMCCH3_0_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
1325 #define UMCCH3_0_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
1326 #define UMCCH3_0_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
1327 #define UMCCH3_0_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
1328 #define UMCCH3_0_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
1329 #define UMCCH3_0_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
1330 #define UMCCH3_0_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
1331 #define UMCCH3_0_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
1332 #define UMCCH3_0_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
1333 #define UMCCH3_0_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
1334 #define UMCCH3_0_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
1335 #define UMCCH3_0_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
1336 #define UMCCH3_0_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
1337 #define UMCCH3_0_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
1338 #define UMCCH3_0_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
1339 #define UMCCH3_0_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
1340 //UMCCH3_0_PerfMonCtr2_Lo
1341 #define UMCCH3_0_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
1342 #define UMCCH3_0_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
1343 //UMCCH3_0_PerfMonCtr2_Hi
1344 #define UMCCH3_0_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
1345 #define UMCCH3_0_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
1346 #define UMCCH3_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
1347 #define UMCCH3_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
1348 #define UMCCH3_0_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
1349 #define UMCCH3_0_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
1350 #define UMCCH3_0_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1351 #define UMCCH3_0_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1352 //UMCCH3_0_PerfMonCtl3
1353 #define UMCCH3_0_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
1354 #define UMCCH3_0_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
1355 #define UMCCH3_0_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
1356 #define UMCCH3_0_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
1357 #define UMCCH3_0_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
1358 #define UMCCH3_0_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
1359 #define UMCCH3_0_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
1360 #define UMCCH3_0_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
1361 #define UMCCH3_0_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
1362 #define UMCCH3_0_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
1363 #define UMCCH3_0_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
1364 #define UMCCH3_0_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
1365 #define UMCCH3_0_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
1366 #define UMCCH3_0_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
1367 #define UMCCH3_0_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
1368 #define UMCCH3_0_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
1369 //UMCCH3_0_PerfMonCtr3_Lo
1370 #define UMCCH3_0_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
1371 #define UMCCH3_0_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
1372 //UMCCH3_0_PerfMonCtr3_Hi
1373 #define UMCCH3_0_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
1374 #define UMCCH3_0_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
1375 #define UMCCH3_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
1376 #define UMCCH3_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
1377 #define UMCCH3_0_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
1378 #define UMCCH3_0_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
1379 #define UMCCH3_0_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1380 #define UMCCH3_0_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1381 //UMCCH3_0_PerfMonCtl4
1382 #define UMCCH3_0_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
1383 #define UMCCH3_0_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
1384 #define UMCCH3_0_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
1385 #define UMCCH3_0_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
1386 #define UMCCH3_0_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
1387 #define UMCCH3_0_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
1388 #define UMCCH3_0_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
1389 #define UMCCH3_0_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
1390 #define UMCCH3_0_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
1391 #define UMCCH3_0_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
1392 #define UMCCH3_0_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
1393 #define UMCCH3_0_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
1394 #define UMCCH3_0_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
1395 #define UMCCH3_0_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
1396 #define UMCCH3_0_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
1397 #define UMCCH3_0_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
1398 //UMCCH3_0_PerfMonCtr4_Lo
1399 #define UMCCH3_0_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
1400 #define UMCCH3_0_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
1401 //UMCCH3_0_PerfMonCtr4_Hi
1402 #define UMCCH3_0_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
1403 #define UMCCH3_0_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
1404 #define UMCCH3_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
1405 #define UMCCH3_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
1406 #define UMCCH3_0_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
1407 #define UMCCH3_0_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
1408 #define UMCCH3_0_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1409 #define UMCCH3_0_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1410 //UMCCH3_0_PerfMonCtl5
1411 #define UMCCH3_0_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
1412 #define UMCCH3_0_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
1413 #define UMCCH3_0_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
1414 #define UMCCH3_0_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
1415 #define UMCCH3_0_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
1416 #define UMCCH3_0_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
1417 #define UMCCH3_0_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
1418 #define UMCCH3_0_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
1419 #define UMCCH3_0_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
1420 #define UMCCH3_0_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
1421 #define UMCCH3_0_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
1422 #define UMCCH3_0_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
1423 #define UMCCH3_0_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
1424 #define UMCCH3_0_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
1425 #define UMCCH3_0_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
1426 #define UMCCH3_0_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
1427 //UMCCH3_0_PerfMonCtr5_Lo
1428 #define UMCCH3_0_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
1429 #define UMCCH3_0_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
1430 //UMCCH3_0_PerfMonCtr5_Hi
1431 #define UMCCH3_0_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
1432 #define UMCCH3_0_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
1433 #define UMCCH3_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
1434 #define UMCCH3_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
1435 #define UMCCH3_0_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
1436 #define UMCCH3_0_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
1437 #define UMCCH3_0_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1438 #define UMCCH3_0_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1439 //UMCCH3_0_PerfMonCtl6
1440 #define UMCCH3_0_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
1441 #define UMCCH3_0_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
1442 #define UMCCH3_0_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
1443 #define UMCCH3_0_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
1444 #define UMCCH3_0_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
1445 #define UMCCH3_0_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
1446 #define UMCCH3_0_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
1447 #define UMCCH3_0_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
1448 #define UMCCH3_0_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
1449 #define UMCCH3_0_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
1450 #define UMCCH3_0_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
1451 #define UMCCH3_0_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
1452 #define UMCCH3_0_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
1453 #define UMCCH3_0_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
1454 #define UMCCH3_0_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
1455 #define UMCCH3_0_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
1456 //UMCCH3_0_PerfMonCtr6_Lo
1457 #define UMCCH3_0_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
1458 #define UMCCH3_0_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
1459 //UMCCH3_0_PerfMonCtr6_Hi
1460 #define UMCCH3_0_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
1461 #define UMCCH3_0_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
1462 #define UMCCH3_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
1463 #define UMCCH3_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
1464 #define UMCCH3_0_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
1465 #define UMCCH3_0_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
1466 #define UMCCH3_0_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1467 #define UMCCH3_0_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1468 //UMCCH3_0_PerfMonCtl7
1469 #define UMCCH3_0_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
1470 #define UMCCH3_0_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
1471 #define UMCCH3_0_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
1472 #define UMCCH3_0_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
1473 #define UMCCH3_0_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
1474 #define UMCCH3_0_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
1475 #define UMCCH3_0_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
1476 #define UMCCH3_0_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
1477 #define UMCCH3_0_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
1478 #define UMCCH3_0_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
1479 #define UMCCH3_0_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
1480 #define UMCCH3_0_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
1481 #define UMCCH3_0_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
1482 #define UMCCH3_0_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
1483 #define UMCCH3_0_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
1484 #define UMCCH3_0_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
1485 //UMCCH3_0_PerfMonCtr7_Lo
1486 #define UMCCH3_0_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
1487 #define UMCCH3_0_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
1488 //UMCCH3_0_PerfMonCtr7_Hi
1489 #define UMCCH3_0_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
1490 #define UMCCH3_0_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
1491 #define UMCCH3_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
1492 #define UMCCH3_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
1493 #define UMCCH3_0_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
1494 #define UMCCH3_0_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
1495 #define UMCCH3_0_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1496 #define UMCCH3_0_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1497 //UMCCH3_0_PerfMonCtl8
1498 #define UMCCH3_0_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
1499 #define UMCCH3_0_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
1500 #define UMCCH3_0_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
1501 #define UMCCH3_0_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
1502 #define UMCCH3_0_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
1503 #define UMCCH3_0_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
1504 #define UMCCH3_0_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
1505 #define UMCCH3_0_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
1506 #define UMCCH3_0_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
1507 #define UMCCH3_0_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
1508 #define UMCCH3_0_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
1509 #define UMCCH3_0_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
1510 #define UMCCH3_0_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
1511 #define UMCCH3_0_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
1512 #define UMCCH3_0_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
1513 #define UMCCH3_0_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
1514 //UMCCH3_0_PerfMonCtr8_Lo
1515 #define UMCCH3_0_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
1516 #define UMCCH3_0_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
1517 //UMCCH3_0_PerfMonCtr8_Hi
1518 #define UMCCH3_0_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
1519 #define UMCCH3_0_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
1520 #define UMCCH3_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
1521 #define UMCCH3_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
1522 #define UMCCH3_0_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
1523 #define UMCCH3_0_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
1524 #define UMCCH3_0_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1525 #define UMCCH3_0_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1526 
1527 
1528 // addressBlock: umc_w_phy_umc0_umcch4_umcchdec
1529 //UMCCH4_0_BaseAddrCS0
1530 #define UMCCH4_0_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
1531 #define UMCCH4_0_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
1532 #define UMCCH4_0_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
1533 #define UMCCH4_0_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
1534 //UMCCH4_0_AddrMaskCS01
1535 #define UMCCH4_0_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
1536 #define UMCCH4_0_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
1537 //UMCCH4_0_AddrSelCS01
1538 #define UMCCH4_0_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
1539 #define UMCCH4_0_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
1540 #define UMCCH4_0_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
1541 #define UMCCH4_0_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
1542 #define UMCCH4_0_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
1543 #define UMCCH4_0_AddrSelCS01__RowLo__SHIFT                                                                    0x18
1544 #define UMCCH4_0_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
1545 #define UMCCH4_0_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
1546 #define UMCCH4_0_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
1547 #define UMCCH4_0_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
1548 #define UMCCH4_0_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
1549 #define UMCCH4_0_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
1550 #define UMCCH4_0_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
1551 #define UMCCH4_0_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
1552 //UMCCH4_0_AddrHashBank0
1553 #define UMCCH4_0_AddrHashBank0__XorEnable__SHIFT                                                              0x0
1554 #define UMCCH4_0_AddrHashBank0__ColXor__SHIFT                                                                 0x1
1555 #define UMCCH4_0_AddrHashBank0__RowXor__SHIFT                                                                 0xe
1556 #define UMCCH4_0_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
1557 #define UMCCH4_0_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
1558 #define UMCCH4_0_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
1559 //UMCCH4_0_AddrHashBank1
1560 #define UMCCH4_0_AddrHashBank1__XorEnable__SHIFT                                                              0x0
1561 #define UMCCH4_0_AddrHashBank1__ColXor__SHIFT                                                                 0x1
1562 #define UMCCH4_0_AddrHashBank1__RowXor__SHIFT                                                                 0xe
1563 #define UMCCH4_0_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
1564 #define UMCCH4_0_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
1565 #define UMCCH4_0_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
1566 //UMCCH4_0_AddrHashBank2
1567 #define UMCCH4_0_AddrHashBank2__XorEnable__SHIFT                                                              0x0
1568 #define UMCCH4_0_AddrHashBank2__ColXor__SHIFT                                                                 0x1
1569 #define UMCCH4_0_AddrHashBank2__RowXor__SHIFT                                                                 0xe
1570 #define UMCCH4_0_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
1571 #define UMCCH4_0_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
1572 #define UMCCH4_0_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
1573 //UMCCH4_0_AddrHashBank3
1574 #define UMCCH4_0_AddrHashBank3__XorEnable__SHIFT                                                              0x0
1575 #define UMCCH4_0_AddrHashBank3__ColXor__SHIFT                                                                 0x1
1576 #define UMCCH4_0_AddrHashBank3__RowXor__SHIFT                                                                 0xe
1577 #define UMCCH4_0_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
1578 #define UMCCH4_0_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
1579 #define UMCCH4_0_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
1580 //UMCCH4_0_AddrHashBank4
1581 #define UMCCH4_0_AddrHashBank4__XorEnable__SHIFT                                                              0x0
1582 #define UMCCH4_0_AddrHashBank4__ColXor__SHIFT                                                                 0x1
1583 #define UMCCH4_0_AddrHashBank4__RowXor__SHIFT                                                                 0xe
1584 #define UMCCH4_0_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
1585 #define UMCCH4_0_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
1586 #define UMCCH4_0_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
1587 //UMCCH4_0_AddrHashBank5
1588 #define UMCCH4_0_AddrHashBank5__XorEnable__SHIFT                                                              0x0
1589 #define UMCCH4_0_AddrHashBank5__ColXor__SHIFT                                                                 0x1
1590 #define UMCCH4_0_AddrHashBank5__RowXor__SHIFT                                                                 0xe
1591 #define UMCCH4_0_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
1592 #define UMCCH4_0_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
1593 #define UMCCH4_0_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
1594 //UMCCH4_0_EccErrCntSel
1595 #define UMCCH4_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
1596 #define UMCCH4_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
1597 #define UMCCH4_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
1598 #define UMCCH4_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
1599 #define UMCCH4_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
1600 #define UMCCH4_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
1601 //UMCCH4_0_EccErrCnt
1602 #define UMCCH4_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
1603 #define UMCCH4_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
1604 //UMCCH4_0_PerfMonCtlClk
1605 #define UMCCH4_0_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
1606 #define UMCCH4_0_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
1607 #define UMCCH4_0_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
1608 #define UMCCH4_0_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
1609 #define UMCCH4_0_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
1610 #define UMCCH4_0_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
1611 #define UMCCH4_0_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
1612 #define UMCCH4_0_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
1613 #define UMCCH4_0_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
1614 #define UMCCH4_0_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
1615 #define UMCCH4_0_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
1616 #define UMCCH4_0_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
1617 //UMCCH4_0_PerfMonCtrClk_Lo
1618 #define UMCCH4_0_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
1619 #define UMCCH4_0_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
1620 //UMCCH4_0_PerfMonCtrClk_Hi
1621 #define UMCCH4_0_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
1622 #define UMCCH4_0_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
1623 #define UMCCH4_0_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
1624 #define UMCCH4_0_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
1625 //UMCCH4_0_PerfMonCtl1
1626 #define UMCCH4_0_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
1627 #define UMCCH4_0_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
1628 #define UMCCH4_0_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
1629 #define UMCCH4_0_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
1630 #define UMCCH4_0_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
1631 #define UMCCH4_0_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
1632 #define UMCCH4_0_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
1633 #define UMCCH4_0_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
1634 #define UMCCH4_0_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
1635 #define UMCCH4_0_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
1636 #define UMCCH4_0_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
1637 #define UMCCH4_0_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
1638 #define UMCCH4_0_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
1639 #define UMCCH4_0_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
1640 #define UMCCH4_0_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
1641 #define UMCCH4_0_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
1642 //UMCCH4_0_PerfMonCtr1_Lo
1643 #define UMCCH4_0_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
1644 #define UMCCH4_0_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
1645 //UMCCH4_0_PerfMonCtr1_Hi
1646 #define UMCCH4_0_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
1647 #define UMCCH4_0_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
1648 #define UMCCH4_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
1649 #define UMCCH4_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
1650 #define UMCCH4_0_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
1651 #define UMCCH4_0_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
1652 #define UMCCH4_0_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1653 #define UMCCH4_0_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1654 //UMCCH4_0_PerfMonCtl2
1655 #define UMCCH4_0_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
1656 #define UMCCH4_0_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
1657 #define UMCCH4_0_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
1658 #define UMCCH4_0_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
1659 #define UMCCH4_0_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
1660 #define UMCCH4_0_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
1661 #define UMCCH4_0_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
1662 #define UMCCH4_0_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
1663 #define UMCCH4_0_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
1664 #define UMCCH4_0_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
1665 #define UMCCH4_0_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
1666 #define UMCCH4_0_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
1667 #define UMCCH4_0_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
1668 #define UMCCH4_0_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
1669 #define UMCCH4_0_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
1670 #define UMCCH4_0_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
1671 //UMCCH4_0_PerfMonCtr2_Lo
1672 #define UMCCH4_0_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
1673 #define UMCCH4_0_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
1674 //UMCCH4_0_PerfMonCtr2_Hi
1675 #define UMCCH4_0_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
1676 #define UMCCH4_0_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
1677 #define UMCCH4_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
1678 #define UMCCH4_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
1679 #define UMCCH4_0_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
1680 #define UMCCH4_0_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
1681 #define UMCCH4_0_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1682 #define UMCCH4_0_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1683 //UMCCH4_0_PerfMonCtl3
1684 #define UMCCH4_0_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
1685 #define UMCCH4_0_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
1686 #define UMCCH4_0_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
1687 #define UMCCH4_0_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
1688 #define UMCCH4_0_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
1689 #define UMCCH4_0_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
1690 #define UMCCH4_0_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
1691 #define UMCCH4_0_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
1692 #define UMCCH4_0_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
1693 #define UMCCH4_0_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
1694 #define UMCCH4_0_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
1695 #define UMCCH4_0_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
1696 #define UMCCH4_0_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
1697 #define UMCCH4_0_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
1698 #define UMCCH4_0_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
1699 #define UMCCH4_0_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
1700 //UMCCH4_0_PerfMonCtr3_Lo
1701 #define UMCCH4_0_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
1702 #define UMCCH4_0_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
1703 //UMCCH4_0_PerfMonCtr3_Hi
1704 #define UMCCH4_0_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
1705 #define UMCCH4_0_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
1706 #define UMCCH4_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
1707 #define UMCCH4_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
1708 #define UMCCH4_0_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
1709 #define UMCCH4_0_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
1710 #define UMCCH4_0_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1711 #define UMCCH4_0_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1712 //UMCCH4_0_PerfMonCtl4
1713 #define UMCCH4_0_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
1714 #define UMCCH4_0_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
1715 #define UMCCH4_0_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
1716 #define UMCCH4_0_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
1717 #define UMCCH4_0_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
1718 #define UMCCH4_0_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
1719 #define UMCCH4_0_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
1720 #define UMCCH4_0_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
1721 #define UMCCH4_0_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
1722 #define UMCCH4_0_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
1723 #define UMCCH4_0_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
1724 #define UMCCH4_0_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
1725 #define UMCCH4_0_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
1726 #define UMCCH4_0_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
1727 #define UMCCH4_0_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
1728 #define UMCCH4_0_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
1729 //UMCCH4_0_PerfMonCtr4_Lo
1730 #define UMCCH4_0_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
1731 #define UMCCH4_0_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
1732 //UMCCH4_0_PerfMonCtr4_Hi
1733 #define UMCCH4_0_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
1734 #define UMCCH4_0_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
1735 #define UMCCH4_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
1736 #define UMCCH4_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
1737 #define UMCCH4_0_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
1738 #define UMCCH4_0_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
1739 #define UMCCH4_0_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1740 #define UMCCH4_0_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1741 //UMCCH4_0_PerfMonCtl5
1742 #define UMCCH4_0_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
1743 #define UMCCH4_0_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
1744 #define UMCCH4_0_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
1745 #define UMCCH4_0_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
1746 #define UMCCH4_0_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
1747 #define UMCCH4_0_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
1748 #define UMCCH4_0_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
1749 #define UMCCH4_0_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
1750 #define UMCCH4_0_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
1751 #define UMCCH4_0_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
1752 #define UMCCH4_0_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
1753 #define UMCCH4_0_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
1754 #define UMCCH4_0_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
1755 #define UMCCH4_0_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
1756 #define UMCCH4_0_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
1757 #define UMCCH4_0_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
1758 //UMCCH4_0_PerfMonCtr5_Lo
1759 #define UMCCH4_0_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
1760 #define UMCCH4_0_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
1761 //UMCCH4_0_PerfMonCtr5_Hi
1762 #define UMCCH4_0_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
1763 #define UMCCH4_0_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
1764 #define UMCCH4_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
1765 #define UMCCH4_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
1766 #define UMCCH4_0_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
1767 #define UMCCH4_0_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
1768 #define UMCCH4_0_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1769 #define UMCCH4_0_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1770 //UMCCH4_0_PerfMonCtl6
1771 #define UMCCH4_0_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
1772 #define UMCCH4_0_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
1773 #define UMCCH4_0_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
1774 #define UMCCH4_0_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
1775 #define UMCCH4_0_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
1776 #define UMCCH4_0_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
1777 #define UMCCH4_0_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
1778 #define UMCCH4_0_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
1779 #define UMCCH4_0_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
1780 #define UMCCH4_0_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
1781 #define UMCCH4_0_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
1782 #define UMCCH4_0_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
1783 #define UMCCH4_0_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
1784 #define UMCCH4_0_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
1785 #define UMCCH4_0_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
1786 #define UMCCH4_0_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
1787 //UMCCH4_0_PerfMonCtr6_Lo
1788 #define UMCCH4_0_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
1789 #define UMCCH4_0_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
1790 //UMCCH4_0_PerfMonCtr6_Hi
1791 #define UMCCH4_0_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
1792 #define UMCCH4_0_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
1793 #define UMCCH4_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
1794 #define UMCCH4_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
1795 #define UMCCH4_0_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
1796 #define UMCCH4_0_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
1797 #define UMCCH4_0_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1798 #define UMCCH4_0_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1799 //UMCCH4_0_PerfMonCtl7
1800 #define UMCCH4_0_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
1801 #define UMCCH4_0_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
1802 #define UMCCH4_0_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
1803 #define UMCCH4_0_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
1804 #define UMCCH4_0_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
1805 #define UMCCH4_0_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
1806 #define UMCCH4_0_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
1807 #define UMCCH4_0_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
1808 #define UMCCH4_0_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
1809 #define UMCCH4_0_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
1810 #define UMCCH4_0_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
1811 #define UMCCH4_0_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
1812 #define UMCCH4_0_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
1813 #define UMCCH4_0_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
1814 #define UMCCH4_0_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
1815 #define UMCCH4_0_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
1816 //UMCCH4_0_PerfMonCtr7_Lo
1817 #define UMCCH4_0_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
1818 #define UMCCH4_0_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
1819 //UMCCH4_0_PerfMonCtr7_Hi
1820 #define UMCCH4_0_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
1821 #define UMCCH4_0_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
1822 #define UMCCH4_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
1823 #define UMCCH4_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
1824 #define UMCCH4_0_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
1825 #define UMCCH4_0_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
1826 #define UMCCH4_0_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1827 #define UMCCH4_0_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1828 //UMCCH4_0_PerfMonCtl8
1829 #define UMCCH4_0_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
1830 #define UMCCH4_0_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
1831 #define UMCCH4_0_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
1832 #define UMCCH4_0_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
1833 #define UMCCH4_0_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
1834 #define UMCCH4_0_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
1835 #define UMCCH4_0_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
1836 #define UMCCH4_0_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
1837 #define UMCCH4_0_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
1838 #define UMCCH4_0_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
1839 #define UMCCH4_0_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
1840 #define UMCCH4_0_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
1841 #define UMCCH4_0_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
1842 #define UMCCH4_0_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
1843 #define UMCCH4_0_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
1844 #define UMCCH4_0_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
1845 //UMCCH4_0_PerfMonCtr8_Lo
1846 #define UMCCH4_0_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
1847 #define UMCCH4_0_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
1848 //UMCCH4_0_PerfMonCtr8_Hi
1849 #define UMCCH4_0_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
1850 #define UMCCH4_0_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
1851 #define UMCCH4_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
1852 #define UMCCH4_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
1853 #define UMCCH4_0_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
1854 #define UMCCH4_0_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
1855 #define UMCCH4_0_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1856 #define UMCCH4_0_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1857 
1858 
1859 // addressBlock: umc_w_phy_umc0_umcch5_umcchdec
1860 //UMCCH5_0_BaseAddrCS0
1861 #define UMCCH5_0_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
1862 #define UMCCH5_0_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
1863 #define UMCCH5_0_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
1864 #define UMCCH5_0_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
1865 //UMCCH5_0_AddrMaskCS01
1866 #define UMCCH5_0_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
1867 #define UMCCH5_0_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
1868 //UMCCH5_0_AddrSelCS01
1869 #define UMCCH5_0_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
1870 #define UMCCH5_0_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
1871 #define UMCCH5_0_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
1872 #define UMCCH5_0_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
1873 #define UMCCH5_0_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
1874 #define UMCCH5_0_AddrSelCS01__RowLo__SHIFT                                                                    0x18
1875 #define UMCCH5_0_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
1876 #define UMCCH5_0_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
1877 #define UMCCH5_0_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
1878 #define UMCCH5_0_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
1879 #define UMCCH5_0_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
1880 #define UMCCH5_0_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
1881 #define UMCCH5_0_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
1882 #define UMCCH5_0_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
1883 //UMCCH5_0_AddrHashBank0
1884 #define UMCCH5_0_AddrHashBank0__XorEnable__SHIFT                                                              0x0
1885 #define UMCCH5_0_AddrHashBank0__ColXor__SHIFT                                                                 0x1
1886 #define UMCCH5_0_AddrHashBank0__RowXor__SHIFT                                                                 0xe
1887 #define UMCCH5_0_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
1888 #define UMCCH5_0_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
1889 #define UMCCH5_0_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
1890 //UMCCH5_0_AddrHashBank1
1891 #define UMCCH5_0_AddrHashBank1__XorEnable__SHIFT                                                              0x0
1892 #define UMCCH5_0_AddrHashBank1__ColXor__SHIFT                                                                 0x1
1893 #define UMCCH5_0_AddrHashBank1__RowXor__SHIFT                                                                 0xe
1894 #define UMCCH5_0_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
1895 #define UMCCH5_0_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
1896 #define UMCCH5_0_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
1897 //UMCCH5_0_AddrHashBank2
1898 #define UMCCH5_0_AddrHashBank2__XorEnable__SHIFT                                                              0x0
1899 #define UMCCH5_0_AddrHashBank2__ColXor__SHIFT                                                                 0x1
1900 #define UMCCH5_0_AddrHashBank2__RowXor__SHIFT                                                                 0xe
1901 #define UMCCH5_0_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
1902 #define UMCCH5_0_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
1903 #define UMCCH5_0_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
1904 //UMCCH5_0_AddrHashBank3
1905 #define UMCCH5_0_AddrHashBank3__XorEnable__SHIFT                                                              0x0
1906 #define UMCCH5_0_AddrHashBank3__ColXor__SHIFT                                                                 0x1
1907 #define UMCCH5_0_AddrHashBank3__RowXor__SHIFT                                                                 0xe
1908 #define UMCCH5_0_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
1909 #define UMCCH5_0_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
1910 #define UMCCH5_0_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
1911 //UMCCH5_0_AddrHashBank4
1912 #define UMCCH5_0_AddrHashBank4__XorEnable__SHIFT                                                              0x0
1913 #define UMCCH5_0_AddrHashBank4__ColXor__SHIFT                                                                 0x1
1914 #define UMCCH5_0_AddrHashBank4__RowXor__SHIFT                                                                 0xe
1915 #define UMCCH5_0_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
1916 #define UMCCH5_0_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
1917 #define UMCCH5_0_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
1918 //UMCCH5_0_AddrHashBank5
1919 #define UMCCH5_0_AddrHashBank5__XorEnable__SHIFT                                                              0x0
1920 #define UMCCH5_0_AddrHashBank5__ColXor__SHIFT                                                                 0x1
1921 #define UMCCH5_0_AddrHashBank5__RowXor__SHIFT                                                                 0xe
1922 #define UMCCH5_0_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
1923 #define UMCCH5_0_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
1924 #define UMCCH5_0_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
1925 //UMCCH5_0_EccErrCntSel
1926 #define UMCCH5_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
1927 #define UMCCH5_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
1928 #define UMCCH5_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
1929 #define UMCCH5_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
1930 #define UMCCH5_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
1931 #define UMCCH5_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
1932 //UMCCH5_0_EccErrCnt
1933 #define UMCCH5_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
1934 #define UMCCH5_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
1935 //UMCCH5_0_PerfMonCtlClk
1936 #define UMCCH5_0_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
1937 #define UMCCH5_0_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
1938 #define UMCCH5_0_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
1939 #define UMCCH5_0_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
1940 #define UMCCH5_0_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
1941 #define UMCCH5_0_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
1942 #define UMCCH5_0_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
1943 #define UMCCH5_0_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
1944 #define UMCCH5_0_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
1945 #define UMCCH5_0_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
1946 #define UMCCH5_0_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
1947 #define UMCCH5_0_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
1948 //UMCCH5_0_PerfMonCtrClk_Lo
1949 #define UMCCH5_0_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
1950 #define UMCCH5_0_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
1951 //UMCCH5_0_PerfMonCtrClk_Hi
1952 #define UMCCH5_0_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
1953 #define UMCCH5_0_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
1954 #define UMCCH5_0_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
1955 #define UMCCH5_0_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
1956 //UMCCH5_0_PerfMonCtl1
1957 #define UMCCH5_0_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
1958 #define UMCCH5_0_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
1959 #define UMCCH5_0_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
1960 #define UMCCH5_0_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
1961 #define UMCCH5_0_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
1962 #define UMCCH5_0_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
1963 #define UMCCH5_0_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
1964 #define UMCCH5_0_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
1965 #define UMCCH5_0_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
1966 #define UMCCH5_0_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
1967 #define UMCCH5_0_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
1968 #define UMCCH5_0_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
1969 #define UMCCH5_0_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
1970 #define UMCCH5_0_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
1971 #define UMCCH5_0_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
1972 #define UMCCH5_0_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
1973 //UMCCH5_0_PerfMonCtr1_Lo
1974 #define UMCCH5_0_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
1975 #define UMCCH5_0_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
1976 //UMCCH5_0_PerfMonCtr1_Hi
1977 #define UMCCH5_0_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
1978 #define UMCCH5_0_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
1979 #define UMCCH5_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
1980 #define UMCCH5_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
1981 #define UMCCH5_0_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
1982 #define UMCCH5_0_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
1983 #define UMCCH5_0_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
1984 #define UMCCH5_0_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
1985 //UMCCH5_0_PerfMonCtl2
1986 #define UMCCH5_0_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
1987 #define UMCCH5_0_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
1988 #define UMCCH5_0_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
1989 #define UMCCH5_0_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
1990 #define UMCCH5_0_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
1991 #define UMCCH5_0_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
1992 #define UMCCH5_0_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
1993 #define UMCCH5_0_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
1994 #define UMCCH5_0_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
1995 #define UMCCH5_0_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
1996 #define UMCCH5_0_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
1997 #define UMCCH5_0_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
1998 #define UMCCH5_0_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
1999 #define UMCCH5_0_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
2000 #define UMCCH5_0_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
2001 #define UMCCH5_0_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
2002 //UMCCH5_0_PerfMonCtr2_Lo
2003 #define UMCCH5_0_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
2004 #define UMCCH5_0_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
2005 //UMCCH5_0_PerfMonCtr2_Hi
2006 #define UMCCH5_0_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
2007 #define UMCCH5_0_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
2008 #define UMCCH5_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
2009 #define UMCCH5_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
2010 #define UMCCH5_0_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
2011 #define UMCCH5_0_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
2012 #define UMCCH5_0_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2013 #define UMCCH5_0_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2014 //UMCCH5_0_PerfMonCtl3
2015 #define UMCCH5_0_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
2016 #define UMCCH5_0_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
2017 #define UMCCH5_0_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
2018 #define UMCCH5_0_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
2019 #define UMCCH5_0_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
2020 #define UMCCH5_0_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
2021 #define UMCCH5_0_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
2022 #define UMCCH5_0_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
2023 #define UMCCH5_0_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
2024 #define UMCCH5_0_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
2025 #define UMCCH5_0_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
2026 #define UMCCH5_0_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
2027 #define UMCCH5_0_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
2028 #define UMCCH5_0_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
2029 #define UMCCH5_0_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
2030 #define UMCCH5_0_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
2031 //UMCCH5_0_PerfMonCtr3_Lo
2032 #define UMCCH5_0_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
2033 #define UMCCH5_0_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
2034 //UMCCH5_0_PerfMonCtr3_Hi
2035 #define UMCCH5_0_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
2036 #define UMCCH5_0_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
2037 #define UMCCH5_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
2038 #define UMCCH5_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
2039 #define UMCCH5_0_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
2040 #define UMCCH5_0_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
2041 #define UMCCH5_0_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2042 #define UMCCH5_0_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2043 //UMCCH5_0_PerfMonCtl4
2044 #define UMCCH5_0_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
2045 #define UMCCH5_0_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
2046 #define UMCCH5_0_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
2047 #define UMCCH5_0_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
2048 #define UMCCH5_0_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
2049 #define UMCCH5_0_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
2050 #define UMCCH5_0_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
2051 #define UMCCH5_0_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
2052 #define UMCCH5_0_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
2053 #define UMCCH5_0_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
2054 #define UMCCH5_0_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
2055 #define UMCCH5_0_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
2056 #define UMCCH5_0_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
2057 #define UMCCH5_0_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
2058 #define UMCCH5_0_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
2059 #define UMCCH5_0_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
2060 //UMCCH5_0_PerfMonCtr4_Lo
2061 #define UMCCH5_0_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
2062 #define UMCCH5_0_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
2063 //UMCCH5_0_PerfMonCtr4_Hi
2064 #define UMCCH5_0_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
2065 #define UMCCH5_0_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
2066 #define UMCCH5_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
2067 #define UMCCH5_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
2068 #define UMCCH5_0_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
2069 #define UMCCH5_0_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
2070 #define UMCCH5_0_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2071 #define UMCCH5_0_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2072 //UMCCH5_0_PerfMonCtl5
2073 #define UMCCH5_0_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
2074 #define UMCCH5_0_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
2075 #define UMCCH5_0_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
2076 #define UMCCH5_0_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
2077 #define UMCCH5_0_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
2078 #define UMCCH5_0_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
2079 #define UMCCH5_0_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
2080 #define UMCCH5_0_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
2081 #define UMCCH5_0_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
2082 #define UMCCH5_0_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
2083 #define UMCCH5_0_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
2084 #define UMCCH5_0_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
2085 #define UMCCH5_0_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
2086 #define UMCCH5_0_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
2087 #define UMCCH5_0_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
2088 #define UMCCH5_0_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
2089 //UMCCH5_0_PerfMonCtr5_Lo
2090 #define UMCCH5_0_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
2091 #define UMCCH5_0_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
2092 //UMCCH5_0_PerfMonCtr5_Hi
2093 #define UMCCH5_0_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
2094 #define UMCCH5_0_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
2095 #define UMCCH5_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
2096 #define UMCCH5_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
2097 #define UMCCH5_0_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
2098 #define UMCCH5_0_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
2099 #define UMCCH5_0_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2100 #define UMCCH5_0_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2101 //UMCCH5_0_PerfMonCtl6
2102 #define UMCCH5_0_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
2103 #define UMCCH5_0_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
2104 #define UMCCH5_0_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
2105 #define UMCCH5_0_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
2106 #define UMCCH5_0_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
2107 #define UMCCH5_0_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
2108 #define UMCCH5_0_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
2109 #define UMCCH5_0_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
2110 #define UMCCH5_0_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
2111 #define UMCCH5_0_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
2112 #define UMCCH5_0_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
2113 #define UMCCH5_0_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
2114 #define UMCCH5_0_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
2115 #define UMCCH5_0_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
2116 #define UMCCH5_0_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
2117 #define UMCCH5_0_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
2118 //UMCCH5_0_PerfMonCtr6_Lo
2119 #define UMCCH5_0_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
2120 #define UMCCH5_0_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
2121 //UMCCH5_0_PerfMonCtr6_Hi
2122 #define UMCCH5_0_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
2123 #define UMCCH5_0_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
2124 #define UMCCH5_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
2125 #define UMCCH5_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
2126 #define UMCCH5_0_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
2127 #define UMCCH5_0_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
2128 #define UMCCH5_0_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2129 #define UMCCH5_0_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2130 //UMCCH5_0_PerfMonCtl7
2131 #define UMCCH5_0_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
2132 #define UMCCH5_0_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
2133 #define UMCCH5_0_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
2134 #define UMCCH5_0_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
2135 #define UMCCH5_0_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
2136 #define UMCCH5_0_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
2137 #define UMCCH5_0_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
2138 #define UMCCH5_0_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
2139 #define UMCCH5_0_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
2140 #define UMCCH5_0_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
2141 #define UMCCH5_0_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
2142 #define UMCCH5_0_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
2143 #define UMCCH5_0_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
2144 #define UMCCH5_0_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
2145 #define UMCCH5_0_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
2146 #define UMCCH5_0_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
2147 //UMCCH5_0_PerfMonCtr7_Lo
2148 #define UMCCH5_0_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
2149 #define UMCCH5_0_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
2150 //UMCCH5_0_PerfMonCtr7_Hi
2151 #define UMCCH5_0_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
2152 #define UMCCH5_0_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
2153 #define UMCCH5_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
2154 #define UMCCH5_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
2155 #define UMCCH5_0_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
2156 #define UMCCH5_0_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
2157 #define UMCCH5_0_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2158 #define UMCCH5_0_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2159 //UMCCH5_0_PerfMonCtl8
2160 #define UMCCH5_0_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
2161 #define UMCCH5_0_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
2162 #define UMCCH5_0_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
2163 #define UMCCH5_0_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
2164 #define UMCCH5_0_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
2165 #define UMCCH5_0_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
2166 #define UMCCH5_0_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
2167 #define UMCCH5_0_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
2168 #define UMCCH5_0_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
2169 #define UMCCH5_0_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
2170 #define UMCCH5_0_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
2171 #define UMCCH5_0_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
2172 #define UMCCH5_0_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
2173 #define UMCCH5_0_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
2174 #define UMCCH5_0_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
2175 #define UMCCH5_0_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
2176 //UMCCH5_0_PerfMonCtr8_Lo
2177 #define UMCCH5_0_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
2178 #define UMCCH5_0_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
2179 //UMCCH5_0_PerfMonCtr8_Hi
2180 #define UMCCH5_0_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
2181 #define UMCCH5_0_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
2182 #define UMCCH5_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
2183 #define UMCCH5_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
2184 #define UMCCH5_0_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
2185 #define UMCCH5_0_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
2186 #define UMCCH5_0_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2187 #define UMCCH5_0_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2188 
2189 
2190 // addressBlock: umc_w_phy_umc0_umcch6_umcchdec
2191 //UMCCH6_0_BaseAddrCS0
2192 #define UMCCH6_0_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
2193 #define UMCCH6_0_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
2194 #define UMCCH6_0_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
2195 #define UMCCH6_0_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
2196 //UMCCH6_0_AddrMaskCS01
2197 #define UMCCH6_0_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
2198 #define UMCCH6_0_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
2199 //UMCCH6_0_AddrSelCS01
2200 #define UMCCH6_0_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
2201 #define UMCCH6_0_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
2202 #define UMCCH6_0_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
2203 #define UMCCH6_0_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
2204 #define UMCCH6_0_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
2205 #define UMCCH6_0_AddrSelCS01__RowLo__SHIFT                                                                    0x18
2206 #define UMCCH6_0_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
2207 #define UMCCH6_0_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
2208 #define UMCCH6_0_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
2209 #define UMCCH6_0_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
2210 #define UMCCH6_0_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
2211 #define UMCCH6_0_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
2212 #define UMCCH6_0_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
2213 #define UMCCH6_0_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
2214 //UMCCH6_0_AddrHashBank0
2215 #define UMCCH6_0_AddrHashBank0__XorEnable__SHIFT                                                              0x0
2216 #define UMCCH6_0_AddrHashBank0__ColXor__SHIFT                                                                 0x1
2217 #define UMCCH6_0_AddrHashBank0__RowXor__SHIFT                                                                 0xe
2218 #define UMCCH6_0_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
2219 #define UMCCH6_0_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
2220 #define UMCCH6_0_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
2221 //UMCCH6_0_AddrHashBank1
2222 #define UMCCH6_0_AddrHashBank1__XorEnable__SHIFT                                                              0x0
2223 #define UMCCH6_0_AddrHashBank1__ColXor__SHIFT                                                                 0x1
2224 #define UMCCH6_0_AddrHashBank1__RowXor__SHIFT                                                                 0xe
2225 #define UMCCH6_0_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
2226 #define UMCCH6_0_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
2227 #define UMCCH6_0_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
2228 //UMCCH6_0_AddrHashBank2
2229 #define UMCCH6_0_AddrHashBank2__XorEnable__SHIFT                                                              0x0
2230 #define UMCCH6_0_AddrHashBank2__ColXor__SHIFT                                                                 0x1
2231 #define UMCCH6_0_AddrHashBank2__RowXor__SHIFT                                                                 0xe
2232 #define UMCCH6_0_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
2233 #define UMCCH6_0_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
2234 #define UMCCH6_0_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
2235 //UMCCH6_0_AddrHashBank3
2236 #define UMCCH6_0_AddrHashBank3__XorEnable__SHIFT                                                              0x0
2237 #define UMCCH6_0_AddrHashBank3__ColXor__SHIFT                                                                 0x1
2238 #define UMCCH6_0_AddrHashBank3__RowXor__SHIFT                                                                 0xe
2239 #define UMCCH6_0_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
2240 #define UMCCH6_0_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
2241 #define UMCCH6_0_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
2242 //UMCCH6_0_AddrHashBank4
2243 #define UMCCH6_0_AddrHashBank4__XorEnable__SHIFT                                                              0x0
2244 #define UMCCH6_0_AddrHashBank4__ColXor__SHIFT                                                                 0x1
2245 #define UMCCH6_0_AddrHashBank4__RowXor__SHIFT                                                                 0xe
2246 #define UMCCH6_0_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
2247 #define UMCCH6_0_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
2248 #define UMCCH6_0_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
2249 //UMCCH6_0_AddrHashBank5
2250 #define UMCCH6_0_AddrHashBank5__XorEnable__SHIFT                                                              0x0
2251 #define UMCCH6_0_AddrHashBank5__ColXor__SHIFT                                                                 0x1
2252 #define UMCCH6_0_AddrHashBank5__RowXor__SHIFT                                                                 0xe
2253 #define UMCCH6_0_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
2254 #define UMCCH6_0_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
2255 #define UMCCH6_0_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
2256 //UMCCH6_0_EccErrCntSel
2257 #define UMCCH6_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
2258 #define UMCCH6_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
2259 #define UMCCH6_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
2260 #define UMCCH6_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
2261 #define UMCCH6_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
2262 #define UMCCH6_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
2263 //UMCCH6_0_EccErrCnt
2264 #define UMCCH6_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
2265 #define UMCCH6_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
2266 //UMCCH6_0_PerfMonCtlClk
2267 #define UMCCH6_0_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
2268 #define UMCCH6_0_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
2269 #define UMCCH6_0_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
2270 #define UMCCH6_0_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
2271 #define UMCCH6_0_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
2272 #define UMCCH6_0_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
2273 #define UMCCH6_0_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
2274 #define UMCCH6_0_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
2275 #define UMCCH6_0_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
2276 #define UMCCH6_0_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
2277 #define UMCCH6_0_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
2278 #define UMCCH6_0_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
2279 //UMCCH6_0_PerfMonCtrClk_Lo
2280 #define UMCCH6_0_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
2281 #define UMCCH6_0_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
2282 //UMCCH6_0_PerfMonCtrClk_Hi
2283 #define UMCCH6_0_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
2284 #define UMCCH6_0_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
2285 #define UMCCH6_0_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
2286 #define UMCCH6_0_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
2287 //UMCCH6_0_PerfMonCtl1
2288 #define UMCCH6_0_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
2289 #define UMCCH6_0_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
2290 #define UMCCH6_0_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
2291 #define UMCCH6_0_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
2292 #define UMCCH6_0_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
2293 #define UMCCH6_0_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
2294 #define UMCCH6_0_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
2295 #define UMCCH6_0_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
2296 #define UMCCH6_0_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
2297 #define UMCCH6_0_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
2298 #define UMCCH6_0_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
2299 #define UMCCH6_0_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
2300 #define UMCCH6_0_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
2301 #define UMCCH6_0_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
2302 #define UMCCH6_0_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
2303 #define UMCCH6_0_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
2304 //UMCCH6_0_PerfMonCtr1_Lo
2305 #define UMCCH6_0_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
2306 #define UMCCH6_0_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
2307 //UMCCH6_0_PerfMonCtr1_Hi
2308 #define UMCCH6_0_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
2309 #define UMCCH6_0_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
2310 #define UMCCH6_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
2311 #define UMCCH6_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
2312 #define UMCCH6_0_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
2313 #define UMCCH6_0_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
2314 #define UMCCH6_0_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2315 #define UMCCH6_0_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2316 //UMCCH6_0_PerfMonCtl2
2317 #define UMCCH6_0_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
2318 #define UMCCH6_0_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
2319 #define UMCCH6_0_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
2320 #define UMCCH6_0_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
2321 #define UMCCH6_0_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
2322 #define UMCCH6_0_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
2323 #define UMCCH6_0_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
2324 #define UMCCH6_0_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
2325 #define UMCCH6_0_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
2326 #define UMCCH6_0_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
2327 #define UMCCH6_0_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
2328 #define UMCCH6_0_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
2329 #define UMCCH6_0_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
2330 #define UMCCH6_0_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
2331 #define UMCCH6_0_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
2332 #define UMCCH6_0_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
2333 //UMCCH6_0_PerfMonCtr2_Lo
2334 #define UMCCH6_0_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
2335 #define UMCCH6_0_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
2336 //UMCCH6_0_PerfMonCtr2_Hi
2337 #define UMCCH6_0_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
2338 #define UMCCH6_0_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
2339 #define UMCCH6_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
2340 #define UMCCH6_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
2341 #define UMCCH6_0_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
2342 #define UMCCH6_0_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
2343 #define UMCCH6_0_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2344 #define UMCCH6_0_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2345 //UMCCH6_0_PerfMonCtl3
2346 #define UMCCH6_0_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
2347 #define UMCCH6_0_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
2348 #define UMCCH6_0_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
2349 #define UMCCH6_0_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
2350 #define UMCCH6_0_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
2351 #define UMCCH6_0_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
2352 #define UMCCH6_0_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
2353 #define UMCCH6_0_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
2354 #define UMCCH6_0_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
2355 #define UMCCH6_0_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
2356 #define UMCCH6_0_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
2357 #define UMCCH6_0_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
2358 #define UMCCH6_0_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
2359 #define UMCCH6_0_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
2360 #define UMCCH6_0_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
2361 #define UMCCH6_0_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
2362 //UMCCH6_0_PerfMonCtr3_Lo
2363 #define UMCCH6_0_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
2364 #define UMCCH6_0_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
2365 //UMCCH6_0_PerfMonCtr3_Hi
2366 #define UMCCH6_0_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
2367 #define UMCCH6_0_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
2368 #define UMCCH6_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
2369 #define UMCCH6_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
2370 #define UMCCH6_0_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
2371 #define UMCCH6_0_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
2372 #define UMCCH6_0_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2373 #define UMCCH6_0_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2374 //UMCCH6_0_PerfMonCtl4
2375 #define UMCCH6_0_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
2376 #define UMCCH6_0_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
2377 #define UMCCH6_0_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
2378 #define UMCCH6_0_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
2379 #define UMCCH6_0_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
2380 #define UMCCH6_0_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
2381 #define UMCCH6_0_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
2382 #define UMCCH6_0_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
2383 #define UMCCH6_0_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
2384 #define UMCCH6_0_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
2385 #define UMCCH6_0_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
2386 #define UMCCH6_0_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
2387 #define UMCCH6_0_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
2388 #define UMCCH6_0_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
2389 #define UMCCH6_0_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
2390 #define UMCCH6_0_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
2391 //UMCCH6_0_PerfMonCtr4_Lo
2392 #define UMCCH6_0_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
2393 #define UMCCH6_0_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
2394 //UMCCH6_0_PerfMonCtr4_Hi
2395 #define UMCCH6_0_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
2396 #define UMCCH6_0_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
2397 #define UMCCH6_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
2398 #define UMCCH6_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
2399 #define UMCCH6_0_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
2400 #define UMCCH6_0_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
2401 #define UMCCH6_0_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2402 #define UMCCH6_0_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2403 //UMCCH6_0_PerfMonCtl5
2404 #define UMCCH6_0_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
2405 #define UMCCH6_0_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
2406 #define UMCCH6_0_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
2407 #define UMCCH6_0_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
2408 #define UMCCH6_0_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
2409 #define UMCCH6_0_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
2410 #define UMCCH6_0_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
2411 #define UMCCH6_0_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
2412 #define UMCCH6_0_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
2413 #define UMCCH6_0_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
2414 #define UMCCH6_0_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
2415 #define UMCCH6_0_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
2416 #define UMCCH6_0_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
2417 #define UMCCH6_0_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
2418 #define UMCCH6_0_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
2419 #define UMCCH6_0_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
2420 //UMCCH6_0_PerfMonCtr5_Lo
2421 #define UMCCH6_0_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
2422 #define UMCCH6_0_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
2423 //UMCCH6_0_PerfMonCtr5_Hi
2424 #define UMCCH6_0_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
2425 #define UMCCH6_0_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
2426 #define UMCCH6_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
2427 #define UMCCH6_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
2428 #define UMCCH6_0_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
2429 #define UMCCH6_0_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
2430 #define UMCCH6_0_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2431 #define UMCCH6_0_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2432 //UMCCH6_0_PerfMonCtl6
2433 #define UMCCH6_0_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
2434 #define UMCCH6_0_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
2435 #define UMCCH6_0_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
2436 #define UMCCH6_0_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
2437 #define UMCCH6_0_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
2438 #define UMCCH6_0_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
2439 #define UMCCH6_0_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
2440 #define UMCCH6_0_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
2441 #define UMCCH6_0_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
2442 #define UMCCH6_0_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
2443 #define UMCCH6_0_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
2444 #define UMCCH6_0_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
2445 #define UMCCH6_0_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
2446 #define UMCCH6_0_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
2447 #define UMCCH6_0_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
2448 #define UMCCH6_0_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
2449 //UMCCH6_0_PerfMonCtr6_Lo
2450 #define UMCCH6_0_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
2451 #define UMCCH6_0_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
2452 //UMCCH6_0_PerfMonCtr6_Hi
2453 #define UMCCH6_0_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
2454 #define UMCCH6_0_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
2455 #define UMCCH6_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
2456 #define UMCCH6_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
2457 #define UMCCH6_0_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
2458 #define UMCCH6_0_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
2459 #define UMCCH6_0_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2460 #define UMCCH6_0_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2461 //UMCCH6_0_PerfMonCtl7
2462 #define UMCCH6_0_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
2463 #define UMCCH6_0_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
2464 #define UMCCH6_0_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
2465 #define UMCCH6_0_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
2466 #define UMCCH6_0_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
2467 #define UMCCH6_0_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
2468 #define UMCCH6_0_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
2469 #define UMCCH6_0_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
2470 #define UMCCH6_0_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
2471 #define UMCCH6_0_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
2472 #define UMCCH6_0_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
2473 #define UMCCH6_0_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
2474 #define UMCCH6_0_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
2475 #define UMCCH6_0_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
2476 #define UMCCH6_0_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
2477 #define UMCCH6_0_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
2478 //UMCCH6_0_PerfMonCtr7_Lo
2479 #define UMCCH6_0_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
2480 #define UMCCH6_0_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
2481 //UMCCH6_0_PerfMonCtr7_Hi
2482 #define UMCCH6_0_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
2483 #define UMCCH6_0_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
2484 #define UMCCH6_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
2485 #define UMCCH6_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
2486 #define UMCCH6_0_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
2487 #define UMCCH6_0_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
2488 #define UMCCH6_0_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2489 #define UMCCH6_0_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2490 //UMCCH6_0_PerfMonCtl8
2491 #define UMCCH6_0_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
2492 #define UMCCH6_0_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
2493 #define UMCCH6_0_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
2494 #define UMCCH6_0_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
2495 #define UMCCH6_0_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
2496 #define UMCCH6_0_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
2497 #define UMCCH6_0_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
2498 #define UMCCH6_0_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
2499 #define UMCCH6_0_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
2500 #define UMCCH6_0_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
2501 #define UMCCH6_0_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
2502 #define UMCCH6_0_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
2503 #define UMCCH6_0_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
2504 #define UMCCH6_0_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
2505 #define UMCCH6_0_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
2506 #define UMCCH6_0_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
2507 //UMCCH6_0_PerfMonCtr8_Lo
2508 #define UMCCH6_0_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
2509 #define UMCCH6_0_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
2510 //UMCCH6_0_PerfMonCtr8_Hi
2511 #define UMCCH6_0_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
2512 #define UMCCH6_0_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
2513 #define UMCCH6_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
2514 #define UMCCH6_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
2515 #define UMCCH6_0_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
2516 #define UMCCH6_0_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
2517 #define UMCCH6_0_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2518 #define UMCCH6_0_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2519 
2520 
2521 // addressBlock: umc_w_phy_umc0_umcch7_umcchdec
2522 //UMCCH7_0_BaseAddrCS0
2523 #define UMCCH7_0_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
2524 #define UMCCH7_0_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
2525 #define UMCCH7_0_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
2526 #define UMCCH7_0_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
2527 //UMCCH7_0_AddrMaskCS01
2528 #define UMCCH7_0_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
2529 #define UMCCH7_0_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
2530 //UMCCH7_0_AddrSelCS01
2531 #define UMCCH7_0_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
2532 #define UMCCH7_0_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
2533 #define UMCCH7_0_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
2534 #define UMCCH7_0_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
2535 #define UMCCH7_0_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
2536 #define UMCCH7_0_AddrSelCS01__RowLo__SHIFT                                                                    0x18
2537 #define UMCCH7_0_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
2538 #define UMCCH7_0_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
2539 #define UMCCH7_0_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
2540 #define UMCCH7_0_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
2541 #define UMCCH7_0_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
2542 #define UMCCH7_0_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
2543 #define UMCCH7_0_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
2544 #define UMCCH7_0_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
2545 //UMCCH7_0_AddrHashBank0
2546 #define UMCCH7_0_AddrHashBank0__XorEnable__SHIFT                                                              0x0
2547 #define UMCCH7_0_AddrHashBank0__ColXor__SHIFT                                                                 0x1
2548 #define UMCCH7_0_AddrHashBank0__RowXor__SHIFT                                                                 0xe
2549 #define UMCCH7_0_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
2550 #define UMCCH7_0_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
2551 #define UMCCH7_0_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
2552 //UMCCH7_0_AddrHashBank1
2553 #define UMCCH7_0_AddrHashBank1__XorEnable__SHIFT                                                              0x0
2554 #define UMCCH7_0_AddrHashBank1__ColXor__SHIFT                                                                 0x1
2555 #define UMCCH7_0_AddrHashBank1__RowXor__SHIFT                                                                 0xe
2556 #define UMCCH7_0_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
2557 #define UMCCH7_0_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
2558 #define UMCCH7_0_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
2559 //UMCCH7_0_AddrHashBank2
2560 #define UMCCH7_0_AddrHashBank2__XorEnable__SHIFT                                                              0x0
2561 #define UMCCH7_0_AddrHashBank2__ColXor__SHIFT                                                                 0x1
2562 #define UMCCH7_0_AddrHashBank2__RowXor__SHIFT                                                                 0xe
2563 #define UMCCH7_0_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
2564 #define UMCCH7_0_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
2565 #define UMCCH7_0_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
2566 //UMCCH7_0_AddrHashBank3
2567 #define UMCCH7_0_AddrHashBank3__XorEnable__SHIFT                                                              0x0
2568 #define UMCCH7_0_AddrHashBank3__ColXor__SHIFT                                                                 0x1
2569 #define UMCCH7_0_AddrHashBank3__RowXor__SHIFT                                                                 0xe
2570 #define UMCCH7_0_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
2571 #define UMCCH7_0_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
2572 #define UMCCH7_0_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
2573 //UMCCH7_0_AddrHashBank4
2574 #define UMCCH7_0_AddrHashBank4__XorEnable__SHIFT                                                              0x0
2575 #define UMCCH7_0_AddrHashBank4__ColXor__SHIFT                                                                 0x1
2576 #define UMCCH7_0_AddrHashBank4__RowXor__SHIFT                                                                 0xe
2577 #define UMCCH7_0_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
2578 #define UMCCH7_0_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
2579 #define UMCCH7_0_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
2580 //UMCCH7_0_AddrHashBank5
2581 #define UMCCH7_0_AddrHashBank5__XorEnable__SHIFT                                                              0x0
2582 #define UMCCH7_0_AddrHashBank5__ColXor__SHIFT                                                                 0x1
2583 #define UMCCH7_0_AddrHashBank5__RowXor__SHIFT                                                                 0xe
2584 #define UMCCH7_0_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
2585 #define UMCCH7_0_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
2586 #define UMCCH7_0_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
2587 //UMCCH7_0_EccErrCntSel
2588 #define UMCCH7_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
2589 #define UMCCH7_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
2590 #define UMCCH7_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
2591 #define UMCCH7_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
2592 #define UMCCH7_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
2593 #define UMCCH7_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
2594 //UMCCH7_0_EccErrCnt
2595 #define UMCCH7_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
2596 #define UMCCH7_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
2597 //UMCCH7_0_PerfMonCtlClk
2598 #define UMCCH7_0_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
2599 #define UMCCH7_0_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
2600 #define UMCCH7_0_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
2601 #define UMCCH7_0_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
2602 #define UMCCH7_0_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
2603 #define UMCCH7_0_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
2604 #define UMCCH7_0_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
2605 #define UMCCH7_0_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
2606 #define UMCCH7_0_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
2607 #define UMCCH7_0_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
2608 #define UMCCH7_0_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
2609 #define UMCCH7_0_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
2610 //UMCCH7_0_PerfMonCtrClk_Lo
2611 #define UMCCH7_0_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
2612 #define UMCCH7_0_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
2613 //UMCCH7_0_PerfMonCtrClk_Hi
2614 #define UMCCH7_0_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
2615 #define UMCCH7_0_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
2616 #define UMCCH7_0_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
2617 #define UMCCH7_0_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
2618 //UMCCH7_0_PerfMonCtl1
2619 #define UMCCH7_0_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
2620 #define UMCCH7_0_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
2621 #define UMCCH7_0_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
2622 #define UMCCH7_0_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
2623 #define UMCCH7_0_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
2624 #define UMCCH7_0_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
2625 #define UMCCH7_0_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
2626 #define UMCCH7_0_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
2627 #define UMCCH7_0_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
2628 #define UMCCH7_0_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
2629 #define UMCCH7_0_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
2630 #define UMCCH7_0_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
2631 #define UMCCH7_0_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
2632 #define UMCCH7_0_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
2633 #define UMCCH7_0_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
2634 #define UMCCH7_0_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
2635 //UMCCH7_0_PerfMonCtr1_Lo
2636 #define UMCCH7_0_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
2637 #define UMCCH7_0_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
2638 //UMCCH7_0_PerfMonCtr1_Hi
2639 #define UMCCH7_0_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
2640 #define UMCCH7_0_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
2641 #define UMCCH7_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
2642 #define UMCCH7_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
2643 #define UMCCH7_0_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
2644 #define UMCCH7_0_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
2645 #define UMCCH7_0_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2646 #define UMCCH7_0_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2647 //UMCCH7_0_PerfMonCtl2
2648 #define UMCCH7_0_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
2649 #define UMCCH7_0_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
2650 #define UMCCH7_0_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
2651 #define UMCCH7_0_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
2652 #define UMCCH7_0_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
2653 #define UMCCH7_0_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
2654 #define UMCCH7_0_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
2655 #define UMCCH7_0_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
2656 #define UMCCH7_0_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
2657 #define UMCCH7_0_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
2658 #define UMCCH7_0_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
2659 #define UMCCH7_0_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
2660 #define UMCCH7_0_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
2661 #define UMCCH7_0_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
2662 #define UMCCH7_0_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
2663 #define UMCCH7_0_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
2664 //UMCCH7_0_PerfMonCtr2_Lo
2665 #define UMCCH7_0_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
2666 #define UMCCH7_0_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
2667 //UMCCH7_0_PerfMonCtr2_Hi
2668 #define UMCCH7_0_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
2669 #define UMCCH7_0_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
2670 #define UMCCH7_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
2671 #define UMCCH7_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
2672 #define UMCCH7_0_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
2673 #define UMCCH7_0_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
2674 #define UMCCH7_0_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2675 #define UMCCH7_0_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2676 //UMCCH7_0_PerfMonCtl3
2677 #define UMCCH7_0_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
2678 #define UMCCH7_0_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
2679 #define UMCCH7_0_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
2680 #define UMCCH7_0_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
2681 #define UMCCH7_0_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
2682 #define UMCCH7_0_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
2683 #define UMCCH7_0_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
2684 #define UMCCH7_0_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
2685 #define UMCCH7_0_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
2686 #define UMCCH7_0_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
2687 #define UMCCH7_0_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
2688 #define UMCCH7_0_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
2689 #define UMCCH7_0_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
2690 #define UMCCH7_0_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
2691 #define UMCCH7_0_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
2692 #define UMCCH7_0_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
2693 //UMCCH7_0_PerfMonCtr3_Lo
2694 #define UMCCH7_0_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
2695 #define UMCCH7_0_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
2696 //UMCCH7_0_PerfMonCtr3_Hi
2697 #define UMCCH7_0_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
2698 #define UMCCH7_0_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
2699 #define UMCCH7_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
2700 #define UMCCH7_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
2701 #define UMCCH7_0_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
2702 #define UMCCH7_0_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
2703 #define UMCCH7_0_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2704 #define UMCCH7_0_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2705 //UMCCH7_0_PerfMonCtl4
2706 #define UMCCH7_0_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
2707 #define UMCCH7_0_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
2708 #define UMCCH7_0_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
2709 #define UMCCH7_0_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
2710 #define UMCCH7_0_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
2711 #define UMCCH7_0_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
2712 #define UMCCH7_0_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
2713 #define UMCCH7_0_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
2714 #define UMCCH7_0_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
2715 #define UMCCH7_0_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
2716 #define UMCCH7_0_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
2717 #define UMCCH7_0_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
2718 #define UMCCH7_0_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
2719 #define UMCCH7_0_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
2720 #define UMCCH7_0_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
2721 #define UMCCH7_0_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
2722 //UMCCH7_0_PerfMonCtr4_Lo
2723 #define UMCCH7_0_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
2724 #define UMCCH7_0_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
2725 //UMCCH7_0_PerfMonCtr4_Hi
2726 #define UMCCH7_0_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
2727 #define UMCCH7_0_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
2728 #define UMCCH7_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
2729 #define UMCCH7_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
2730 #define UMCCH7_0_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
2731 #define UMCCH7_0_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
2732 #define UMCCH7_0_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2733 #define UMCCH7_0_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2734 //UMCCH7_0_PerfMonCtl5
2735 #define UMCCH7_0_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
2736 #define UMCCH7_0_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
2737 #define UMCCH7_0_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
2738 #define UMCCH7_0_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
2739 #define UMCCH7_0_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
2740 #define UMCCH7_0_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
2741 #define UMCCH7_0_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
2742 #define UMCCH7_0_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
2743 #define UMCCH7_0_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
2744 #define UMCCH7_0_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
2745 #define UMCCH7_0_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
2746 #define UMCCH7_0_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
2747 #define UMCCH7_0_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
2748 #define UMCCH7_0_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
2749 #define UMCCH7_0_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
2750 #define UMCCH7_0_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
2751 //UMCCH7_0_PerfMonCtr5_Lo
2752 #define UMCCH7_0_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
2753 #define UMCCH7_0_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
2754 //UMCCH7_0_PerfMonCtr5_Hi
2755 #define UMCCH7_0_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
2756 #define UMCCH7_0_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
2757 #define UMCCH7_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
2758 #define UMCCH7_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
2759 #define UMCCH7_0_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
2760 #define UMCCH7_0_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
2761 #define UMCCH7_0_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2762 #define UMCCH7_0_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2763 //UMCCH7_0_PerfMonCtl6
2764 #define UMCCH7_0_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
2765 #define UMCCH7_0_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
2766 #define UMCCH7_0_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
2767 #define UMCCH7_0_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
2768 #define UMCCH7_0_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
2769 #define UMCCH7_0_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
2770 #define UMCCH7_0_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
2771 #define UMCCH7_0_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
2772 #define UMCCH7_0_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
2773 #define UMCCH7_0_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
2774 #define UMCCH7_0_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
2775 #define UMCCH7_0_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
2776 #define UMCCH7_0_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
2777 #define UMCCH7_0_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
2778 #define UMCCH7_0_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
2779 #define UMCCH7_0_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
2780 //UMCCH7_0_PerfMonCtr6_Lo
2781 #define UMCCH7_0_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
2782 #define UMCCH7_0_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
2783 //UMCCH7_0_PerfMonCtr6_Hi
2784 #define UMCCH7_0_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
2785 #define UMCCH7_0_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
2786 #define UMCCH7_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
2787 #define UMCCH7_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
2788 #define UMCCH7_0_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
2789 #define UMCCH7_0_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
2790 #define UMCCH7_0_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2791 #define UMCCH7_0_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2792 //UMCCH7_0_PerfMonCtl7
2793 #define UMCCH7_0_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
2794 #define UMCCH7_0_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
2795 #define UMCCH7_0_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
2796 #define UMCCH7_0_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
2797 #define UMCCH7_0_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
2798 #define UMCCH7_0_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
2799 #define UMCCH7_0_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
2800 #define UMCCH7_0_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
2801 #define UMCCH7_0_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
2802 #define UMCCH7_0_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
2803 #define UMCCH7_0_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
2804 #define UMCCH7_0_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
2805 #define UMCCH7_0_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
2806 #define UMCCH7_0_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
2807 #define UMCCH7_0_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
2808 #define UMCCH7_0_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
2809 //UMCCH7_0_PerfMonCtr7_Lo
2810 #define UMCCH7_0_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
2811 #define UMCCH7_0_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
2812 //UMCCH7_0_PerfMonCtr7_Hi
2813 #define UMCCH7_0_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
2814 #define UMCCH7_0_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
2815 #define UMCCH7_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
2816 #define UMCCH7_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
2817 #define UMCCH7_0_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
2818 #define UMCCH7_0_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
2819 #define UMCCH7_0_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2820 #define UMCCH7_0_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2821 //UMCCH7_0_PerfMonCtl8
2822 #define UMCCH7_0_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
2823 #define UMCCH7_0_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
2824 #define UMCCH7_0_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
2825 #define UMCCH7_0_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
2826 #define UMCCH7_0_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
2827 #define UMCCH7_0_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
2828 #define UMCCH7_0_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
2829 #define UMCCH7_0_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
2830 #define UMCCH7_0_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
2831 #define UMCCH7_0_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
2832 #define UMCCH7_0_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
2833 #define UMCCH7_0_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
2834 #define UMCCH7_0_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
2835 #define UMCCH7_0_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
2836 #define UMCCH7_0_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
2837 #define UMCCH7_0_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
2838 //UMCCH7_0_PerfMonCtr8_Lo
2839 #define UMCCH7_0_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
2840 #define UMCCH7_0_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
2841 //UMCCH7_0_PerfMonCtr8_Hi
2842 #define UMCCH7_0_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
2843 #define UMCCH7_0_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
2844 #define UMCCH7_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
2845 #define UMCCH7_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
2846 #define UMCCH7_0_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
2847 #define UMCCH7_0_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
2848 #define UMCCH7_0_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2849 #define UMCCH7_0_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2850 
2851 
2852 // addressBlock: umc_w_phy_umc1_umcch0_umcchdec
2853 //UMCCH0_1_BaseAddrCS0
2854 #define UMCCH0_1_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
2855 #define UMCCH0_1_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
2856 #define UMCCH0_1_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
2857 #define UMCCH0_1_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
2858 //UMCCH0_1_AddrMaskCS01
2859 #define UMCCH0_1_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
2860 #define UMCCH0_1_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
2861 //UMCCH0_1_AddrSelCS01
2862 #define UMCCH0_1_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
2863 #define UMCCH0_1_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
2864 #define UMCCH0_1_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
2865 #define UMCCH0_1_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
2866 #define UMCCH0_1_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
2867 #define UMCCH0_1_AddrSelCS01__RowLo__SHIFT                                                                    0x18
2868 #define UMCCH0_1_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
2869 #define UMCCH0_1_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
2870 #define UMCCH0_1_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
2871 #define UMCCH0_1_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
2872 #define UMCCH0_1_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
2873 #define UMCCH0_1_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
2874 #define UMCCH0_1_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
2875 #define UMCCH0_1_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
2876 //UMCCH0_1_AddrHashBank0
2877 #define UMCCH0_1_AddrHashBank0__XorEnable__SHIFT                                                              0x0
2878 #define UMCCH0_1_AddrHashBank0__ColXor__SHIFT                                                                 0x1
2879 #define UMCCH0_1_AddrHashBank0__RowXor__SHIFT                                                                 0xe
2880 #define UMCCH0_1_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
2881 #define UMCCH0_1_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
2882 #define UMCCH0_1_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
2883 //UMCCH0_1_AddrHashBank1
2884 #define UMCCH0_1_AddrHashBank1__XorEnable__SHIFT                                                              0x0
2885 #define UMCCH0_1_AddrHashBank1__ColXor__SHIFT                                                                 0x1
2886 #define UMCCH0_1_AddrHashBank1__RowXor__SHIFT                                                                 0xe
2887 #define UMCCH0_1_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
2888 #define UMCCH0_1_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
2889 #define UMCCH0_1_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
2890 //UMCCH0_1_AddrHashBank2
2891 #define UMCCH0_1_AddrHashBank2__XorEnable__SHIFT                                                              0x0
2892 #define UMCCH0_1_AddrHashBank2__ColXor__SHIFT                                                                 0x1
2893 #define UMCCH0_1_AddrHashBank2__RowXor__SHIFT                                                                 0xe
2894 #define UMCCH0_1_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
2895 #define UMCCH0_1_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
2896 #define UMCCH0_1_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
2897 //UMCCH0_1_AddrHashBank3
2898 #define UMCCH0_1_AddrHashBank3__XorEnable__SHIFT                                                              0x0
2899 #define UMCCH0_1_AddrHashBank3__ColXor__SHIFT                                                                 0x1
2900 #define UMCCH0_1_AddrHashBank3__RowXor__SHIFT                                                                 0xe
2901 #define UMCCH0_1_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
2902 #define UMCCH0_1_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
2903 #define UMCCH0_1_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
2904 //UMCCH0_1_AddrHashBank4
2905 #define UMCCH0_1_AddrHashBank4__XorEnable__SHIFT                                                              0x0
2906 #define UMCCH0_1_AddrHashBank4__ColXor__SHIFT                                                                 0x1
2907 #define UMCCH0_1_AddrHashBank4__RowXor__SHIFT                                                                 0xe
2908 #define UMCCH0_1_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
2909 #define UMCCH0_1_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
2910 #define UMCCH0_1_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
2911 //UMCCH0_1_AddrHashBank5
2912 #define UMCCH0_1_AddrHashBank5__XorEnable__SHIFT                                                              0x0
2913 #define UMCCH0_1_AddrHashBank5__ColXor__SHIFT                                                                 0x1
2914 #define UMCCH0_1_AddrHashBank5__RowXor__SHIFT                                                                 0xe
2915 #define UMCCH0_1_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
2916 #define UMCCH0_1_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
2917 #define UMCCH0_1_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
2918 //UMCCH0_1_EccErrCntSel
2919 #define UMCCH0_1_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
2920 #define UMCCH0_1_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
2921 #define UMCCH0_1_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
2922 #define UMCCH0_1_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
2923 #define UMCCH0_1_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
2924 #define UMCCH0_1_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
2925 //UMCCH0_1_EccErrCnt
2926 #define UMCCH0_1_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
2927 #define UMCCH0_1_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
2928 //UMCCH0_1_PerfMonCtlClk
2929 #define UMCCH0_1_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
2930 #define UMCCH0_1_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
2931 #define UMCCH0_1_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
2932 #define UMCCH0_1_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
2933 #define UMCCH0_1_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
2934 #define UMCCH0_1_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
2935 #define UMCCH0_1_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
2936 #define UMCCH0_1_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
2937 #define UMCCH0_1_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
2938 #define UMCCH0_1_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
2939 #define UMCCH0_1_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
2940 #define UMCCH0_1_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
2941 //UMCCH0_1_PerfMonCtrClk_Lo
2942 #define UMCCH0_1_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
2943 #define UMCCH0_1_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
2944 //UMCCH0_1_PerfMonCtrClk_Hi
2945 #define UMCCH0_1_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
2946 #define UMCCH0_1_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
2947 #define UMCCH0_1_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
2948 #define UMCCH0_1_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
2949 //UMCCH0_1_PerfMonCtl1
2950 #define UMCCH0_1_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
2951 #define UMCCH0_1_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
2952 #define UMCCH0_1_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
2953 #define UMCCH0_1_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
2954 #define UMCCH0_1_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
2955 #define UMCCH0_1_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
2956 #define UMCCH0_1_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
2957 #define UMCCH0_1_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
2958 #define UMCCH0_1_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
2959 #define UMCCH0_1_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
2960 #define UMCCH0_1_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
2961 #define UMCCH0_1_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
2962 #define UMCCH0_1_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
2963 #define UMCCH0_1_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
2964 #define UMCCH0_1_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
2965 #define UMCCH0_1_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
2966 //UMCCH0_1_PerfMonCtr1_Lo
2967 #define UMCCH0_1_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
2968 #define UMCCH0_1_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
2969 //UMCCH0_1_PerfMonCtr1_Hi
2970 #define UMCCH0_1_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
2971 #define UMCCH0_1_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
2972 #define UMCCH0_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
2973 #define UMCCH0_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
2974 #define UMCCH0_1_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
2975 #define UMCCH0_1_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
2976 #define UMCCH0_1_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
2977 #define UMCCH0_1_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
2978 //UMCCH0_1_PerfMonCtl2
2979 #define UMCCH0_1_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
2980 #define UMCCH0_1_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
2981 #define UMCCH0_1_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
2982 #define UMCCH0_1_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
2983 #define UMCCH0_1_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
2984 #define UMCCH0_1_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
2985 #define UMCCH0_1_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
2986 #define UMCCH0_1_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
2987 #define UMCCH0_1_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
2988 #define UMCCH0_1_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
2989 #define UMCCH0_1_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
2990 #define UMCCH0_1_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
2991 #define UMCCH0_1_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
2992 #define UMCCH0_1_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
2993 #define UMCCH0_1_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
2994 #define UMCCH0_1_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
2995 //UMCCH0_1_PerfMonCtr2_Lo
2996 #define UMCCH0_1_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
2997 #define UMCCH0_1_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
2998 //UMCCH0_1_PerfMonCtr2_Hi
2999 #define UMCCH0_1_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
3000 #define UMCCH0_1_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
3001 #define UMCCH0_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
3002 #define UMCCH0_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
3003 #define UMCCH0_1_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
3004 #define UMCCH0_1_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
3005 #define UMCCH0_1_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3006 #define UMCCH0_1_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3007 //UMCCH0_1_PerfMonCtl3
3008 #define UMCCH0_1_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
3009 #define UMCCH0_1_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
3010 #define UMCCH0_1_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
3011 #define UMCCH0_1_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
3012 #define UMCCH0_1_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
3013 #define UMCCH0_1_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
3014 #define UMCCH0_1_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
3015 #define UMCCH0_1_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
3016 #define UMCCH0_1_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
3017 #define UMCCH0_1_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
3018 #define UMCCH0_1_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
3019 #define UMCCH0_1_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
3020 #define UMCCH0_1_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
3021 #define UMCCH0_1_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
3022 #define UMCCH0_1_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
3023 #define UMCCH0_1_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
3024 //UMCCH0_1_PerfMonCtr3_Lo
3025 #define UMCCH0_1_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
3026 #define UMCCH0_1_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
3027 //UMCCH0_1_PerfMonCtr3_Hi
3028 #define UMCCH0_1_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
3029 #define UMCCH0_1_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
3030 #define UMCCH0_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
3031 #define UMCCH0_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
3032 #define UMCCH0_1_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
3033 #define UMCCH0_1_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
3034 #define UMCCH0_1_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3035 #define UMCCH0_1_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3036 //UMCCH0_1_PerfMonCtl4
3037 #define UMCCH0_1_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
3038 #define UMCCH0_1_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
3039 #define UMCCH0_1_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
3040 #define UMCCH0_1_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
3041 #define UMCCH0_1_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
3042 #define UMCCH0_1_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
3043 #define UMCCH0_1_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
3044 #define UMCCH0_1_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
3045 #define UMCCH0_1_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
3046 #define UMCCH0_1_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
3047 #define UMCCH0_1_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
3048 #define UMCCH0_1_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
3049 #define UMCCH0_1_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
3050 #define UMCCH0_1_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
3051 #define UMCCH0_1_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
3052 #define UMCCH0_1_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
3053 //UMCCH0_1_PerfMonCtr4_Lo
3054 #define UMCCH0_1_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
3055 #define UMCCH0_1_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
3056 //UMCCH0_1_PerfMonCtr4_Hi
3057 #define UMCCH0_1_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
3058 #define UMCCH0_1_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
3059 #define UMCCH0_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
3060 #define UMCCH0_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
3061 #define UMCCH0_1_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
3062 #define UMCCH0_1_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
3063 #define UMCCH0_1_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3064 #define UMCCH0_1_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3065 //UMCCH0_1_PerfMonCtl5
3066 #define UMCCH0_1_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
3067 #define UMCCH0_1_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
3068 #define UMCCH0_1_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
3069 #define UMCCH0_1_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
3070 #define UMCCH0_1_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
3071 #define UMCCH0_1_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
3072 #define UMCCH0_1_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
3073 #define UMCCH0_1_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
3074 #define UMCCH0_1_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
3075 #define UMCCH0_1_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
3076 #define UMCCH0_1_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
3077 #define UMCCH0_1_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
3078 #define UMCCH0_1_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
3079 #define UMCCH0_1_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
3080 #define UMCCH0_1_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
3081 #define UMCCH0_1_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
3082 //UMCCH0_1_PerfMonCtr5_Lo
3083 #define UMCCH0_1_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
3084 #define UMCCH0_1_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
3085 //UMCCH0_1_PerfMonCtr5_Hi
3086 #define UMCCH0_1_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
3087 #define UMCCH0_1_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
3088 #define UMCCH0_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
3089 #define UMCCH0_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
3090 #define UMCCH0_1_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
3091 #define UMCCH0_1_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
3092 #define UMCCH0_1_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3093 #define UMCCH0_1_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3094 //UMCCH0_1_PerfMonCtl6
3095 #define UMCCH0_1_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
3096 #define UMCCH0_1_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
3097 #define UMCCH0_1_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
3098 #define UMCCH0_1_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
3099 #define UMCCH0_1_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
3100 #define UMCCH0_1_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
3101 #define UMCCH0_1_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
3102 #define UMCCH0_1_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
3103 #define UMCCH0_1_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
3104 #define UMCCH0_1_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
3105 #define UMCCH0_1_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
3106 #define UMCCH0_1_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
3107 #define UMCCH0_1_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
3108 #define UMCCH0_1_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
3109 #define UMCCH0_1_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
3110 #define UMCCH0_1_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
3111 //UMCCH0_1_PerfMonCtr6_Lo
3112 #define UMCCH0_1_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
3113 #define UMCCH0_1_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
3114 //UMCCH0_1_PerfMonCtr6_Hi
3115 #define UMCCH0_1_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
3116 #define UMCCH0_1_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
3117 #define UMCCH0_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
3118 #define UMCCH0_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
3119 #define UMCCH0_1_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
3120 #define UMCCH0_1_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
3121 #define UMCCH0_1_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3122 #define UMCCH0_1_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3123 //UMCCH0_1_PerfMonCtl7
3124 #define UMCCH0_1_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
3125 #define UMCCH0_1_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
3126 #define UMCCH0_1_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
3127 #define UMCCH0_1_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
3128 #define UMCCH0_1_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
3129 #define UMCCH0_1_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
3130 #define UMCCH0_1_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
3131 #define UMCCH0_1_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
3132 #define UMCCH0_1_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
3133 #define UMCCH0_1_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
3134 #define UMCCH0_1_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
3135 #define UMCCH0_1_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
3136 #define UMCCH0_1_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
3137 #define UMCCH0_1_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
3138 #define UMCCH0_1_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
3139 #define UMCCH0_1_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
3140 //UMCCH0_1_PerfMonCtr7_Lo
3141 #define UMCCH0_1_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
3142 #define UMCCH0_1_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
3143 //UMCCH0_1_PerfMonCtr7_Hi
3144 #define UMCCH0_1_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
3145 #define UMCCH0_1_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
3146 #define UMCCH0_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
3147 #define UMCCH0_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
3148 #define UMCCH0_1_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
3149 #define UMCCH0_1_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
3150 #define UMCCH0_1_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3151 #define UMCCH0_1_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3152 //UMCCH0_1_PerfMonCtl8
3153 #define UMCCH0_1_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
3154 #define UMCCH0_1_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
3155 #define UMCCH0_1_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
3156 #define UMCCH0_1_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
3157 #define UMCCH0_1_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
3158 #define UMCCH0_1_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
3159 #define UMCCH0_1_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
3160 #define UMCCH0_1_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
3161 #define UMCCH0_1_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
3162 #define UMCCH0_1_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
3163 #define UMCCH0_1_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
3164 #define UMCCH0_1_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
3165 #define UMCCH0_1_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
3166 #define UMCCH0_1_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
3167 #define UMCCH0_1_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
3168 #define UMCCH0_1_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
3169 //UMCCH0_1_PerfMonCtr8_Lo
3170 #define UMCCH0_1_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
3171 #define UMCCH0_1_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
3172 //UMCCH0_1_PerfMonCtr8_Hi
3173 #define UMCCH0_1_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
3174 #define UMCCH0_1_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
3175 #define UMCCH0_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
3176 #define UMCCH0_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
3177 #define UMCCH0_1_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
3178 #define UMCCH0_1_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
3179 #define UMCCH0_1_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3180 #define UMCCH0_1_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3181 
3182 
3183 // addressBlock: umc_w_phy_umc1_umcch1_umcchdec
3184 //UMCCH1_1_BaseAddrCS0
3185 #define UMCCH1_1_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
3186 #define UMCCH1_1_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
3187 #define UMCCH1_1_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
3188 #define UMCCH1_1_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
3189 //UMCCH1_1_AddrMaskCS01
3190 #define UMCCH1_1_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
3191 #define UMCCH1_1_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
3192 //UMCCH1_1_AddrSelCS01
3193 #define UMCCH1_1_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
3194 #define UMCCH1_1_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
3195 #define UMCCH1_1_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
3196 #define UMCCH1_1_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
3197 #define UMCCH1_1_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
3198 #define UMCCH1_1_AddrSelCS01__RowLo__SHIFT                                                                    0x18
3199 #define UMCCH1_1_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
3200 #define UMCCH1_1_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
3201 #define UMCCH1_1_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
3202 #define UMCCH1_1_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
3203 #define UMCCH1_1_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
3204 #define UMCCH1_1_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
3205 #define UMCCH1_1_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
3206 #define UMCCH1_1_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
3207 //UMCCH1_1_AddrHashBank0
3208 #define UMCCH1_1_AddrHashBank0__XorEnable__SHIFT                                                              0x0
3209 #define UMCCH1_1_AddrHashBank0__ColXor__SHIFT                                                                 0x1
3210 #define UMCCH1_1_AddrHashBank0__RowXor__SHIFT                                                                 0xe
3211 #define UMCCH1_1_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
3212 #define UMCCH1_1_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
3213 #define UMCCH1_1_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
3214 //UMCCH1_1_AddrHashBank1
3215 #define UMCCH1_1_AddrHashBank1__XorEnable__SHIFT                                                              0x0
3216 #define UMCCH1_1_AddrHashBank1__ColXor__SHIFT                                                                 0x1
3217 #define UMCCH1_1_AddrHashBank1__RowXor__SHIFT                                                                 0xe
3218 #define UMCCH1_1_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
3219 #define UMCCH1_1_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
3220 #define UMCCH1_1_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
3221 //UMCCH1_1_AddrHashBank2
3222 #define UMCCH1_1_AddrHashBank2__XorEnable__SHIFT                                                              0x0
3223 #define UMCCH1_1_AddrHashBank2__ColXor__SHIFT                                                                 0x1
3224 #define UMCCH1_1_AddrHashBank2__RowXor__SHIFT                                                                 0xe
3225 #define UMCCH1_1_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
3226 #define UMCCH1_1_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
3227 #define UMCCH1_1_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
3228 //UMCCH1_1_AddrHashBank3
3229 #define UMCCH1_1_AddrHashBank3__XorEnable__SHIFT                                                              0x0
3230 #define UMCCH1_1_AddrHashBank3__ColXor__SHIFT                                                                 0x1
3231 #define UMCCH1_1_AddrHashBank3__RowXor__SHIFT                                                                 0xe
3232 #define UMCCH1_1_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
3233 #define UMCCH1_1_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
3234 #define UMCCH1_1_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
3235 //UMCCH1_1_AddrHashBank4
3236 #define UMCCH1_1_AddrHashBank4__XorEnable__SHIFT                                                              0x0
3237 #define UMCCH1_1_AddrHashBank4__ColXor__SHIFT                                                                 0x1
3238 #define UMCCH1_1_AddrHashBank4__RowXor__SHIFT                                                                 0xe
3239 #define UMCCH1_1_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
3240 #define UMCCH1_1_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
3241 #define UMCCH1_1_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
3242 //UMCCH1_1_AddrHashBank5
3243 #define UMCCH1_1_AddrHashBank5__XorEnable__SHIFT                                                              0x0
3244 #define UMCCH1_1_AddrHashBank5__ColXor__SHIFT                                                                 0x1
3245 #define UMCCH1_1_AddrHashBank5__RowXor__SHIFT                                                                 0xe
3246 #define UMCCH1_1_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
3247 #define UMCCH1_1_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
3248 #define UMCCH1_1_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
3249 //UMCCH1_1_EccErrCntSel
3250 #define UMCCH1_1_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
3251 #define UMCCH1_1_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
3252 #define UMCCH1_1_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
3253 #define UMCCH1_1_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
3254 #define UMCCH1_1_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
3255 #define UMCCH1_1_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
3256 //UMCCH1_1_EccErrCnt
3257 #define UMCCH1_1_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
3258 #define UMCCH1_1_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
3259 //UMCCH1_1_PerfMonCtlClk
3260 #define UMCCH1_1_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
3261 #define UMCCH1_1_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
3262 #define UMCCH1_1_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
3263 #define UMCCH1_1_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
3264 #define UMCCH1_1_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
3265 #define UMCCH1_1_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
3266 #define UMCCH1_1_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
3267 #define UMCCH1_1_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
3268 #define UMCCH1_1_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
3269 #define UMCCH1_1_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
3270 #define UMCCH1_1_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
3271 #define UMCCH1_1_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
3272 //UMCCH1_1_PerfMonCtrClk_Lo
3273 #define UMCCH1_1_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
3274 #define UMCCH1_1_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
3275 //UMCCH1_1_PerfMonCtrClk_Hi
3276 #define UMCCH1_1_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
3277 #define UMCCH1_1_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
3278 #define UMCCH1_1_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
3279 #define UMCCH1_1_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
3280 //UMCCH1_1_PerfMonCtl1
3281 #define UMCCH1_1_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
3282 #define UMCCH1_1_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
3283 #define UMCCH1_1_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
3284 #define UMCCH1_1_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
3285 #define UMCCH1_1_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
3286 #define UMCCH1_1_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
3287 #define UMCCH1_1_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
3288 #define UMCCH1_1_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
3289 #define UMCCH1_1_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
3290 #define UMCCH1_1_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
3291 #define UMCCH1_1_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
3292 #define UMCCH1_1_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
3293 #define UMCCH1_1_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
3294 #define UMCCH1_1_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
3295 #define UMCCH1_1_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
3296 #define UMCCH1_1_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
3297 //UMCCH1_1_PerfMonCtr1_Lo
3298 #define UMCCH1_1_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
3299 #define UMCCH1_1_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
3300 //UMCCH1_1_PerfMonCtr1_Hi
3301 #define UMCCH1_1_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
3302 #define UMCCH1_1_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
3303 #define UMCCH1_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
3304 #define UMCCH1_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
3305 #define UMCCH1_1_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
3306 #define UMCCH1_1_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
3307 #define UMCCH1_1_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3308 #define UMCCH1_1_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3309 //UMCCH1_1_PerfMonCtl2
3310 #define UMCCH1_1_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
3311 #define UMCCH1_1_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
3312 #define UMCCH1_1_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
3313 #define UMCCH1_1_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
3314 #define UMCCH1_1_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
3315 #define UMCCH1_1_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
3316 #define UMCCH1_1_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
3317 #define UMCCH1_1_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
3318 #define UMCCH1_1_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
3319 #define UMCCH1_1_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
3320 #define UMCCH1_1_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
3321 #define UMCCH1_1_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
3322 #define UMCCH1_1_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
3323 #define UMCCH1_1_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
3324 #define UMCCH1_1_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
3325 #define UMCCH1_1_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
3326 //UMCCH1_1_PerfMonCtr2_Lo
3327 #define UMCCH1_1_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
3328 #define UMCCH1_1_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
3329 //UMCCH1_1_PerfMonCtr2_Hi
3330 #define UMCCH1_1_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
3331 #define UMCCH1_1_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
3332 #define UMCCH1_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
3333 #define UMCCH1_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
3334 #define UMCCH1_1_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
3335 #define UMCCH1_1_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
3336 #define UMCCH1_1_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3337 #define UMCCH1_1_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3338 //UMCCH1_1_PerfMonCtl3
3339 #define UMCCH1_1_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
3340 #define UMCCH1_1_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
3341 #define UMCCH1_1_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
3342 #define UMCCH1_1_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
3343 #define UMCCH1_1_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
3344 #define UMCCH1_1_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
3345 #define UMCCH1_1_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
3346 #define UMCCH1_1_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
3347 #define UMCCH1_1_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
3348 #define UMCCH1_1_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
3349 #define UMCCH1_1_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
3350 #define UMCCH1_1_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
3351 #define UMCCH1_1_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
3352 #define UMCCH1_1_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
3353 #define UMCCH1_1_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
3354 #define UMCCH1_1_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
3355 //UMCCH1_1_PerfMonCtr3_Lo
3356 #define UMCCH1_1_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
3357 #define UMCCH1_1_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
3358 //UMCCH1_1_PerfMonCtr3_Hi
3359 #define UMCCH1_1_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
3360 #define UMCCH1_1_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
3361 #define UMCCH1_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
3362 #define UMCCH1_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
3363 #define UMCCH1_1_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
3364 #define UMCCH1_1_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
3365 #define UMCCH1_1_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3366 #define UMCCH1_1_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3367 //UMCCH1_1_PerfMonCtl4
3368 #define UMCCH1_1_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
3369 #define UMCCH1_1_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
3370 #define UMCCH1_1_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
3371 #define UMCCH1_1_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
3372 #define UMCCH1_1_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
3373 #define UMCCH1_1_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
3374 #define UMCCH1_1_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
3375 #define UMCCH1_1_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
3376 #define UMCCH1_1_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
3377 #define UMCCH1_1_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
3378 #define UMCCH1_1_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
3379 #define UMCCH1_1_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
3380 #define UMCCH1_1_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
3381 #define UMCCH1_1_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
3382 #define UMCCH1_1_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
3383 #define UMCCH1_1_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
3384 //UMCCH1_1_PerfMonCtr4_Lo
3385 #define UMCCH1_1_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
3386 #define UMCCH1_1_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
3387 //UMCCH1_1_PerfMonCtr4_Hi
3388 #define UMCCH1_1_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
3389 #define UMCCH1_1_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
3390 #define UMCCH1_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
3391 #define UMCCH1_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
3392 #define UMCCH1_1_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
3393 #define UMCCH1_1_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
3394 #define UMCCH1_1_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3395 #define UMCCH1_1_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3396 //UMCCH1_1_PerfMonCtl5
3397 #define UMCCH1_1_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
3398 #define UMCCH1_1_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
3399 #define UMCCH1_1_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
3400 #define UMCCH1_1_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
3401 #define UMCCH1_1_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
3402 #define UMCCH1_1_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
3403 #define UMCCH1_1_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
3404 #define UMCCH1_1_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
3405 #define UMCCH1_1_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
3406 #define UMCCH1_1_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
3407 #define UMCCH1_1_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
3408 #define UMCCH1_1_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
3409 #define UMCCH1_1_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
3410 #define UMCCH1_1_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
3411 #define UMCCH1_1_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
3412 #define UMCCH1_1_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
3413 //UMCCH1_1_PerfMonCtr5_Lo
3414 #define UMCCH1_1_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
3415 #define UMCCH1_1_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
3416 //UMCCH1_1_PerfMonCtr5_Hi
3417 #define UMCCH1_1_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
3418 #define UMCCH1_1_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
3419 #define UMCCH1_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
3420 #define UMCCH1_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
3421 #define UMCCH1_1_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
3422 #define UMCCH1_1_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
3423 #define UMCCH1_1_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3424 #define UMCCH1_1_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3425 //UMCCH1_1_PerfMonCtl6
3426 #define UMCCH1_1_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
3427 #define UMCCH1_1_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
3428 #define UMCCH1_1_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
3429 #define UMCCH1_1_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
3430 #define UMCCH1_1_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
3431 #define UMCCH1_1_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
3432 #define UMCCH1_1_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
3433 #define UMCCH1_1_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
3434 #define UMCCH1_1_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
3435 #define UMCCH1_1_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
3436 #define UMCCH1_1_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
3437 #define UMCCH1_1_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
3438 #define UMCCH1_1_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
3439 #define UMCCH1_1_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
3440 #define UMCCH1_1_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
3441 #define UMCCH1_1_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
3442 //UMCCH1_1_PerfMonCtr6_Lo
3443 #define UMCCH1_1_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
3444 #define UMCCH1_1_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
3445 //UMCCH1_1_PerfMonCtr6_Hi
3446 #define UMCCH1_1_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
3447 #define UMCCH1_1_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
3448 #define UMCCH1_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
3449 #define UMCCH1_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
3450 #define UMCCH1_1_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
3451 #define UMCCH1_1_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
3452 #define UMCCH1_1_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3453 #define UMCCH1_1_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3454 //UMCCH1_1_PerfMonCtl7
3455 #define UMCCH1_1_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
3456 #define UMCCH1_1_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
3457 #define UMCCH1_1_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
3458 #define UMCCH1_1_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
3459 #define UMCCH1_1_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
3460 #define UMCCH1_1_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
3461 #define UMCCH1_1_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
3462 #define UMCCH1_1_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
3463 #define UMCCH1_1_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
3464 #define UMCCH1_1_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
3465 #define UMCCH1_1_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
3466 #define UMCCH1_1_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
3467 #define UMCCH1_1_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
3468 #define UMCCH1_1_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
3469 #define UMCCH1_1_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
3470 #define UMCCH1_1_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
3471 //UMCCH1_1_PerfMonCtr7_Lo
3472 #define UMCCH1_1_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
3473 #define UMCCH1_1_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
3474 //UMCCH1_1_PerfMonCtr7_Hi
3475 #define UMCCH1_1_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
3476 #define UMCCH1_1_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
3477 #define UMCCH1_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
3478 #define UMCCH1_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
3479 #define UMCCH1_1_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
3480 #define UMCCH1_1_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
3481 #define UMCCH1_1_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3482 #define UMCCH1_1_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3483 //UMCCH1_1_PerfMonCtl8
3484 #define UMCCH1_1_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
3485 #define UMCCH1_1_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
3486 #define UMCCH1_1_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
3487 #define UMCCH1_1_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
3488 #define UMCCH1_1_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
3489 #define UMCCH1_1_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
3490 #define UMCCH1_1_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
3491 #define UMCCH1_1_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
3492 #define UMCCH1_1_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
3493 #define UMCCH1_1_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
3494 #define UMCCH1_1_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
3495 #define UMCCH1_1_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
3496 #define UMCCH1_1_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
3497 #define UMCCH1_1_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
3498 #define UMCCH1_1_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
3499 #define UMCCH1_1_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
3500 //UMCCH1_1_PerfMonCtr8_Lo
3501 #define UMCCH1_1_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
3502 #define UMCCH1_1_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
3503 //UMCCH1_1_PerfMonCtr8_Hi
3504 #define UMCCH1_1_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
3505 #define UMCCH1_1_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
3506 #define UMCCH1_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
3507 #define UMCCH1_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
3508 #define UMCCH1_1_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
3509 #define UMCCH1_1_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
3510 #define UMCCH1_1_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3511 #define UMCCH1_1_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3512 
3513 
3514 // addressBlock: umc_w_phy_umc1_umcch2_umcchdec
3515 //UMCCH2_1_BaseAddrCS0
3516 #define UMCCH2_1_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
3517 #define UMCCH2_1_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
3518 #define UMCCH2_1_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
3519 #define UMCCH2_1_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
3520 //UMCCH2_1_AddrMaskCS01
3521 #define UMCCH2_1_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
3522 #define UMCCH2_1_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
3523 //UMCCH2_1_AddrSelCS01
3524 #define UMCCH2_1_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
3525 #define UMCCH2_1_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
3526 #define UMCCH2_1_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
3527 #define UMCCH2_1_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
3528 #define UMCCH2_1_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
3529 #define UMCCH2_1_AddrSelCS01__RowLo__SHIFT                                                                    0x18
3530 #define UMCCH2_1_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
3531 #define UMCCH2_1_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
3532 #define UMCCH2_1_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
3533 #define UMCCH2_1_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
3534 #define UMCCH2_1_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
3535 #define UMCCH2_1_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
3536 #define UMCCH2_1_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
3537 #define UMCCH2_1_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
3538 //UMCCH2_1_AddrHashBank0
3539 #define UMCCH2_1_AddrHashBank0__XorEnable__SHIFT                                                              0x0
3540 #define UMCCH2_1_AddrHashBank0__ColXor__SHIFT                                                                 0x1
3541 #define UMCCH2_1_AddrHashBank0__RowXor__SHIFT                                                                 0xe
3542 #define UMCCH2_1_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
3543 #define UMCCH2_1_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
3544 #define UMCCH2_1_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
3545 //UMCCH2_1_AddrHashBank1
3546 #define UMCCH2_1_AddrHashBank1__XorEnable__SHIFT                                                              0x0
3547 #define UMCCH2_1_AddrHashBank1__ColXor__SHIFT                                                                 0x1
3548 #define UMCCH2_1_AddrHashBank1__RowXor__SHIFT                                                                 0xe
3549 #define UMCCH2_1_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
3550 #define UMCCH2_1_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
3551 #define UMCCH2_1_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
3552 //UMCCH2_1_AddrHashBank2
3553 #define UMCCH2_1_AddrHashBank2__XorEnable__SHIFT                                                              0x0
3554 #define UMCCH2_1_AddrHashBank2__ColXor__SHIFT                                                                 0x1
3555 #define UMCCH2_1_AddrHashBank2__RowXor__SHIFT                                                                 0xe
3556 #define UMCCH2_1_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
3557 #define UMCCH2_1_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
3558 #define UMCCH2_1_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
3559 //UMCCH2_1_AddrHashBank3
3560 #define UMCCH2_1_AddrHashBank3__XorEnable__SHIFT                                                              0x0
3561 #define UMCCH2_1_AddrHashBank3__ColXor__SHIFT                                                                 0x1
3562 #define UMCCH2_1_AddrHashBank3__RowXor__SHIFT                                                                 0xe
3563 #define UMCCH2_1_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
3564 #define UMCCH2_1_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
3565 #define UMCCH2_1_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
3566 //UMCCH2_1_AddrHashBank4
3567 #define UMCCH2_1_AddrHashBank4__XorEnable__SHIFT                                                              0x0
3568 #define UMCCH2_1_AddrHashBank4__ColXor__SHIFT                                                                 0x1
3569 #define UMCCH2_1_AddrHashBank4__RowXor__SHIFT                                                                 0xe
3570 #define UMCCH2_1_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
3571 #define UMCCH2_1_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
3572 #define UMCCH2_1_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
3573 //UMCCH2_1_AddrHashBank5
3574 #define UMCCH2_1_AddrHashBank5__XorEnable__SHIFT                                                              0x0
3575 #define UMCCH2_1_AddrHashBank5__ColXor__SHIFT                                                                 0x1
3576 #define UMCCH2_1_AddrHashBank5__RowXor__SHIFT                                                                 0xe
3577 #define UMCCH2_1_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
3578 #define UMCCH2_1_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
3579 #define UMCCH2_1_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
3580 //UMCCH2_1_EccErrCntSel
3581 #define UMCCH2_1_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
3582 #define UMCCH2_1_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
3583 #define UMCCH2_1_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
3584 #define UMCCH2_1_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
3585 #define UMCCH2_1_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
3586 #define UMCCH2_1_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
3587 //UMCCH2_1_EccErrCnt
3588 #define UMCCH2_1_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
3589 #define UMCCH2_1_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
3590 //UMCCH2_1_PerfMonCtlClk
3591 #define UMCCH2_1_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
3592 #define UMCCH2_1_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
3593 #define UMCCH2_1_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
3594 #define UMCCH2_1_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
3595 #define UMCCH2_1_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
3596 #define UMCCH2_1_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
3597 #define UMCCH2_1_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
3598 #define UMCCH2_1_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
3599 #define UMCCH2_1_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
3600 #define UMCCH2_1_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
3601 #define UMCCH2_1_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
3602 #define UMCCH2_1_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
3603 //UMCCH2_1_PerfMonCtrClk_Lo
3604 #define UMCCH2_1_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
3605 #define UMCCH2_1_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
3606 //UMCCH2_1_PerfMonCtrClk_Hi
3607 #define UMCCH2_1_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
3608 #define UMCCH2_1_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
3609 #define UMCCH2_1_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
3610 #define UMCCH2_1_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
3611 //UMCCH2_1_PerfMonCtl1
3612 #define UMCCH2_1_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
3613 #define UMCCH2_1_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
3614 #define UMCCH2_1_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
3615 #define UMCCH2_1_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
3616 #define UMCCH2_1_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
3617 #define UMCCH2_1_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
3618 #define UMCCH2_1_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
3619 #define UMCCH2_1_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
3620 #define UMCCH2_1_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
3621 #define UMCCH2_1_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
3622 #define UMCCH2_1_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
3623 #define UMCCH2_1_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
3624 #define UMCCH2_1_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
3625 #define UMCCH2_1_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
3626 #define UMCCH2_1_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
3627 #define UMCCH2_1_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
3628 //UMCCH2_1_PerfMonCtr1_Lo
3629 #define UMCCH2_1_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
3630 #define UMCCH2_1_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
3631 //UMCCH2_1_PerfMonCtr1_Hi
3632 #define UMCCH2_1_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
3633 #define UMCCH2_1_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
3634 #define UMCCH2_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
3635 #define UMCCH2_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
3636 #define UMCCH2_1_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
3637 #define UMCCH2_1_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
3638 #define UMCCH2_1_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3639 #define UMCCH2_1_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3640 //UMCCH2_1_PerfMonCtl2
3641 #define UMCCH2_1_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
3642 #define UMCCH2_1_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
3643 #define UMCCH2_1_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
3644 #define UMCCH2_1_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
3645 #define UMCCH2_1_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
3646 #define UMCCH2_1_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
3647 #define UMCCH2_1_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
3648 #define UMCCH2_1_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
3649 #define UMCCH2_1_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
3650 #define UMCCH2_1_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
3651 #define UMCCH2_1_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
3652 #define UMCCH2_1_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
3653 #define UMCCH2_1_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
3654 #define UMCCH2_1_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
3655 #define UMCCH2_1_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
3656 #define UMCCH2_1_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
3657 //UMCCH2_1_PerfMonCtr2_Lo
3658 #define UMCCH2_1_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
3659 #define UMCCH2_1_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
3660 //UMCCH2_1_PerfMonCtr2_Hi
3661 #define UMCCH2_1_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
3662 #define UMCCH2_1_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
3663 #define UMCCH2_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
3664 #define UMCCH2_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
3665 #define UMCCH2_1_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
3666 #define UMCCH2_1_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
3667 #define UMCCH2_1_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3668 #define UMCCH2_1_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3669 //UMCCH2_1_PerfMonCtl3
3670 #define UMCCH2_1_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
3671 #define UMCCH2_1_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
3672 #define UMCCH2_1_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
3673 #define UMCCH2_1_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
3674 #define UMCCH2_1_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
3675 #define UMCCH2_1_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
3676 #define UMCCH2_1_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
3677 #define UMCCH2_1_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
3678 #define UMCCH2_1_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
3679 #define UMCCH2_1_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
3680 #define UMCCH2_1_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
3681 #define UMCCH2_1_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
3682 #define UMCCH2_1_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
3683 #define UMCCH2_1_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
3684 #define UMCCH2_1_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
3685 #define UMCCH2_1_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
3686 //UMCCH2_1_PerfMonCtr3_Lo
3687 #define UMCCH2_1_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
3688 #define UMCCH2_1_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
3689 //UMCCH2_1_PerfMonCtr3_Hi
3690 #define UMCCH2_1_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
3691 #define UMCCH2_1_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
3692 #define UMCCH2_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
3693 #define UMCCH2_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
3694 #define UMCCH2_1_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
3695 #define UMCCH2_1_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
3696 #define UMCCH2_1_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3697 #define UMCCH2_1_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3698 //UMCCH2_1_PerfMonCtl4
3699 #define UMCCH2_1_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
3700 #define UMCCH2_1_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
3701 #define UMCCH2_1_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
3702 #define UMCCH2_1_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
3703 #define UMCCH2_1_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
3704 #define UMCCH2_1_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
3705 #define UMCCH2_1_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
3706 #define UMCCH2_1_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
3707 #define UMCCH2_1_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
3708 #define UMCCH2_1_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
3709 #define UMCCH2_1_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
3710 #define UMCCH2_1_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
3711 #define UMCCH2_1_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
3712 #define UMCCH2_1_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
3713 #define UMCCH2_1_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
3714 #define UMCCH2_1_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
3715 //UMCCH2_1_PerfMonCtr4_Lo
3716 #define UMCCH2_1_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
3717 #define UMCCH2_1_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
3718 //UMCCH2_1_PerfMonCtr4_Hi
3719 #define UMCCH2_1_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
3720 #define UMCCH2_1_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
3721 #define UMCCH2_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
3722 #define UMCCH2_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
3723 #define UMCCH2_1_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
3724 #define UMCCH2_1_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
3725 #define UMCCH2_1_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3726 #define UMCCH2_1_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3727 //UMCCH2_1_PerfMonCtl5
3728 #define UMCCH2_1_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
3729 #define UMCCH2_1_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
3730 #define UMCCH2_1_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
3731 #define UMCCH2_1_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
3732 #define UMCCH2_1_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
3733 #define UMCCH2_1_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
3734 #define UMCCH2_1_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
3735 #define UMCCH2_1_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
3736 #define UMCCH2_1_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
3737 #define UMCCH2_1_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
3738 #define UMCCH2_1_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
3739 #define UMCCH2_1_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
3740 #define UMCCH2_1_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
3741 #define UMCCH2_1_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
3742 #define UMCCH2_1_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
3743 #define UMCCH2_1_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
3744 //UMCCH2_1_PerfMonCtr5_Lo
3745 #define UMCCH2_1_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
3746 #define UMCCH2_1_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
3747 //UMCCH2_1_PerfMonCtr5_Hi
3748 #define UMCCH2_1_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
3749 #define UMCCH2_1_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
3750 #define UMCCH2_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
3751 #define UMCCH2_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
3752 #define UMCCH2_1_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
3753 #define UMCCH2_1_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
3754 #define UMCCH2_1_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3755 #define UMCCH2_1_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3756 //UMCCH2_1_PerfMonCtl6
3757 #define UMCCH2_1_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
3758 #define UMCCH2_1_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
3759 #define UMCCH2_1_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
3760 #define UMCCH2_1_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
3761 #define UMCCH2_1_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
3762 #define UMCCH2_1_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
3763 #define UMCCH2_1_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
3764 #define UMCCH2_1_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
3765 #define UMCCH2_1_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
3766 #define UMCCH2_1_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
3767 #define UMCCH2_1_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
3768 #define UMCCH2_1_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
3769 #define UMCCH2_1_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
3770 #define UMCCH2_1_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
3771 #define UMCCH2_1_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
3772 #define UMCCH2_1_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
3773 //UMCCH2_1_PerfMonCtr6_Lo
3774 #define UMCCH2_1_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
3775 #define UMCCH2_1_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
3776 //UMCCH2_1_PerfMonCtr6_Hi
3777 #define UMCCH2_1_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
3778 #define UMCCH2_1_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
3779 #define UMCCH2_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
3780 #define UMCCH2_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
3781 #define UMCCH2_1_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
3782 #define UMCCH2_1_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
3783 #define UMCCH2_1_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3784 #define UMCCH2_1_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3785 //UMCCH2_1_PerfMonCtl7
3786 #define UMCCH2_1_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
3787 #define UMCCH2_1_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
3788 #define UMCCH2_1_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
3789 #define UMCCH2_1_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
3790 #define UMCCH2_1_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
3791 #define UMCCH2_1_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
3792 #define UMCCH2_1_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
3793 #define UMCCH2_1_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
3794 #define UMCCH2_1_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
3795 #define UMCCH2_1_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
3796 #define UMCCH2_1_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
3797 #define UMCCH2_1_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
3798 #define UMCCH2_1_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
3799 #define UMCCH2_1_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
3800 #define UMCCH2_1_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
3801 #define UMCCH2_1_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
3802 //UMCCH2_1_PerfMonCtr7_Lo
3803 #define UMCCH2_1_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
3804 #define UMCCH2_1_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
3805 //UMCCH2_1_PerfMonCtr7_Hi
3806 #define UMCCH2_1_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
3807 #define UMCCH2_1_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
3808 #define UMCCH2_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
3809 #define UMCCH2_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
3810 #define UMCCH2_1_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
3811 #define UMCCH2_1_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
3812 #define UMCCH2_1_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3813 #define UMCCH2_1_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3814 //UMCCH2_1_PerfMonCtl8
3815 #define UMCCH2_1_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
3816 #define UMCCH2_1_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
3817 #define UMCCH2_1_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
3818 #define UMCCH2_1_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
3819 #define UMCCH2_1_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
3820 #define UMCCH2_1_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
3821 #define UMCCH2_1_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
3822 #define UMCCH2_1_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
3823 #define UMCCH2_1_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
3824 #define UMCCH2_1_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
3825 #define UMCCH2_1_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
3826 #define UMCCH2_1_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
3827 #define UMCCH2_1_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
3828 #define UMCCH2_1_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
3829 #define UMCCH2_1_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
3830 #define UMCCH2_1_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
3831 //UMCCH2_1_PerfMonCtr8_Lo
3832 #define UMCCH2_1_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
3833 #define UMCCH2_1_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
3834 //UMCCH2_1_PerfMonCtr8_Hi
3835 #define UMCCH2_1_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
3836 #define UMCCH2_1_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
3837 #define UMCCH2_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
3838 #define UMCCH2_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
3839 #define UMCCH2_1_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
3840 #define UMCCH2_1_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
3841 #define UMCCH2_1_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3842 #define UMCCH2_1_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3843 
3844 
3845 // addressBlock: umc_w_phy_umc1_umcch3_umcchdec
3846 //UMCCH3_1_BaseAddrCS0
3847 #define UMCCH3_1_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
3848 #define UMCCH3_1_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
3849 #define UMCCH3_1_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
3850 #define UMCCH3_1_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
3851 //UMCCH3_1_AddrMaskCS01
3852 #define UMCCH3_1_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
3853 #define UMCCH3_1_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
3854 //UMCCH3_1_AddrSelCS01
3855 #define UMCCH3_1_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
3856 #define UMCCH3_1_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
3857 #define UMCCH3_1_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
3858 #define UMCCH3_1_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
3859 #define UMCCH3_1_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
3860 #define UMCCH3_1_AddrSelCS01__RowLo__SHIFT                                                                    0x18
3861 #define UMCCH3_1_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
3862 #define UMCCH3_1_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
3863 #define UMCCH3_1_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
3864 #define UMCCH3_1_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
3865 #define UMCCH3_1_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
3866 #define UMCCH3_1_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
3867 #define UMCCH3_1_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
3868 #define UMCCH3_1_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
3869 //UMCCH3_1_AddrHashBank0
3870 #define UMCCH3_1_AddrHashBank0__XorEnable__SHIFT                                                              0x0
3871 #define UMCCH3_1_AddrHashBank0__ColXor__SHIFT                                                                 0x1
3872 #define UMCCH3_1_AddrHashBank0__RowXor__SHIFT                                                                 0xe
3873 #define UMCCH3_1_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
3874 #define UMCCH3_1_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
3875 #define UMCCH3_1_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
3876 //UMCCH3_1_AddrHashBank1
3877 #define UMCCH3_1_AddrHashBank1__XorEnable__SHIFT                                                              0x0
3878 #define UMCCH3_1_AddrHashBank1__ColXor__SHIFT                                                                 0x1
3879 #define UMCCH3_1_AddrHashBank1__RowXor__SHIFT                                                                 0xe
3880 #define UMCCH3_1_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
3881 #define UMCCH3_1_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
3882 #define UMCCH3_1_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
3883 //UMCCH3_1_AddrHashBank2
3884 #define UMCCH3_1_AddrHashBank2__XorEnable__SHIFT                                                              0x0
3885 #define UMCCH3_1_AddrHashBank2__ColXor__SHIFT                                                                 0x1
3886 #define UMCCH3_1_AddrHashBank2__RowXor__SHIFT                                                                 0xe
3887 #define UMCCH3_1_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
3888 #define UMCCH3_1_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
3889 #define UMCCH3_1_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
3890 //UMCCH3_1_AddrHashBank3
3891 #define UMCCH3_1_AddrHashBank3__XorEnable__SHIFT                                                              0x0
3892 #define UMCCH3_1_AddrHashBank3__ColXor__SHIFT                                                                 0x1
3893 #define UMCCH3_1_AddrHashBank3__RowXor__SHIFT                                                                 0xe
3894 #define UMCCH3_1_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
3895 #define UMCCH3_1_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
3896 #define UMCCH3_1_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
3897 //UMCCH3_1_AddrHashBank4
3898 #define UMCCH3_1_AddrHashBank4__XorEnable__SHIFT                                                              0x0
3899 #define UMCCH3_1_AddrHashBank4__ColXor__SHIFT                                                                 0x1
3900 #define UMCCH3_1_AddrHashBank4__RowXor__SHIFT                                                                 0xe
3901 #define UMCCH3_1_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
3902 #define UMCCH3_1_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
3903 #define UMCCH3_1_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
3904 //UMCCH3_1_AddrHashBank5
3905 #define UMCCH3_1_AddrHashBank5__XorEnable__SHIFT                                                              0x0
3906 #define UMCCH3_1_AddrHashBank5__ColXor__SHIFT                                                                 0x1
3907 #define UMCCH3_1_AddrHashBank5__RowXor__SHIFT                                                                 0xe
3908 #define UMCCH3_1_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
3909 #define UMCCH3_1_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
3910 #define UMCCH3_1_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
3911 //UMCCH3_1_EccErrCntSel
3912 #define UMCCH3_1_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
3913 #define UMCCH3_1_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
3914 #define UMCCH3_1_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
3915 #define UMCCH3_1_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
3916 #define UMCCH3_1_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
3917 #define UMCCH3_1_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
3918 //UMCCH3_1_EccErrCnt
3919 #define UMCCH3_1_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
3920 #define UMCCH3_1_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
3921 //UMCCH3_1_PerfMonCtlClk
3922 #define UMCCH3_1_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
3923 #define UMCCH3_1_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
3924 #define UMCCH3_1_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
3925 #define UMCCH3_1_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
3926 #define UMCCH3_1_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
3927 #define UMCCH3_1_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
3928 #define UMCCH3_1_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
3929 #define UMCCH3_1_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
3930 #define UMCCH3_1_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
3931 #define UMCCH3_1_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
3932 #define UMCCH3_1_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
3933 #define UMCCH3_1_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
3934 //UMCCH3_1_PerfMonCtrClk_Lo
3935 #define UMCCH3_1_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
3936 #define UMCCH3_1_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
3937 //UMCCH3_1_PerfMonCtrClk_Hi
3938 #define UMCCH3_1_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
3939 #define UMCCH3_1_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
3940 #define UMCCH3_1_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
3941 #define UMCCH3_1_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
3942 //UMCCH3_1_PerfMonCtl1
3943 #define UMCCH3_1_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
3944 #define UMCCH3_1_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
3945 #define UMCCH3_1_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
3946 #define UMCCH3_1_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
3947 #define UMCCH3_1_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
3948 #define UMCCH3_1_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
3949 #define UMCCH3_1_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
3950 #define UMCCH3_1_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
3951 #define UMCCH3_1_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
3952 #define UMCCH3_1_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
3953 #define UMCCH3_1_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
3954 #define UMCCH3_1_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
3955 #define UMCCH3_1_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
3956 #define UMCCH3_1_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
3957 #define UMCCH3_1_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
3958 #define UMCCH3_1_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
3959 //UMCCH3_1_PerfMonCtr1_Lo
3960 #define UMCCH3_1_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
3961 #define UMCCH3_1_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
3962 //UMCCH3_1_PerfMonCtr1_Hi
3963 #define UMCCH3_1_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
3964 #define UMCCH3_1_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
3965 #define UMCCH3_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
3966 #define UMCCH3_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
3967 #define UMCCH3_1_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
3968 #define UMCCH3_1_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
3969 #define UMCCH3_1_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3970 #define UMCCH3_1_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
3971 //UMCCH3_1_PerfMonCtl2
3972 #define UMCCH3_1_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
3973 #define UMCCH3_1_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
3974 #define UMCCH3_1_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
3975 #define UMCCH3_1_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
3976 #define UMCCH3_1_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
3977 #define UMCCH3_1_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
3978 #define UMCCH3_1_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
3979 #define UMCCH3_1_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
3980 #define UMCCH3_1_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
3981 #define UMCCH3_1_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
3982 #define UMCCH3_1_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
3983 #define UMCCH3_1_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
3984 #define UMCCH3_1_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
3985 #define UMCCH3_1_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
3986 #define UMCCH3_1_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
3987 #define UMCCH3_1_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
3988 //UMCCH3_1_PerfMonCtr2_Lo
3989 #define UMCCH3_1_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
3990 #define UMCCH3_1_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
3991 //UMCCH3_1_PerfMonCtr2_Hi
3992 #define UMCCH3_1_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
3993 #define UMCCH3_1_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
3994 #define UMCCH3_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
3995 #define UMCCH3_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
3996 #define UMCCH3_1_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
3997 #define UMCCH3_1_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
3998 #define UMCCH3_1_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
3999 #define UMCCH3_1_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4000 //UMCCH3_1_PerfMonCtl3
4001 #define UMCCH3_1_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
4002 #define UMCCH3_1_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
4003 #define UMCCH3_1_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
4004 #define UMCCH3_1_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
4005 #define UMCCH3_1_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
4006 #define UMCCH3_1_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
4007 #define UMCCH3_1_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
4008 #define UMCCH3_1_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
4009 #define UMCCH3_1_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
4010 #define UMCCH3_1_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
4011 #define UMCCH3_1_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
4012 #define UMCCH3_1_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
4013 #define UMCCH3_1_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
4014 #define UMCCH3_1_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
4015 #define UMCCH3_1_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
4016 #define UMCCH3_1_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
4017 //UMCCH3_1_PerfMonCtr3_Lo
4018 #define UMCCH3_1_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
4019 #define UMCCH3_1_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
4020 //UMCCH3_1_PerfMonCtr3_Hi
4021 #define UMCCH3_1_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
4022 #define UMCCH3_1_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
4023 #define UMCCH3_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
4024 #define UMCCH3_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
4025 #define UMCCH3_1_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
4026 #define UMCCH3_1_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
4027 #define UMCCH3_1_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4028 #define UMCCH3_1_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4029 //UMCCH3_1_PerfMonCtl4
4030 #define UMCCH3_1_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
4031 #define UMCCH3_1_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
4032 #define UMCCH3_1_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
4033 #define UMCCH3_1_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
4034 #define UMCCH3_1_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
4035 #define UMCCH3_1_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
4036 #define UMCCH3_1_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
4037 #define UMCCH3_1_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
4038 #define UMCCH3_1_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
4039 #define UMCCH3_1_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
4040 #define UMCCH3_1_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
4041 #define UMCCH3_1_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
4042 #define UMCCH3_1_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
4043 #define UMCCH3_1_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
4044 #define UMCCH3_1_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
4045 #define UMCCH3_1_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
4046 //UMCCH3_1_PerfMonCtr4_Lo
4047 #define UMCCH3_1_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
4048 #define UMCCH3_1_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
4049 //UMCCH3_1_PerfMonCtr4_Hi
4050 #define UMCCH3_1_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
4051 #define UMCCH3_1_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
4052 #define UMCCH3_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
4053 #define UMCCH3_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
4054 #define UMCCH3_1_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
4055 #define UMCCH3_1_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
4056 #define UMCCH3_1_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4057 #define UMCCH3_1_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4058 //UMCCH3_1_PerfMonCtl5
4059 #define UMCCH3_1_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
4060 #define UMCCH3_1_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
4061 #define UMCCH3_1_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
4062 #define UMCCH3_1_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
4063 #define UMCCH3_1_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
4064 #define UMCCH3_1_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
4065 #define UMCCH3_1_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
4066 #define UMCCH3_1_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
4067 #define UMCCH3_1_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
4068 #define UMCCH3_1_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
4069 #define UMCCH3_1_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
4070 #define UMCCH3_1_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
4071 #define UMCCH3_1_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
4072 #define UMCCH3_1_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
4073 #define UMCCH3_1_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
4074 #define UMCCH3_1_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
4075 //UMCCH3_1_PerfMonCtr5_Lo
4076 #define UMCCH3_1_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
4077 #define UMCCH3_1_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
4078 //UMCCH3_1_PerfMonCtr5_Hi
4079 #define UMCCH3_1_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
4080 #define UMCCH3_1_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
4081 #define UMCCH3_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
4082 #define UMCCH3_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
4083 #define UMCCH3_1_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
4084 #define UMCCH3_1_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
4085 #define UMCCH3_1_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4086 #define UMCCH3_1_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4087 //UMCCH3_1_PerfMonCtl6
4088 #define UMCCH3_1_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
4089 #define UMCCH3_1_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
4090 #define UMCCH3_1_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
4091 #define UMCCH3_1_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
4092 #define UMCCH3_1_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
4093 #define UMCCH3_1_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
4094 #define UMCCH3_1_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
4095 #define UMCCH3_1_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
4096 #define UMCCH3_1_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
4097 #define UMCCH3_1_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
4098 #define UMCCH3_1_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
4099 #define UMCCH3_1_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
4100 #define UMCCH3_1_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
4101 #define UMCCH3_1_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
4102 #define UMCCH3_1_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
4103 #define UMCCH3_1_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
4104 //UMCCH3_1_PerfMonCtr6_Lo
4105 #define UMCCH3_1_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
4106 #define UMCCH3_1_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
4107 //UMCCH3_1_PerfMonCtr6_Hi
4108 #define UMCCH3_1_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
4109 #define UMCCH3_1_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
4110 #define UMCCH3_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
4111 #define UMCCH3_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
4112 #define UMCCH3_1_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
4113 #define UMCCH3_1_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
4114 #define UMCCH3_1_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4115 #define UMCCH3_1_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4116 //UMCCH3_1_PerfMonCtl7
4117 #define UMCCH3_1_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
4118 #define UMCCH3_1_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
4119 #define UMCCH3_1_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
4120 #define UMCCH3_1_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
4121 #define UMCCH3_1_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
4122 #define UMCCH3_1_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
4123 #define UMCCH3_1_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
4124 #define UMCCH3_1_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
4125 #define UMCCH3_1_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
4126 #define UMCCH3_1_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
4127 #define UMCCH3_1_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
4128 #define UMCCH3_1_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
4129 #define UMCCH3_1_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
4130 #define UMCCH3_1_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
4131 #define UMCCH3_1_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
4132 #define UMCCH3_1_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
4133 //UMCCH3_1_PerfMonCtr7_Lo
4134 #define UMCCH3_1_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
4135 #define UMCCH3_1_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
4136 //UMCCH3_1_PerfMonCtr7_Hi
4137 #define UMCCH3_1_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
4138 #define UMCCH3_1_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
4139 #define UMCCH3_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
4140 #define UMCCH3_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
4141 #define UMCCH3_1_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
4142 #define UMCCH3_1_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
4143 #define UMCCH3_1_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4144 #define UMCCH3_1_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4145 //UMCCH3_1_PerfMonCtl8
4146 #define UMCCH3_1_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
4147 #define UMCCH3_1_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
4148 #define UMCCH3_1_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
4149 #define UMCCH3_1_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
4150 #define UMCCH3_1_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
4151 #define UMCCH3_1_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
4152 #define UMCCH3_1_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
4153 #define UMCCH3_1_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
4154 #define UMCCH3_1_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
4155 #define UMCCH3_1_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
4156 #define UMCCH3_1_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
4157 #define UMCCH3_1_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
4158 #define UMCCH3_1_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
4159 #define UMCCH3_1_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
4160 #define UMCCH3_1_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
4161 #define UMCCH3_1_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
4162 //UMCCH3_1_PerfMonCtr8_Lo
4163 #define UMCCH3_1_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
4164 #define UMCCH3_1_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
4165 //UMCCH3_1_PerfMonCtr8_Hi
4166 #define UMCCH3_1_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
4167 #define UMCCH3_1_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
4168 #define UMCCH3_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
4169 #define UMCCH3_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
4170 #define UMCCH3_1_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
4171 #define UMCCH3_1_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
4172 #define UMCCH3_1_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4173 #define UMCCH3_1_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4174 
4175 
4176 // addressBlock: umc_w_phy_umc1_umcch4_umcchdec
4177 //UMCCH4_1_BaseAddrCS0
4178 #define UMCCH4_1_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
4179 #define UMCCH4_1_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
4180 #define UMCCH4_1_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
4181 #define UMCCH4_1_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
4182 //UMCCH4_1_AddrMaskCS01
4183 #define UMCCH4_1_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
4184 #define UMCCH4_1_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
4185 //UMCCH4_1_AddrSelCS01
4186 #define UMCCH4_1_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
4187 #define UMCCH4_1_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
4188 #define UMCCH4_1_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
4189 #define UMCCH4_1_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
4190 #define UMCCH4_1_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
4191 #define UMCCH4_1_AddrSelCS01__RowLo__SHIFT                                                                    0x18
4192 #define UMCCH4_1_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
4193 #define UMCCH4_1_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
4194 #define UMCCH4_1_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
4195 #define UMCCH4_1_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
4196 #define UMCCH4_1_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
4197 #define UMCCH4_1_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
4198 #define UMCCH4_1_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
4199 #define UMCCH4_1_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
4200 //UMCCH4_1_AddrHashBank0
4201 #define UMCCH4_1_AddrHashBank0__XorEnable__SHIFT                                                              0x0
4202 #define UMCCH4_1_AddrHashBank0__ColXor__SHIFT                                                                 0x1
4203 #define UMCCH4_1_AddrHashBank0__RowXor__SHIFT                                                                 0xe
4204 #define UMCCH4_1_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
4205 #define UMCCH4_1_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
4206 #define UMCCH4_1_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
4207 //UMCCH4_1_AddrHashBank1
4208 #define UMCCH4_1_AddrHashBank1__XorEnable__SHIFT                                                              0x0
4209 #define UMCCH4_1_AddrHashBank1__ColXor__SHIFT                                                                 0x1
4210 #define UMCCH4_1_AddrHashBank1__RowXor__SHIFT                                                                 0xe
4211 #define UMCCH4_1_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
4212 #define UMCCH4_1_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
4213 #define UMCCH4_1_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
4214 //UMCCH4_1_AddrHashBank2
4215 #define UMCCH4_1_AddrHashBank2__XorEnable__SHIFT                                                              0x0
4216 #define UMCCH4_1_AddrHashBank2__ColXor__SHIFT                                                                 0x1
4217 #define UMCCH4_1_AddrHashBank2__RowXor__SHIFT                                                                 0xe
4218 #define UMCCH4_1_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
4219 #define UMCCH4_1_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
4220 #define UMCCH4_1_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
4221 //UMCCH4_1_AddrHashBank3
4222 #define UMCCH4_1_AddrHashBank3__XorEnable__SHIFT                                                              0x0
4223 #define UMCCH4_1_AddrHashBank3__ColXor__SHIFT                                                                 0x1
4224 #define UMCCH4_1_AddrHashBank3__RowXor__SHIFT                                                                 0xe
4225 #define UMCCH4_1_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
4226 #define UMCCH4_1_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
4227 #define UMCCH4_1_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
4228 //UMCCH4_1_AddrHashBank4
4229 #define UMCCH4_1_AddrHashBank4__XorEnable__SHIFT                                                              0x0
4230 #define UMCCH4_1_AddrHashBank4__ColXor__SHIFT                                                                 0x1
4231 #define UMCCH4_1_AddrHashBank4__RowXor__SHIFT                                                                 0xe
4232 #define UMCCH4_1_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
4233 #define UMCCH4_1_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
4234 #define UMCCH4_1_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
4235 //UMCCH4_1_AddrHashBank5
4236 #define UMCCH4_1_AddrHashBank5__XorEnable__SHIFT                                                              0x0
4237 #define UMCCH4_1_AddrHashBank5__ColXor__SHIFT                                                                 0x1
4238 #define UMCCH4_1_AddrHashBank5__RowXor__SHIFT                                                                 0xe
4239 #define UMCCH4_1_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
4240 #define UMCCH4_1_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
4241 #define UMCCH4_1_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
4242 //UMCCH4_1_EccErrCntSel
4243 #define UMCCH4_1_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
4244 #define UMCCH4_1_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
4245 #define UMCCH4_1_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
4246 #define UMCCH4_1_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
4247 #define UMCCH4_1_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
4248 #define UMCCH4_1_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
4249 //UMCCH4_1_EccErrCnt
4250 #define UMCCH4_1_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
4251 #define UMCCH4_1_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
4252 //UMCCH4_1_PerfMonCtlClk
4253 #define UMCCH4_1_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
4254 #define UMCCH4_1_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
4255 #define UMCCH4_1_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
4256 #define UMCCH4_1_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
4257 #define UMCCH4_1_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
4258 #define UMCCH4_1_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
4259 #define UMCCH4_1_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
4260 #define UMCCH4_1_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
4261 #define UMCCH4_1_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
4262 #define UMCCH4_1_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
4263 #define UMCCH4_1_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
4264 #define UMCCH4_1_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
4265 //UMCCH4_1_PerfMonCtrClk_Lo
4266 #define UMCCH4_1_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
4267 #define UMCCH4_1_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
4268 //UMCCH4_1_PerfMonCtrClk_Hi
4269 #define UMCCH4_1_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
4270 #define UMCCH4_1_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
4271 #define UMCCH4_1_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
4272 #define UMCCH4_1_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
4273 //UMCCH4_1_PerfMonCtl1
4274 #define UMCCH4_1_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
4275 #define UMCCH4_1_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
4276 #define UMCCH4_1_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
4277 #define UMCCH4_1_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
4278 #define UMCCH4_1_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
4279 #define UMCCH4_1_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
4280 #define UMCCH4_1_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
4281 #define UMCCH4_1_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
4282 #define UMCCH4_1_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
4283 #define UMCCH4_1_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
4284 #define UMCCH4_1_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
4285 #define UMCCH4_1_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
4286 #define UMCCH4_1_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
4287 #define UMCCH4_1_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
4288 #define UMCCH4_1_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
4289 #define UMCCH4_1_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
4290 //UMCCH4_1_PerfMonCtr1_Lo
4291 #define UMCCH4_1_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
4292 #define UMCCH4_1_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
4293 //UMCCH4_1_PerfMonCtr1_Hi
4294 #define UMCCH4_1_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
4295 #define UMCCH4_1_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
4296 #define UMCCH4_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
4297 #define UMCCH4_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
4298 #define UMCCH4_1_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
4299 #define UMCCH4_1_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
4300 #define UMCCH4_1_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4301 #define UMCCH4_1_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4302 //UMCCH4_1_PerfMonCtl2
4303 #define UMCCH4_1_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
4304 #define UMCCH4_1_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
4305 #define UMCCH4_1_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
4306 #define UMCCH4_1_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
4307 #define UMCCH4_1_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
4308 #define UMCCH4_1_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
4309 #define UMCCH4_1_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
4310 #define UMCCH4_1_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
4311 #define UMCCH4_1_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
4312 #define UMCCH4_1_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
4313 #define UMCCH4_1_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
4314 #define UMCCH4_1_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
4315 #define UMCCH4_1_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
4316 #define UMCCH4_1_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
4317 #define UMCCH4_1_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
4318 #define UMCCH4_1_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
4319 //UMCCH4_1_PerfMonCtr2_Lo
4320 #define UMCCH4_1_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
4321 #define UMCCH4_1_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
4322 //UMCCH4_1_PerfMonCtr2_Hi
4323 #define UMCCH4_1_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
4324 #define UMCCH4_1_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
4325 #define UMCCH4_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
4326 #define UMCCH4_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
4327 #define UMCCH4_1_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
4328 #define UMCCH4_1_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
4329 #define UMCCH4_1_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4330 #define UMCCH4_1_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4331 //UMCCH4_1_PerfMonCtl3
4332 #define UMCCH4_1_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
4333 #define UMCCH4_1_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
4334 #define UMCCH4_1_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
4335 #define UMCCH4_1_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
4336 #define UMCCH4_1_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
4337 #define UMCCH4_1_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
4338 #define UMCCH4_1_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
4339 #define UMCCH4_1_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
4340 #define UMCCH4_1_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
4341 #define UMCCH4_1_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
4342 #define UMCCH4_1_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
4343 #define UMCCH4_1_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
4344 #define UMCCH4_1_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
4345 #define UMCCH4_1_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
4346 #define UMCCH4_1_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
4347 #define UMCCH4_1_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
4348 //UMCCH4_1_PerfMonCtr3_Lo
4349 #define UMCCH4_1_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
4350 #define UMCCH4_1_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
4351 //UMCCH4_1_PerfMonCtr3_Hi
4352 #define UMCCH4_1_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
4353 #define UMCCH4_1_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
4354 #define UMCCH4_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
4355 #define UMCCH4_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
4356 #define UMCCH4_1_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
4357 #define UMCCH4_1_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
4358 #define UMCCH4_1_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4359 #define UMCCH4_1_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4360 //UMCCH4_1_PerfMonCtl4
4361 #define UMCCH4_1_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
4362 #define UMCCH4_1_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
4363 #define UMCCH4_1_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
4364 #define UMCCH4_1_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
4365 #define UMCCH4_1_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
4366 #define UMCCH4_1_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
4367 #define UMCCH4_1_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
4368 #define UMCCH4_1_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
4369 #define UMCCH4_1_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
4370 #define UMCCH4_1_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
4371 #define UMCCH4_1_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
4372 #define UMCCH4_1_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
4373 #define UMCCH4_1_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
4374 #define UMCCH4_1_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
4375 #define UMCCH4_1_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
4376 #define UMCCH4_1_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
4377 //UMCCH4_1_PerfMonCtr4_Lo
4378 #define UMCCH4_1_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
4379 #define UMCCH4_1_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
4380 //UMCCH4_1_PerfMonCtr4_Hi
4381 #define UMCCH4_1_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
4382 #define UMCCH4_1_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
4383 #define UMCCH4_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
4384 #define UMCCH4_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
4385 #define UMCCH4_1_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
4386 #define UMCCH4_1_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
4387 #define UMCCH4_1_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4388 #define UMCCH4_1_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4389 //UMCCH4_1_PerfMonCtl5
4390 #define UMCCH4_1_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
4391 #define UMCCH4_1_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
4392 #define UMCCH4_1_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
4393 #define UMCCH4_1_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
4394 #define UMCCH4_1_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
4395 #define UMCCH4_1_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
4396 #define UMCCH4_1_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
4397 #define UMCCH4_1_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
4398 #define UMCCH4_1_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
4399 #define UMCCH4_1_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
4400 #define UMCCH4_1_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
4401 #define UMCCH4_1_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
4402 #define UMCCH4_1_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
4403 #define UMCCH4_1_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
4404 #define UMCCH4_1_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
4405 #define UMCCH4_1_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
4406 //UMCCH4_1_PerfMonCtr5_Lo
4407 #define UMCCH4_1_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
4408 #define UMCCH4_1_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
4409 //UMCCH4_1_PerfMonCtr5_Hi
4410 #define UMCCH4_1_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
4411 #define UMCCH4_1_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
4412 #define UMCCH4_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
4413 #define UMCCH4_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
4414 #define UMCCH4_1_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
4415 #define UMCCH4_1_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
4416 #define UMCCH4_1_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4417 #define UMCCH4_1_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4418 //UMCCH4_1_PerfMonCtl6
4419 #define UMCCH4_1_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
4420 #define UMCCH4_1_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
4421 #define UMCCH4_1_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
4422 #define UMCCH4_1_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
4423 #define UMCCH4_1_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
4424 #define UMCCH4_1_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
4425 #define UMCCH4_1_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
4426 #define UMCCH4_1_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
4427 #define UMCCH4_1_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
4428 #define UMCCH4_1_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
4429 #define UMCCH4_1_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
4430 #define UMCCH4_1_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
4431 #define UMCCH4_1_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
4432 #define UMCCH4_1_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
4433 #define UMCCH4_1_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
4434 #define UMCCH4_1_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
4435 //UMCCH4_1_PerfMonCtr6_Lo
4436 #define UMCCH4_1_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
4437 #define UMCCH4_1_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
4438 //UMCCH4_1_PerfMonCtr6_Hi
4439 #define UMCCH4_1_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
4440 #define UMCCH4_1_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
4441 #define UMCCH4_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
4442 #define UMCCH4_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
4443 #define UMCCH4_1_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
4444 #define UMCCH4_1_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
4445 #define UMCCH4_1_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4446 #define UMCCH4_1_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4447 //UMCCH4_1_PerfMonCtl7
4448 #define UMCCH4_1_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
4449 #define UMCCH4_1_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
4450 #define UMCCH4_1_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
4451 #define UMCCH4_1_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
4452 #define UMCCH4_1_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
4453 #define UMCCH4_1_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
4454 #define UMCCH4_1_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
4455 #define UMCCH4_1_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
4456 #define UMCCH4_1_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
4457 #define UMCCH4_1_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
4458 #define UMCCH4_1_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
4459 #define UMCCH4_1_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
4460 #define UMCCH4_1_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
4461 #define UMCCH4_1_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
4462 #define UMCCH4_1_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
4463 #define UMCCH4_1_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
4464 //UMCCH4_1_PerfMonCtr7_Lo
4465 #define UMCCH4_1_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
4466 #define UMCCH4_1_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
4467 //UMCCH4_1_PerfMonCtr7_Hi
4468 #define UMCCH4_1_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
4469 #define UMCCH4_1_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
4470 #define UMCCH4_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
4471 #define UMCCH4_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
4472 #define UMCCH4_1_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
4473 #define UMCCH4_1_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
4474 #define UMCCH4_1_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4475 #define UMCCH4_1_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4476 //UMCCH4_1_PerfMonCtl8
4477 #define UMCCH4_1_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
4478 #define UMCCH4_1_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
4479 #define UMCCH4_1_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
4480 #define UMCCH4_1_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
4481 #define UMCCH4_1_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
4482 #define UMCCH4_1_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
4483 #define UMCCH4_1_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
4484 #define UMCCH4_1_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
4485 #define UMCCH4_1_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
4486 #define UMCCH4_1_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
4487 #define UMCCH4_1_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
4488 #define UMCCH4_1_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
4489 #define UMCCH4_1_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
4490 #define UMCCH4_1_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
4491 #define UMCCH4_1_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
4492 #define UMCCH4_1_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
4493 //UMCCH4_1_PerfMonCtr8_Lo
4494 #define UMCCH4_1_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
4495 #define UMCCH4_1_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
4496 //UMCCH4_1_PerfMonCtr8_Hi
4497 #define UMCCH4_1_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
4498 #define UMCCH4_1_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
4499 #define UMCCH4_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
4500 #define UMCCH4_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
4501 #define UMCCH4_1_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
4502 #define UMCCH4_1_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
4503 #define UMCCH4_1_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4504 #define UMCCH4_1_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4505 
4506 
4507 // addressBlock: umc_w_phy_umc1_umcch5_umcchdec
4508 //UMCCH5_1_BaseAddrCS0
4509 #define UMCCH5_1_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
4510 #define UMCCH5_1_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
4511 #define UMCCH5_1_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
4512 #define UMCCH5_1_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
4513 //UMCCH5_1_AddrMaskCS01
4514 #define UMCCH5_1_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
4515 #define UMCCH5_1_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
4516 //UMCCH5_1_AddrSelCS01
4517 #define UMCCH5_1_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
4518 #define UMCCH5_1_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
4519 #define UMCCH5_1_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
4520 #define UMCCH5_1_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
4521 #define UMCCH5_1_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
4522 #define UMCCH5_1_AddrSelCS01__RowLo__SHIFT                                                                    0x18
4523 #define UMCCH5_1_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
4524 #define UMCCH5_1_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
4525 #define UMCCH5_1_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
4526 #define UMCCH5_1_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
4527 #define UMCCH5_1_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
4528 #define UMCCH5_1_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
4529 #define UMCCH5_1_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
4530 #define UMCCH5_1_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
4531 //UMCCH5_1_AddrHashBank0
4532 #define UMCCH5_1_AddrHashBank0__XorEnable__SHIFT                                                              0x0
4533 #define UMCCH5_1_AddrHashBank0__ColXor__SHIFT                                                                 0x1
4534 #define UMCCH5_1_AddrHashBank0__RowXor__SHIFT                                                                 0xe
4535 #define UMCCH5_1_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
4536 #define UMCCH5_1_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
4537 #define UMCCH5_1_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
4538 //UMCCH5_1_AddrHashBank1
4539 #define UMCCH5_1_AddrHashBank1__XorEnable__SHIFT                                                              0x0
4540 #define UMCCH5_1_AddrHashBank1__ColXor__SHIFT                                                                 0x1
4541 #define UMCCH5_1_AddrHashBank1__RowXor__SHIFT                                                                 0xe
4542 #define UMCCH5_1_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
4543 #define UMCCH5_1_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
4544 #define UMCCH5_1_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
4545 //UMCCH5_1_AddrHashBank2
4546 #define UMCCH5_1_AddrHashBank2__XorEnable__SHIFT                                                              0x0
4547 #define UMCCH5_1_AddrHashBank2__ColXor__SHIFT                                                                 0x1
4548 #define UMCCH5_1_AddrHashBank2__RowXor__SHIFT                                                                 0xe
4549 #define UMCCH5_1_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
4550 #define UMCCH5_1_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
4551 #define UMCCH5_1_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
4552 //UMCCH5_1_AddrHashBank3
4553 #define UMCCH5_1_AddrHashBank3__XorEnable__SHIFT                                                              0x0
4554 #define UMCCH5_1_AddrHashBank3__ColXor__SHIFT                                                                 0x1
4555 #define UMCCH5_1_AddrHashBank3__RowXor__SHIFT                                                                 0xe
4556 #define UMCCH5_1_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
4557 #define UMCCH5_1_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
4558 #define UMCCH5_1_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
4559 //UMCCH5_1_AddrHashBank4
4560 #define UMCCH5_1_AddrHashBank4__XorEnable__SHIFT                                                              0x0
4561 #define UMCCH5_1_AddrHashBank4__ColXor__SHIFT                                                                 0x1
4562 #define UMCCH5_1_AddrHashBank4__RowXor__SHIFT                                                                 0xe
4563 #define UMCCH5_1_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
4564 #define UMCCH5_1_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
4565 #define UMCCH5_1_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
4566 //UMCCH5_1_AddrHashBank5
4567 #define UMCCH5_1_AddrHashBank5__XorEnable__SHIFT                                                              0x0
4568 #define UMCCH5_1_AddrHashBank5__ColXor__SHIFT                                                                 0x1
4569 #define UMCCH5_1_AddrHashBank5__RowXor__SHIFT                                                                 0xe
4570 #define UMCCH5_1_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
4571 #define UMCCH5_1_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
4572 #define UMCCH5_1_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
4573 //UMCCH5_1_EccErrCntSel
4574 #define UMCCH5_1_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
4575 #define UMCCH5_1_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
4576 #define UMCCH5_1_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
4577 #define UMCCH5_1_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
4578 #define UMCCH5_1_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
4579 #define UMCCH5_1_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
4580 //UMCCH5_1_EccErrCnt
4581 #define UMCCH5_1_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
4582 #define UMCCH5_1_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
4583 //UMCCH5_1_PerfMonCtlClk
4584 #define UMCCH5_1_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
4585 #define UMCCH5_1_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
4586 #define UMCCH5_1_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
4587 #define UMCCH5_1_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
4588 #define UMCCH5_1_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
4589 #define UMCCH5_1_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
4590 #define UMCCH5_1_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
4591 #define UMCCH5_1_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
4592 #define UMCCH5_1_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
4593 #define UMCCH5_1_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
4594 #define UMCCH5_1_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
4595 #define UMCCH5_1_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
4596 //UMCCH5_1_PerfMonCtrClk_Lo
4597 #define UMCCH5_1_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
4598 #define UMCCH5_1_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
4599 //UMCCH5_1_PerfMonCtrClk_Hi
4600 #define UMCCH5_1_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
4601 #define UMCCH5_1_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
4602 #define UMCCH5_1_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
4603 #define UMCCH5_1_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
4604 //UMCCH5_1_PerfMonCtl1
4605 #define UMCCH5_1_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
4606 #define UMCCH5_1_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
4607 #define UMCCH5_1_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
4608 #define UMCCH5_1_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
4609 #define UMCCH5_1_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
4610 #define UMCCH5_1_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
4611 #define UMCCH5_1_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
4612 #define UMCCH5_1_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
4613 #define UMCCH5_1_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
4614 #define UMCCH5_1_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
4615 #define UMCCH5_1_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
4616 #define UMCCH5_1_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
4617 #define UMCCH5_1_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
4618 #define UMCCH5_1_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
4619 #define UMCCH5_1_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
4620 #define UMCCH5_1_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
4621 //UMCCH5_1_PerfMonCtr1_Lo
4622 #define UMCCH5_1_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
4623 #define UMCCH5_1_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
4624 //UMCCH5_1_PerfMonCtr1_Hi
4625 #define UMCCH5_1_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
4626 #define UMCCH5_1_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
4627 #define UMCCH5_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
4628 #define UMCCH5_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
4629 #define UMCCH5_1_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
4630 #define UMCCH5_1_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
4631 #define UMCCH5_1_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4632 #define UMCCH5_1_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4633 //UMCCH5_1_PerfMonCtl2
4634 #define UMCCH5_1_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
4635 #define UMCCH5_1_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
4636 #define UMCCH5_1_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
4637 #define UMCCH5_1_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
4638 #define UMCCH5_1_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
4639 #define UMCCH5_1_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
4640 #define UMCCH5_1_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
4641 #define UMCCH5_1_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
4642 #define UMCCH5_1_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
4643 #define UMCCH5_1_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
4644 #define UMCCH5_1_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
4645 #define UMCCH5_1_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
4646 #define UMCCH5_1_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
4647 #define UMCCH5_1_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
4648 #define UMCCH5_1_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
4649 #define UMCCH5_1_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
4650 //UMCCH5_1_PerfMonCtr2_Lo
4651 #define UMCCH5_1_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
4652 #define UMCCH5_1_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
4653 //UMCCH5_1_PerfMonCtr2_Hi
4654 #define UMCCH5_1_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
4655 #define UMCCH5_1_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
4656 #define UMCCH5_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
4657 #define UMCCH5_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
4658 #define UMCCH5_1_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
4659 #define UMCCH5_1_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
4660 #define UMCCH5_1_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4661 #define UMCCH5_1_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4662 //UMCCH5_1_PerfMonCtl3
4663 #define UMCCH5_1_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
4664 #define UMCCH5_1_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
4665 #define UMCCH5_1_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
4666 #define UMCCH5_1_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
4667 #define UMCCH5_1_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
4668 #define UMCCH5_1_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
4669 #define UMCCH5_1_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
4670 #define UMCCH5_1_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
4671 #define UMCCH5_1_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
4672 #define UMCCH5_1_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
4673 #define UMCCH5_1_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
4674 #define UMCCH5_1_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
4675 #define UMCCH5_1_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
4676 #define UMCCH5_1_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
4677 #define UMCCH5_1_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
4678 #define UMCCH5_1_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
4679 //UMCCH5_1_PerfMonCtr3_Lo
4680 #define UMCCH5_1_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
4681 #define UMCCH5_1_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
4682 //UMCCH5_1_PerfMonCtr3_Hi
4683 #define UMCCH5_1_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
4684 #define UMCCH5_1_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
4685 #define UMCCH5_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
4686 #define UMCCH5_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
4687 #define UMCCH5_1_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
4688 #define UMCCH5_1_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
4689 #define UMCCH5_1_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4690 #define UMCCH5_1_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4691 //UMCCH5_1_PerfMonCtl4
4692 #define UMCCH5_1_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
4693 #define UMCCH5_1_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
4694 #define UMCCH5_1_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
4695 #define UMCCH5_1_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
4696 #define UMCCH5_1_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
4697 #define UMCCH5_1_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
4698 #define UMCCH5_1_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
4699 #define UMCCH5_1_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
4700 #define UMCCH5_1_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
4701 #define UMCCH5_1_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
4702 #define UMCCH5_1_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
4703 #define UMCCH5_1_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
4704 #define UMCCH5_1_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
4705 #define UMCCH5_1_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
4706 #define UMCCH5_1_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
4707 #define UMCCH5_1_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
4708 //UMCCH5_1_PerfMonCtr4_Lo
4709 #define UMCCH5_1_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
4710 #define UMCCH5_1_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
4711 //UMCCH5_1_PerfMonCtr4_Hi
4712 #define UMCCH5_1_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
4713 #define UMCCH5_1_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
4714 #define UMCCH5_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
4715 #define UMCCH5_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
4716 #define UMCCH5_1_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
4717 #define UMCCH5_1_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
4718 #define UMCCH5_1_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4719 #define UMCCH5_1_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4720 //UMCCH5_1_PerfMonCtl5
4721 #define UMCCH5_1_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
4722 #define UMCCH5_1_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
4723 #define UMCCH5_1_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
4724 #define UMCCH5_1_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
4725 #define UMCCH5_1_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
4726 #define UMCCH5_1_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
4727 #define UMCCH5_1_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
4728 #define UMCCH5_1_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
4729 #define UMCCH5_1_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
4730 #define UMCCH5_1_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
4731 #define UMCCH5_1_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
4732 #define UMCCH5_1_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
4733 #define UMCCH5_1_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
4734 #define UMCCH5_1_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
4735 #define UMCCH5_1_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
4736 #define UMCCH5_1_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
4737 //UMCCH5_1_PerfMonCtr5_Lo
4738 #define UMCCH5_1_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
4739 #define UMCCH5_1_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
4740 //UMCCH5_1_PerfMonCtr5_Hi
4741 #define UMCCH5_1_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
4742 #define UMCCH5_1_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
4743 #define UMCCH5_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
4744 #define UMCCH5_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
4745 #define UMCCH5_1_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
4746 #define UMCCH5_1_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
4747 #define UMCCH5_1_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4748 #define UMCCH5_1_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4749 //UMCCH5_1_PerfMonCtl6
4750 #define UMCCH5_1_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
4751 #define UMCCH5_1_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
4752 #define UMCCH5_1_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
4753 #define UMCCH5_1_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
4754 #define UMCCH5_1_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
4755 #define UMCCH5_1_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
4756 #define UMCCH5_1_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
4757 #define UMCCH5_1_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
4758 #define UMCCH5_1_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
4759 #define UMCCH5_1_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
4760 #define UMCCH5_1_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
4761 #define UMCCH5_1_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
4762 #define UMCCH5_1_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
4763 #define UMCCH5_1_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
4764 #define UMCCH5_1_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
4765 #define UMCCH5_1_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
4766 //UMCCH5_1_PerfMonCtr6_Lo
4767 #define UMCCH5_1_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
4768 #define UMCCH5_1_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
4769 //UMCCH5_1_PerfMonCtr6_Hi
4770 #define UMCCH5_1_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
4771 #define UMCCH5_1_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
4772 #define UMCCH5_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
4773 #define UMCCH5_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
4774 #define UMCCH5_1_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
4775 #define UMCCH5_1_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
4776 #define UMCCH5_1_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4777 #define UMCCH5_1_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4778 //UMCCH5_1_PerfMonCtl7
4779 #define UMCCH5_1_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
4780 #define UMCCH5_1_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
4781 #define UMCCH5_1_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
4782 #define UMCCH5_1_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
4783 #define UMCCH5_1_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
4784 #define UMCCH5_1_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
4785 #define UMCCH5_1_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
4786 #define UMCCH5_1_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
4787 #define UMCCH5_1_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
4788 #define UMCCH5_1_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
4789 #define UMCCH5_1_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
4790 #define UMCCH5_1_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
4791 #define UMCCH5_1_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
4792 #define UMCCH5_1_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
4793 #define UMCCH5_1_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
4794 #define UMCCH5_1_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
4795 //UMCCH5_1_PerfMonCtr7_Lo
4796 #define UMCCH5_1_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
4797 #define UMCCH5_1_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
4798 //UMCCH5_1_PerfMonCtr7_Hi
4799 #define UMCCH5_1_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
4800 #define UMCCH5_1_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
4801 #define UMCCH5_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
4802 #define UMCCH5_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
4803 #define UMCCH5_1_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
4804 #define UMCCH5_1_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
4805 #define UMCCH5_1_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4806 #define UMCCH5_1_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4807 //UMCCH5_1_PerfMonCtl8
4808 #define UMCCH5_1_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
4809 #define UMCCH5_1_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
4810 #define UMCCH5_1_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
4811 #define UMCCH5_1_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
4812 #define UMCCH5_1_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
4813 #define UMCCH5_1_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
4814 #define UMCCH5_1_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
4815 #define UMCCH5_1_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
4816 #define UMCCH5_1_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
4817 #define UMCCH5_1_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
4818 #define UMCCH5_1_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
4819 #define UMCCH5_1_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
4820 #define UMCCH5_1_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
4821 #define UMCCH5_1_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
4822 #define UMCCH5_1_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
4823 #define UMCCH5_1_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
4824 //UMCCH5_1_PerfMonCtr8_Lo
4825 #define UMCCH5_1_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
4826 #define UMCCH5_1_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
4827 //UMCCH5_1_PerfMonCtr8_Hi
4828 #define UMCCH5_1_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
4829 #define UMCCH5_1_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
4830 #define UMCCH5_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
4831 #define UMCCH5_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
4832 #define UMCCH5_1_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
4833 #define UMCCH5_1_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
4834 #define UMCCH5_1_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4835 #define UMCCH5_1_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4836 
4837 
4838 // addressBlock: umc_w_phy_umc1_umcch6_umcchdec
4839 //UMCCH6_1_BaseAddrCS0
4840 #define UMCCH6_1_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
4841 #define UMCCH6_1_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
4842 #define UMCCH6_1_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
4843 #define UMCCH6_1_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
4844 //UMCCH6_1_AddrMaskCS01
4845 #define UMCCH6_1_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
4846 #define UMCCH6_1_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
4847 //UMCCH6_1_AddrSelCS01
4848 #define UMCCH6_1_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
4849 #define UMCCH6_1_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
4850 #define UMCCH6_1_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
4851 #define UMCCH6_1_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
4852 #define UMCCH6_1_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
4853 #define UMCCH6_1_AddrSelCS01__RowLo__SHIFT                                                                    0x18
4854 #define UMCCH6_1_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
4855 #define UMCCH6_1_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
4856 #define UMCCH6_1_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
4857 #define UMCCH6_1_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
4858 #define UMCCH6_1_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
4859 #define UMCCH6_1_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
4860 #define UMCCH6_1_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
4861 #define UMCCH6_1_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
4862 //UMCCH6_1_AddrHashBank0
4863 #define UMCCH6_1_AddrHashBank0__XorEnable__SHIFT                                                              0x0
4864 #define UMCCH6_1_AddrHashBank0__ColXor__SHIFT                                                                 0x1
4865 #define UMCCH6_1_AddrHashBank0__RowXor__SHIFT                                                                 0xe
4866 #define UMCCH6_1_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
4867 #define UMCCH6_1_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
4868 #define UMCCH6_1_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
4869 //UMCCH6_1_AddrHashBank1
4870 #define UMCCH6_1_AddrHashBank1__XorEnable__SHIFT                                                              0x0
4871 #define UMCCH6_1_AddrHashBank1__ColXor__SHIFT                                                                 0x1
4872 #define UMCCH6_1_AddrHashBank1__RowXor__SHIFT                                                                 0xe
4873 #define UMCCH6_1_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
4874 #define UMCCH6_1_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
4875 #define UMCCH6_1_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
4876 //UMCCH6_1_AddrHashBank2
4877 #define UMCCH6_1_AddrHashBank2__XorEnable__SHIFT                                                              0x0
4878 #define UMCCH6_1_AddrHashBank2__ColXor__SHIFT                                                                 0x1
4879 #define UMCCH6_1_AddrHashBank2__RowXor__SHIFT                                                                 0xe
4880 #define UMCCH6_1_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
4881 #define UMCCH6_1_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
4882 #define UMCCH6_1_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
4883 //UMCCH6_1_AddrHashBank3
4884 #define UMCCH6_1_AddrHashBank3__XorEnable__SHIFT                                                              0x0
4885 #define UMCCH6_1_AddrHashBank3__ColXor__SHIFT                                                                 0x1
4886 #define UMCCH6_1_AddrHashBank3__RowXor__SHIFT                                                                 0xe
4887 #define UMCCH6_1_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
4888 #define UMCCH6_1_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
4889 #define UMCCH6_1_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
4890 //UMCCH6_1_AddrHashBank4
4891 #define UMCCH6_1_AddrHashBank4__XorEnable__SHIFT                                                              0x0
4892 #define UMCCH6_1_AddrHashBank4__ColXor__SHIFT                                                                 0x1
4893 #define UMCCH6_1_AddrHashBank4__RowXor__SHIFT                                                                 0xe
4894 #define UMCCH6_1_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
4895 #define UMCCH6_1_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
4896 #define UMCCH6_1_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
4897 //UMCCH6_1_AddrHashBank5
4898 #define UMCCH6_1_AddrHashBank5__XorEnable__SHIFT                                                              0x0
4899 #define UMCCH6_1_AddrHashBank5__ColXor__SHIFT                                                                 0x1
4900 #define UMCCH6_1_AddrHashBank5__RowXor__SHIFT                                                                 0xe
4901 #define UMCCH6_1_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
4902 #define UMCCH6_1_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
4903 #define UMCCH6_1_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
4904 //UMCCH6_1_EccErrCntSel
4905 #define UMCCH6_1_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
4906 #define UMCCH6_1_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
4907 #define UMCCH6_1_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
4908 #define UMCCH6_1_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
4909 #define UMCCH6_1_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
4910 #define UMCCH6_1_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
4911 //UMCCH6_1_EccErrCnt
4912 #define UMCCH6_1_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
4913 #define UMCCH6_1_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
4914 //UMCCH6_1_PerfMonCtlClk
4915 #define UMCCH6_1_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
4916 #define UMCCH6_1_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
4917 #define UMCCH6_1_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
4918 #define UMCCH6_1_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
4919 #define UMCCH6_1_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
4920 #define UMCCH6_1_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
4921 #define UMCCH6_1_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
4922 #define UMCCH6_1_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
4923 #define UMCCH6_1_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
4924 #define UMCCH6_1_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
4925 #define UMCCH6_1_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
4926 #define UMCCH6_1_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
4927 //UMCCH6_1_PerfMonCtrClk_Lo
4928 #define UMCCH6_1_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
4929 #define UMCCH6_1_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
4930 //UMCCH6_1_PerfMonCtrClk_Hi
4931 #define UMCCH6_1_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
4932 #define UMCCH6_1_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
4933 #define UMCCH6_1_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
4934 #define UMCCH6_1_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
4935 //UMCCH6_1_PerfMonCtl1
4936 #define UMCCH6_1_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
4937 #define UMCCH6_1_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
4938 #define UMCCH6_1_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
4939 #define UMCCH6_1_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
4940 #define UMCCH6_1_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
4941 #define UMCCH6_1_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
4942 #define UMCCH6_1_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
4943 #define UMCCH6_1_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
4944 #define UMCCH6_1_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
4945 #define UMCCH6_1_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
4946 #define UMCCH6_1_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
4947 #define UMCCH6_1_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
4948 #define UMCCH6_1_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
4949 #define UMCCH6_1_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
4950 #define UMCCH6_1_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
4951 #define UMCCH6_1_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
4952 //UMCCH6_1_PerfMonCtr1_Lo
4953 #define UMCCH6_1_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
4954 #define UMCCH6_1_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
4955 //UMCCH6_1_PerfMonCtr1_Hi
4956 #define UMCCH6_1_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
4957 #define UMCCH6_1_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
4958 #define UMCCH6_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
4959 #define UMCCH6_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
4960 #define UMCCH6_1_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
4961 #define UMCCH6_1_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
4962 #define UMCCH6_1_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4963 #define UMCCH6_1_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4964 //UMCCH6_1_PerfMonCtl2
4965 #define UMCCH6_1_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
4966 #define UMCCH6_1_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
4967 #define UMCCH6_1_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
4968 #define UMCCH6_1_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
4969 #define UMCCH6_1_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
4970 #define UMCCH6_1_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
4971 #define UMCCH6_1_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
4972 #define UMCCH6_1_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
4973 #define UMCCH6_1_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
4974 #define UMCCH6_1_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
4975 #define UMCCH6_1_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
4976 #define UMCCH6_1_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
4977 #define UMCCH6_1_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
4978 #define UMCCH6_1_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
4979 #define UMCCH6_1_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
4980 #define UMCCH6_1_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
4981 //UMCCH6_1_PerfMonCtr2_Lo
4982 #define UMCCH6_1_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
4983 #define UMCCH6_1_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
4984 //UMCCH6_1_PerfMonCtr2_Hi
4985 #define UMCCH6_1_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
4986 #define UMCCH6_1_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
4987 #define UMCCH6_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
4988 #define UMCCH6_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
4989 #define UMCCH6_1_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
4990 #define UMCCH6_1_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
4991 #define UMCCH6_1_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
4992 #define UMCCH6_1_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
4993 //UMCCH6_1_PerfMonCtl3
4994 #define UMCCH6_1_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
4995 #define UMCCH6_1_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
4996 #define UMCCH6_1_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
4997 #define UMCCH6_1_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
4998 #define UMCCH6_1_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
4999 #define UMCCH6_1_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
5000 #define UMCCH6_1_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
5001 #define UMCCH6_1_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
5002 #define UMCCH6_1_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
5003 #define UMCCH6_1_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
5004 #define UMCCH6_1_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
5005 #define UMCCH6_1_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
5006 #define UMCCH6_1_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
5007 #define UMCCH6_1_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
5008 #define UMCCH6_1_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
5009 #define UMCCH6_1_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
5010 //UMCCH6_1_PerfMonCtr3_Lo
5011 #define UMCCH6_1_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
5012 #define UMCCH6_1_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
5013 //UMCCH6_1_PerfMonCtr3_Hi
5014 #define UMCCH6_1_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
5015 #define UMCCH6_1_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
5016 #define UMCCH6_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
5017 #define UMCCH6_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
5018 #define UMCCH6_1_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
5019 #define UMCCH6_1_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
5020 #define UMCCH6_1_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5021 #define UMCCH6_1_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5022 //UMCCH6_1_PerfMonCtl4
5023 #define UMCCH6_1_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
5024 #define UMCCH6_1_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
5025 #define UMCCH6_1_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
5026 #define UMCCH6_1_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
5027 #define UMCCH6_1_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
5028 #define UMCCH6_1_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
5029 #define UMCCH6_1_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
5030 #define UMCCH6_1_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
5031 #define UMCCH6_1_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
5032 #define UMCCH6_1_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
5033 #define UMCCH6_1_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
5034 #define UMCCH6_1_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
5035 #define UMCCH6_1_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
5036 #define UMCCH6_1_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
5037 #define UMCCH6_1_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
5038 #define UMCCH6_1_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
5039 //UMCCH6_1_PerfMonCtr4_Lo
5040 #define UMCCH6_1_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
5041 #define UMCCH6_1_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
5042 //UMCCH6_1_PerfMonCtr4_Hi
5043 #define UMCCH6_1_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
5044 #define UMCCH6_1_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
5045 #define UMCCH6_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
5046 #define UMCCH6_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
5047 #define UMCCH6_1_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
5048 #define UMCCH6_1_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
5049 #define UMCCH6_1_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5050 #define UMCCH6_1_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5051 //UMCCH6_1_PerfMonCtl5
5052 #define UMCCH6_1_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
5053 #define UMCCH6_1_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
5054 #define UMCCH6_1_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
5055 #define UMCCH6_1_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
5056 #define UMCCH6_1_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
5057 #define UMCCH6_1_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
5058 #define UMCCH6_1_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
5059 #define UMCCH6_1_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
5060 #define UMCCH6_1_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
5061 #define UMCCH6_1_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
5062 #define UMCCH6_1_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
5063 #define UMCCH6_1_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
5064 #define UMCCH6_1_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
5065 #define UMCCH6_1_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
5066 #define UMCCH6_1_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
5067 #define UMCCH6_1_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
5068 //UMCCH6_1_PerfMonCtr5_Lo
5069 #define UMCCH6_1_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
5070 #define UMCCH6_1_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
5071 //UMCCH6_1_PerfMonCtr5_Hi
5072 #define UMCCH6_1_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
5073 #define UMCCH6_1_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
5074 #define UMCCH6_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
5075 #define UMCCH6_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
5076 #define UMCCH6_1_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
5077 #define UMCCH6_1_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
5078 #define UMCCH6_1_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5079 #define UMCCH6_1_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5080 //UMCCH6_1_PerfMonCtl6
5081 #define UMCCH6_1_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
5082 #define UMCCH6_1_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
5083 #define UMCCH6_1_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
5084 #define UMCCH6_1_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
5085 #define UMCCH6_1_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
5086 #define UMCCH6_1_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
5087 #define UMCCH6_1_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
5088 #define UMCCH6_1_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
5089 #define UMCCH6_1_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
5090 #define UMCCH6_1_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
5091 #define UMCCH6_1_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
5092 #define UMCCH6_1_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
5093 #define UMCCH6_1_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
5094 #define UMCCH6_1_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
5095 #define UMCCH6_1_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
5096 #define UMCCH6_1_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
5097 //UMCCH6_1_PerfMonCtr6_Lo
5098 #define UMCCH6_1_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
5099 #define UMCCH6_1_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
5100 //UMCCH6_1_PerfMonCtr6_Hi
5101 #define UMCCH6_1_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
5102 #define UMCCH6_1_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
5103 #define UMCCH6_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
5104 #define UMCCH6_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
5105 #define UMCCH6_1_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
5106 #define UMCCH6_1_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
5107 #define UMCCH6_1_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5108 #define UMCCH6_1_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5109 //UMCCH6_1_PerfMonCtl7
5110 #define UMCCH6_1_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
5111 #define UMCCH6_1_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
5112 #define UMCCH6_1_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
5113 #define UMCCH6_1_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
5114 #define UMCCH6_1_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
5115 #define UMCCH6_1_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
5116 #define UMCCH6_1_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
5117 #define UMCCH6_1_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
5118 #define UMCCH6_1_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
5119 #define UMCCH6_1_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
5120 #define UMCCH6_1_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
5121 #define UMCCH6_1_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
5122 #define UMCCH6_1_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
5123 #define UMCCH6_1_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
5124 #define UMCCH6_1_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
5125 #define UMCCH6_1_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
5126 //UMCCH6_1_PerfMonCtr7_Lo
5127 #define UMCCH6_1_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
5128 #define UMCCH6_1_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
5129 //UMCCH6_1_PerfMonCtr7_Hi
5130 #define UMCCH6_1_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
5131 #define UMCCH6_1_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
5132 #define UMCCH6_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
5133 #define UMCCH6_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
5134 #define UMCCH6_1_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
5135 #define UMCCH6_1_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
5136 #define UMCCH6_1_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5137 #define UMCCH6_1_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5138 //UMCCH6_1_PerfMonCtl8
5139 #define UMCCH6_1_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
5140 #define UMCCH6_1_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
5141 #define UMCCH6_1_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
5142 #define UMCCH6_1_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
5143 #define UMCCH6_1_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
5144 #define UMCCH6_1_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
5145 #define UMCCH6_1_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
5146 #define UMCCH6_1_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
5147 #define UMCCH6_1_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
5148 #define UMCCH6_1_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
5149 #define UMCCH6_1_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
5150 #define UMCCH6_1_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
5151 #define UMCCH6_1_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
5152 #define UMCCH6_1_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
5153 #define UMCCH6_1_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
5154 #define UMCCH6_1_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
5155 //UMCCH6_1_PerfMonCtr8_Lo
5156 #define UMCCH6_1_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
5157 #define UMCCH6_1_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
5158 //UMCCH6_1_PerfMonCtr8_Hi
5159 #define UMCCH6_1_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
5160 #define UMCCH6_1_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
5161 #define UMCCH6_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
5162 #define UMCCH6_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
5163 #define UMCCH6_1_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
5164 #define UMCCH6_1_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
5165 #define UMCCH6_1_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5166 #define UMCCH6_1_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5167 
5168 
5169 // addressBlock: umc_w_phy_umc1_umcch7_umcchdec
5170 //UMCCH7_1_BaseAddrCS0
5171 #define UMCCH7_1_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
5172 #define UMCCH7_1_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
5173 #define UMCCH7_1_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
5174 #define UMCCH7_1_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
5175 //UMCCH7_1_AddrMaskCS01
5176 #define UMCCH7_1_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
5177 #define UMCCH7_1_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
5178 //UMCCH7_1_AddrSelCS01
5179 #define UMCCH7_1_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
5180 #define UMCCH7_1_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
5181 #define UMCCH7_1_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
5182 #define UMCCH7_1_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
5183 #define UMCCH7_1_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
5184 #define UMCCH7_1_AddrSelCS01__RowLo__SHIFT                                                                    0x18
5185 #define UMCCH7_1_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
5186 #define UMCCH7_1_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
5187 #define UMCCH7_1_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
5188 #define UMCCH7_1_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
5189 #define UMCCH7_1_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
5190 #define UMCCH7_1_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
5191 #define UMCCH7_1_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
5192 #define UMCCH7_1_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
5193 //UMCCH7_1_AddrHashBank0
5194 #define UMCCH7_1_AddrHashBank0__XorEnable__SHIFT                                                              0x0
5195 #define UMCCH7_1_AddrHashBank0__ColXor__SHIFT                                                                 0x1
5196 #define UMCCH7_1_AddrHashBank0__RowXor__SHIFT                                                                 0xe
5197 #define UMCCH7_1_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
5198 #define UMCCH7_1_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
5199 #define UMCCH7_1_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
5200 //UMCCH7_1_AddrHashBank1
5201 #define UMCCH7_1_AddrHashBank1__XorEnable__SHIFT                                                              0x0
5202 #define UMCCH7_1_AddrHashBank1__ColXor__SHIFT                                                                 0x1
5203 #define UMCCH7_1_AddrHashBank1__RowXor__SHIFT                                                                 0xe
5204 #define UMCCH7_1_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
5205 #define UMCCH7_1_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
5206 #define UMCCH7_1_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
5207 //UMCCH7_1_AddrHashBank2
5208 #define UMCCH7_1_AddrHashBank2__XorEnable__SHIFT                                                              0x0
5209 #define UMCCH7_1_AddrHashBank2__ColXor__SHIFT                                                                 0x1
5210 #define UMCCH7_1_AddrHashBank2__RowXor__SHIFT                                                                 0xe
5211 #define UMCCH7_1_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
5212 #define UMCCH7_1_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
5213 #define UMCCH7_1_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
5214 //UMCCH7_1_AddrHashBank3
5215 #define UMCCH7_1_AddrHashBank3__XorEnable__SHIFT                                                              0x0
5216 #define UMCCH7_1_AddrHashBank3__ColXor__SHIFT                                                                 0x1
5217 #define UMCCH7_1_AddrHashBank3__RowXor__SHIFT                                                                 0xe
5218 #define UMCCH7_1_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
5219 #define UMCCH7_1_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
5220 #define UMCCH7_1_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
5221 //UMCCH7_1_AddrHashBank4
5222 #define UMCCH7_1_AddrHashBank4__XorEnable__SHIFT                                                              0x0
5223 #define UMCCH7_1_AddrHashBank4__ColXor__SHIFT                                                                 0x1
5224 #define UMCCH7_1_AddrHashBank4__RowXor__SHIFT                                                                 0xe
5225 #define UMCCH7_1_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
5226 #define UMCCH7_1_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
5227 #define UMCCH7_1_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
5228 //UMCCH7_1_AddrHashBank5
5229 #define UMCCH7_1_AddrHashBank5__XorEnable__SHIFT                                                              0x0
5230 #define UMCCH7_1_AddrHashBank5__ColXor__SHIFT                                                                 0x1
5231 #define UMCCH7_1_AddrHashBank5__RowXor__SHIFT                                                                 0xe
5232 #define UMCCH7_1_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
5233 #define UMCCH7_1_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
5234 #define UMCCH7_1_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
5235 //UMCCH7_1_EccErrCntSel
5236 #define UMCCH7_1_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
5237 #define UMCCH7_1_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
5238 #define UMCCH7_1_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
5239 #define UMCCH7_1_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
5240 #define UMCCH7_1_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
5241 #define UMCCH7_1_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
5242 //UMCCH7_1_EccErrCnt
5243 #define UMCCH7_1_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
5244 #define UMCCH7_1_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
5245 //UMCCH7_1_PerfMonCtlClk
5246 #define UMCCH7_1_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
5247 #define UMCCH7_1_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
5248 #define UMCCH7_1_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
5249 #define UMCCH7_1_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
5250 #define UMCCH7_1_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
5251 #define UMCCH7_1_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
5252 #define UMCCH7_1_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
5253 #define UMCCH7_1_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
5254 #define UMCCH7_1_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
5255 #define UMCCH7_1_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
5256 #define UMCCH7_1_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
5257 #define UMCCH7_1_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
5258 //UMCCH7_1_PerfMonCtrClk_Lo
5259 #define UMCCH7_1_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
5260 #define UMCCH7_1_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
5261 //UMCCH7_1_PerfMonCtrClk_Hi
5262 #define UMCCH7_1_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
5263 #define UMCCH7_1_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
5264 #define UMCCH7_1_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
5265 #define UMCCH7_1_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
5266 //UMCCH7_1_PerfMonCtl1
5267 #define UMCCH7_1_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
5268 #define UMCCH7_1_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
5269 #define UMCCH7_1_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
5270 #define UMCCH7_1_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
5271 #define UMCCH7_1_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
5272 #define UMCCH7_1_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
5273 #define UMCCH7_1_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
5274 #define UMCCH7_1_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
5275 #define UMCCH7_1_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
5276 #define UMCCH7_1_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
5277 #define UMCCH7_1_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
5278 #define UMCCH7_1_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
5279 #define UMCCH7_1_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
5280 #define UMCCH7_1_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
5281 #define UMCCH7_1_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
5282 #define UMCCH7_1_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
5283 //UMCCH7_1_PerfMonCtr1_Lo
5284 #define UMCCH7_1_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
5285 #define UMCCH7_1_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
5286 //UMCCH7_1_PerfMonCtr1_Hi
5287 #define UMCCH7_1_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
5288 #define UMCCH7_1_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
5289 #define UMCCH7_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
5290 #define UMCCH7_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
5291 #define UMCCH7_1_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
5292 #define UMCCH7_1_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
5293 #define UMCCH7_1_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5294 #define UMCCH7_1_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5295 //UMCCH7_1_PerfMonCtl2
5296 #define UMCCH7_1_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
5297 #define UMCCH7_1_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
5298 #define UMCCH7_1_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
5299 #define UMCCH7_1_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
5300 #define UMCCH7_1_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
5301 #define UMCCH7_1_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
5302 #define UMCCH7_1_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
5303 #define UMCCH7_1_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
5304 #define UMCCH7_1_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
5305 #define UMCCH7_1_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
5306 #define UMCCH7_1_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
5307 #define UMCCH7_1_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
5308 #define UMCCH7_1_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
5309 #define UMCCH7_1_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
5310 #define UMCCH7_1_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
5311 #define UMCCH7_1_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
5312 //UMCCH7_1_PerfMonCtr2_Lo
5313 #define UMCCH7_1_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
5314 #define UMCCH7_1_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
5315 //UMCCH7_1_PerfMonCtr2_Hi
5316 #define UMCCH7_1_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
5317 #define UMCCH7_1_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
5318 #define UMCCH7_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
5319 #define UMCCH7_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
5320 #define UMCCH7_1_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
5321 #define UMCCH7_1_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
5322 #define UMCCH7_1_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5323 #define UMCCH7_1_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5324 //UMCCH7_1_PerfMonCtl3
5325 #define UMCCH7_1_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
5326 #define UMCCH7_1_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
5327 #define UMCCH7_1_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
5328 #define UMCCH7_1_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
5329 #define UMCCH7_1_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
5330 #define UMCCH7_1_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
5331 #define UMCCH7_1_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
5332 #define UMCCH7_1_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
5333 #define UMCCH7_1_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
5334 #define UMCCH7_1_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
5335 #define UMCCH7_1_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
5336 #define UMCCH7_1_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
5337 #define UMCCH7_1_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
5338 #define UMCCH7_1_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
5339 #define UMCCH7_1_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
5340 #define UMCCH7_1_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
5341 //UMCCH7_1_PerfMonCtr3_Lo
5342 #define UMCCH7_1_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
5343 #define UMCCH7_1_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
5344 //UMCCH7_1_PerfMonCtr3_Hi
5345 #define UMCCH7_1_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
5346 #define UMCCH7_1_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
5347 #define UMCCH7_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
5348 #define UMCCH7_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
5349 #define UMCCH7_1_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
5350 #define UMCCH7_1_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
5351 #define UMCCH7_1_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5352 #define UMCCH7_1_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5353 //UMCCH7_1_PerfMonCtl4
5354 #define UMCCH7_1_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
5355 #define UMCCH7_1_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
5356 #define UMCCH7_1_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
5357 #define UMCCH7_1_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
5358 #define UMCCH7_1_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
5359 #define UMCCH7_1_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
5360 #define UMCCH7_1_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
5361 #define UMCCH7_1_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
5362 #define UMCCH7_1_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
5363 #define UMCCH7_1_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
5364 #define UMCCH7_1_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
5365 #define UMCCH7_1_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
5366 #define UMCCH7_1_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
5367 #define UMCCH7_1_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
5368 #define UMCCH7_1_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
5369 #define UMCCH7_1_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
5370 //UMCCH7_1_PerfMonCtr4_Lo
5371 #define UMCCH7_1_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
5372 #define UMCCH7_1_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
5373 //UMCCH7_1_PerfMonCtr4_Hi
5374 #define UMCCH7_1_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
5375 #define UMCCH7_1_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
5376 #define UMCCH7_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
5377 #define UMCCH7_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
5378 #define UMCCH7_1_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
5379 #define UMCCH7_1_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
5380 #define UMCCH7_1_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5381 #define UMCCH7_1_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5382 //UMCCH7_1_PerfMonCtl5
5383 #define UMCCH7_1_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
5384 #define UMCCH7_1_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
5385 #define UMCCH7_1_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
5386 #define UMCCH7_1_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
5387 #define UMCCH7_1_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
5388 #define UMCCH7_1_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
5389 #define UMCCH7_1_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
5390 #define UMCCH7_1_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
5391 #define UMCCH7_1_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
5392 #define UMCCH7_1_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
5393 #define UMCCH7_1_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
5394 #define UMCCH7_1_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
5395 #define UMCCH7_1_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
5396 #define UMCCH7_1_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
5397 #define UMCCH7_1_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
5398 #define UMCCH7_1_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
5399 //UMCCH7_1_PerfMonCtr5_Lo
5400 #define UMCCH7_1_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
5401 #define UMCCH7_1_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
5402 //UMCCH7_1_PerfMonCtr5_Hi
5403 #define UMCCH7_1_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
5404 #define UMCCH7_1_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
5405 #define UMCCH7_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
5406 #define UMCCH7_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
5407 #define UMCCH7_1_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
5408 #define UMCCH7_1_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
5409 #define UMCCH7_1_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5410 #define UMCCH7_1_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5411 //UMCCH7_1_PerfMonCtl6
5412 #define UMCCH7_1_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
5413 #define UMCCH7_1_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
5414 #define UMCCH7_1_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
5415 #define UMCCH7_1_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
5416 #define UMCCH7_1_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
5417 #define UMCCH7_1_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
5418 #define UMCCH7_1_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
5419 #define UMCCH7_1_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
5420 #define UMCCH7_1_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
5421 #define UMCCH7_1_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
5422 #define UMCCH7_1_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
5423 #define UMCCH7_1_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
5424 #define UMCCH7_1_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
5425 #define UMCCH7_1_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
5426 #define UMCCH7_1_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
5427 #define UMCCH7_1_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
5428 //UMCCH7_1_PerfMonCtr6_Lo
5429 #define UMCCH7_1_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
5430 #define UMCCH7_1_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
5431 //UMCCH7_1_PerfMonCtr6_Hi
5432 #define UMCCH7_1_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
5433 #define UMCCH7_1_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
5434 #define UMCCH7_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
5435 #define UMCCH7_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
5436 #define UMCCH7_1_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
5437 #define UMCCH7_1_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
5438 #define UMCCH7_1_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5439 #define UMCCH7_1_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5440 //UMCCH7_1_PerfMonCtl7
5441 #define UMCCH7_1_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
5442 #define UMCCH7_1_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
5443 #define UMCCH7_1_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
5444 #define UMCCH7_1_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
5445 #define UMCCH7_1_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
5446 #define UMCCH7_1_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
5447 #define UMCCH7_1_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
5448 #define UMCCH7_1_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
5449 #define UMCCH7_1_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
5450 #define UMCCH7_1_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
5451 #define UMCCH7_1_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
5452 #define UMCCH7_1_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
5453 #define UMCCH7_1_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
5454 #define UMCCH7_1_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
5455 #define UMCCH7_1_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
5456 #define UMCCH7_1_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
5457 //UMCCH7_1_PerfMonCtr7_Lo
5458 #define UMCCH7_1_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
5459 #define UMCCH7_1_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
5460 //UMCCH7_1_PerfMonCtr7_Hi
5461 #define UMCCH7_1_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
5462 #define UMCCH7_1_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
5463 #define UMCCH7_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
5464 #define UMCCH7_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
5465 #define UMCCH7_1_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
5466 #define UMCCH7_1_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
5467 #define UMCCH7_1_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5468 #define UMCCH7_1_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5469 //UMCCH7_1_PerfMonCtl8
5470 #define UMCCH7_1_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
5471 #define UMCCH7_1_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
5472 #define UMCCH7_1_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
5473 #define UMCCH7_1_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
5474 #define UMCCH7_1_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
5475 #define UMCCH7_1_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
5476 #define UMCCH7_1_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
5477 #define UMCCH7_1_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
5478 #define UMCCH7_1_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
5479 #define UMCCH7_1_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
5480 #define UMCCH7_1_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
5481 #define UMCCH7_1_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
5482 #define UMCCH7_1_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
5483 #define UMCCH7_1_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
5484 #define UMCCH7_1_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
5485 #define UMCCH7_1_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
5486 //UMCCH7_1_PerfMonCtr8_Lo
5487 #define UMCCH7_1_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
5488 #define UMCCH7_1_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
5489 //UMCCH7_1_PerfMonCtr8_Hi
5490 #define UMCCH7_1_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
5491 #define UMCCH7_1_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
5492 #define UMCCH7_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
5493 #define UMCCH7_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
5494 #define UMCCH7_1_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
5495 #define UMCCH7_1_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
5496 #define UMCCH7_1_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5497 #define UMCCH7_1_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5498 
5499 
5500 // addressBlock: umc_w_phy_umc2_umcch0_umcchdec
5501 //UMCCH0_2_BaseAddrCS0
5502 #define UMCCH0_2_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
5503 #define UMCCH0_2_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
5504 #define UMCCH0_2_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
5505 #define UMCCH0_2_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
5506 //UMCCH0_2_AddrMaskCS01
5507 #define UMCCH0_2_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
5508 #define UMCCH0_2_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
5509 //UMCCH0_2_AddrSelCS01
5510 #define UMCCH0_2_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
5511 #define UMCCH0_2_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
5512 #define UMCCH0_2_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
5513 #define UMCCH0_2_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
5514 #define UMCCH0_2_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
5515 #define UMCCH0_2_AddrSelCS01__RowLo__SHIFT                                                                    0x18
5516 #define UMCCH0_2_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
5517 #define UMCCH0_2_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
5518 #define UMCCH0_2_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
5519 #define UMCCH0_2_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
5520 #define UMCCH0_2_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
5521 #define UMCCH0_2_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
5522 #define UMCCH0_2_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
5523 #define UMCCH0_2_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
5524 //UMCCH0_2_AddrHashBank0
5525 #define UMCCH0_2_AddrHashBank0__XorEnable__SHIFT                                                              0x0
5526 #define UMCCH0_2_AddrHashBank0__ColXor__SHIFT                                                                 0x1
5527 #define UMCCH0_2_AddrHashBank0__RowXor__SHIFT                                                                 0xe
5528 #define UMCCH0_2_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
5529 #define UMCCH0_2_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
5530 #define UMCCH0_2_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
5531 //UMCCH0_2_AddrHashBank1
5532 #define UMCCH0_2_AddrHashBank1__XorEnable__SHIFT                                                              0x0
5533 #define UMCCH0_2_AddrHashBank1__ColXor__SHIFT                                                                 0x1
5534 #define UMCCH0_2_AddrHashBank1__RowXor__SHIFT                                                                 0xe
5535 #define UMCCH0_2_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
5536 #define UMCCH0_2_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
5537 #define UMCCH0_2_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
5538 //UMCCH0_2_AddrHashBank2
5539 #define UMCCH0_2_AddrHashBank2__XorEnable__SHIFT                                                              0x0
5540 #define UMCCH0_2_AddrHashBank2__ColXor__SHIFT                                                                 0x1
5541 #define UMCCH0_2_AddrHashBank2__RowXor__SHIFT                                                                 0xe
5542 #define UMCCH0_2_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
5543 #define UMCCH0_2_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
5544 #define UMCCH0_2_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
5545 //UMCCH0_2_AddrHashBank3
5546 #define UMCCH0_2_AddrHashBank3__XorEnable__SHIFT                                                              0x0
5547 #define UMCCH0_2_AddrHashBank3__ColXor__SHIFT                                                                 0x1
5548 #define UMCCH0_2_AddrHashBank3__RowXor__SHIFT                                                                 0xe
5549 #define UMCCH0_2_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
5550 #define UMCCH0_2_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
5551 #define UMCCH0_2_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
5552 //UMCCH0_2_AddrHashBank4
5553 #define UMCCH0_2_AddrHashBank4__XorEnable__SHIFT                                                              0x0
5554 #define UMCCH0_2_AddrHashBank4__ColXor__SHIFT                                                                 0x1
5555 #define UMCCH0_2_AddrHashBank4__RowXor__SHIFT                                                                 0xe
5556 #define UMCCH0_2_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
5557 #define UMCCH0_2_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
5558 #define UMCCH0_2_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
5559 //UMCCH0_2_AddrHashBank5
5560 #define UMCCH0_2_AddrHashBank5__XorEnable__SHIFT                                                              0x0
5561 #define UMCCH0_2_AddrHashBank5__ColXor__SHIFT                                                                 0x1
5562 #define UMCCH0_2_AddrHashBank5__RowXor__SHIFT                                                                 0xe
5563 #define UMCCH0_2_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
5564 #define UMCCH0_2_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
5565 #define UMCCH0_2_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
5566 //UMCCH0_2_EccErrCntSel
5567 #define UMCCH0_2_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
5568 #define UMCCH0_2_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
5569 #define UMCCH0_2_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
5570 #define UMCCH0_2_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
5571 #define UMCCH0_2_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
5572 #define UMCCH0_2_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
5573 //UMCCH0_2_EccErrCnt
5574 #define UMCCH0_2_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
5575 #define UMCCH0_2_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
5576 //UMCCH0_2_PerfMonCtlClk
5577 #define UMCCH0_2_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
5578 #define UMCCH0_2_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
5579 #define UMCCH0_2_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
5580 #define UMCCH0_2_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
5581 #define UMCCH0_2_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
5582 #define UMCCH0_2_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
5583 #define UMCCH0_2_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
5584 #define UMCCH0_2_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
5585 #define UMCCH0_2_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
5586 #define UMCCH0_2_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
5587 #define UMCCH0_2_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
5588 #define UMCCH0_2_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
5589 //UMCCH0_2_PerfMonCtrClk_Lo
5590 #define UMCCH0_2_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
5591 #define UMCCH0_2_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
5592 //UMCCH0_2_PerfMonCtrClk_Hi
5593 #define UMCCH0_2_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
5594 #define UMCCH0_2_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
5595 #define UMCCH0_2_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
5596 #define UMCCH0_2_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
5597 //UMCCH0_2_PerfMonCtl1
5598 #define UMCCH0_2_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
5599 #define UMCCH0_2_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
5600 #define UMCCH0_2_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
5601 #define UMCCH0_2_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
5602 #define UMCCH0_2_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
5603 #define UMCCH0_2_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
5604 #define UMCCH0_2_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
5605 #define UMCCH0_2_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
5606 #define UMCCH0_2_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
5607 #define UMCCH0_2_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
5608 #define UMCCH0_2_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
5609 #define UMCCH0_2_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
5610 #define UMCCH0_2_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
5611 #define UMCCH0_2_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
5612 #define UMCCH0_2_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
5613 #define UMCCH0_2_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
5614 //UMCCH0_2_PerfMonCtr1_Lo
5615 #define UMCCH0_2_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
5616 #define UMCCH0_2_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
5617 //UMCCH0_2_PerfMonCtr1_Hi
5618 #define UMCCH0_2_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
5619 #define UMCCH0_2_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
5620 #define UMCCH0_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
5621 #define UMCCH0_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
5622 #define UMCCH0_2_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
5623 #define UMCCH0_2_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
5624 #define UMCCH0_2_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5625 #define UMCCH0_2_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5626 //UMCCH0_2_PerfMonCtl2
5627 #define UMCCH0_2_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
5628 #define UMCCH0_2_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
5629 #define UMCCH0_2_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
5630 #define UMCCH0_2_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
5631 #define UMCCH0_2_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
5632 #define UMCCH0_2_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
5633 #define UMCCH0_2_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
5634 #define UMCCH0_2_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
5635 #define UMCCH0_2_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
5636 #define UMCCH0_2_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
5637 #define UMCCH0_2_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
5638 #define UMCCH0_2_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
5639 #define UMCCH0_2_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
5640 #define UMCCH0_2_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
5641 #define UMCCH0_2_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
5642 #define UMCCH0_2_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
5643 //UMCCH0_2_PerfMonCtr2_Lo
5644 #define UMCCH0_2_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
5645 #define UMCCH0_2_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
5646 //UMCCH0_2_PerfMonCtr2_Hi
5647 #define UMCCH0_2_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
5648 #define UMCCH0_2_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
5649 #define UMCCH0_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
5650 #define UMCCH0_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
5651 #define UMCCH0_2_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
5652 #define UMCCH0_2_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
5653 #define UMCCH0_2_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5654 #define UMCCH0_2_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5655 //UMCCH0_2_PerfMonCtl3
5656 #define UMCCH0_2_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
5657 #define UMCCH0_2_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
5658 #define UMCCH0_2_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
5659 #define UMCCH0_2_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
5660 #define UMCCH0_2_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
5661 #define UMCCH0_2_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
5662 #define UMCCH0_2_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
5663 #define UMCCH0_2_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
5664 #define UMCCH0_2_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
5665 #define UMCCH0_2_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
5666 #define UMCCH0_2_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
5667 #define UMCCH0_2_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
5668 #define UMCCH0_2_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
5669 #define UMCCH0_2_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
5670 #define UMCCH0_2_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
5671 #define UMCCH0_2_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
5672 //UMCCH0_2_PerfMonCtr3_Lo
5673 #define UMCCH0_2_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
5674 #define UMCCH0_2_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
5675 //UMCCH0_2_PerfMonCtr3_Hi
5676 #define UMCCH0_2_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
5677 #define UMCCH0_2_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
5678 #define UMCCH0_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
5679 #define UMCCH0_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
5680 #define UMCCH0_2_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
5681 #define UMCCH0_2_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
5682 #define UMCCH0_2_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5683 #define UMCCH0_2_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5684 //UMCCH0_2_PerfMonCtl4
5685 #define UMCCH0_2_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
5686 #define UMCCH0_2_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
5687 #define UMCCH0_2_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
5688 #define UMCCH0_2_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
5689 #define UMCCH0_2_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
5690 #define UMCCH0_2_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
5691 #define UMCCH0_2_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
5692 #define UMCCH0_2_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
5693 #define UMCCH0_2_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
5694 #define UMCCH0_2_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
5695 #define UMCCH0_2_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
5696 #define UMCCH0_2_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
5697 #define UMCCH0_2_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
5698 #define UMCCH0_2_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
5699 #define UMCCH0_2_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
5700 #define UMCCH0_2_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
5701 //UMCCH0_2_PerfMonCtr4_Lo
5702 #define UMCCH0_2_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
5703 #define UMCCH0_2_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
5704 //UMCCH0_2_PerfMonCtr4_Hi
5705 #define UMCCH0_2_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
5706 #define UMCCH0_2_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
5707 #define UMCCH0_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
5708 #define UMCCH0_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
5709 #define UMCCH0_2_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
5710 #define UMCCH0_2_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
5711 #define UMCCH0_2_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5712 #define UMCCH0_2_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5713 //UMCCH0_2_PerfMonCtl5
5714 #define UMCCH0_2_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
5715 #define UMCCH0_2_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
5716 #define UMCCH0_2_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
5717 #define UMCCH0_2_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
5718 #define UMCCH0_2_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
5719 #define UMCCH0_2_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
5720 #define UMCCH0_2_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
5721 #define UMCCH0_2_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
5722 #define UMCCH0_2_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
5723 #define UMCCH0_2_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
5724 #define UMCCH0_2_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
5725 #define UMCCH0_2_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
5726 #define UMCCH0_2_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
5727 #define UMCCH0_2_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
5728 #define UMCCH0_2_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
5729 #define UMCCH0_2_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
5730 //UMCCH0_2_PerfMonCtr5_Lo
5731 #define UMCCH0_2_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
5732 #define UMCCH0_2_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
5733 //UMCCH0_2_PerfMonCtr5_Hi
5734 #define UMCCH0_2_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
5735 #define UMCCH0_2_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
5736 #define UMCCH0_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
5737 #define UMCCH0_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
5738 #define UMCCH0_2_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
5739 #define UMCCH0_2_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
5740 #define UMCCH0_2_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5741 #define UMCCH0_2_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5742 //UMCCH0_2_PerfMonCtl6
5743 #define UMCCH0_2_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
5744 #define UMCCH0_2_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
5745 #define UMCCH0_2_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
5746 #define UMCCH0_2_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
5747 #define UMCCH0_2_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
5748 #define UMCCH0_2_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
5749 #define UMCCH0_2_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
5750 #define UMCCH0_2_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
5751 #define UMCCH0_2_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
5752 #define UMCCH0_2_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
5753 #define UMCCH0_2_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
5754 #define UMCCH0_2_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
5755 #define UMCCH0_2_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
5756 #define UMCCH0_2_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
5757 #define UMCCH0_2_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
5758 #define UMCCH0_2_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
5759 //UMCCH0_2_PerfMonCtr6_Lo
5760 #define UMCCH0_2_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
5761 #define UMCCH0_2_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
5762 //UMCCH0_2_PerfMonCtr6_Hi
5763 #define UMCCH0_2_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
5764 #define UMCCH0_2_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
5765 #define UMCCH0_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
5766 #define UMCCH0_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
5767 #define UMCCH0_2_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
5768 #define UMCCH0_2_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
5769 #define UMCCH0_2_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5770 #define UMCCH0_2_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5771 //UMCCH0_2_PerfMonCtl7
5772 #define UMCCH0_2_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
5773 #define UMCCH0_2_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
5774 #define UMCCH0_2_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
5775 #define UMCCH0_2_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
5776 #define UMCCH0_2_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
5777 #define UMCCH0_2_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
5778 #define UMCCH0_2_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
5779 #define UMCCH0_2_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
5780 #define UMCCH0_2_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
5781 #define UMCCH0_2_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
5782 #define UMCCH0_2_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
5783 #define UMCCH0_2_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
5784 #define UMCCH0_2_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
5785 #define UMCCH0_2_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
5786 #define UMCCH0_2_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
5787 #define UMCCH0_2_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
5788 //UMCCH0_2_PerfMonCtr7_Lo
5789 #define UMCCH0_2_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
5790 #define UMCCH0_2_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
5791 //UMCCH0_2_PerfMonCtr7_Hi
5792 #define UMCCH0_2_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
5793 #define UMCCH0_2_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
5794 #define UMCCH0_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
5795 #define UMCCH0_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
5796 #define UMCCH0_2_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
5797 #define UMCCH0_2_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
5798 #define UMCCH0_2_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5799 #define UMCCH0_2_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5800 //UMCCH0_2_PerfMonCtl8
5801 #define UMCCH0_2_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
5802 #define UMCCH0_2_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
5803 #define UMCCH0_2_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
5804 #define UMCCH0_2_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
5805 #define UMCCH0_2_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
5806 #define UMCCH0_2_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
5807 #define UMCCH0_2_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
5808 #define UMCCH0_2_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
5809 #define UMCCH0_2_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
5810 #define UMCCH0_2_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
5811 #define UMCCH0_2_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
5812 #define UMCCH0_2_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
5813 #define UMCCH0_2_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
5814 #define UMCCH0_2_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
5815 #define UMCCH0_2_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
5816 #define UMCCH0_2_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
5817 //UMCCH0_2_PerfMonCtr8_Lo
5818 #define UMCCH0_2_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
5819 #define UMCCH0_2_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
5820 //UMCCH0_2_PerfMonCtr8_Hi
5821 #define UMCCH0_2_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
5822 #define UMCCH0_2_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
5823 #define UMCCH0_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
5824 #define UMCCH0_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
5825 #define UMCCH0_2_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
5826 #define UMCCH0_2_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
5827 #define UMCCH0_2_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5828 #define UMCCH0_2_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5829 
5830 
5831 // addressBlock: umc_w_phy_umc2_umcch1_umcchdec
5832 //UMCCH1_2_BaseAddrCS0
5833 #define UMCCH1_2_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
5834 #define UMCCH1_2_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
5835 #define UMCCH1_2_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
5836 #define UMCCH1_2_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
5837 //UMCCH1_2_AddrMaskCS01
5838 #define UMCCH1_2_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
5839 #define UMCCH1_2_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
5840 //UMCCH1_2_AddrSelCS01
5841 #define UMCCH1_2_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
5842 #define UMCCH1_2_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
5843 #define UMCCH1_2_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
5844 #define UMCCH1_2_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
5845 #define UMCCH1_2_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
5846 #define UMCCH1_2_AddrSelCS01__RowLo__SHIFT                                                                    0x18
5847 #define UMCCH1_2_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
5848 #define UMCCH1_2_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
5849 #define UMCCH1_2_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
5850 #define UMCCH1_2_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
5851 #define UMCCH1_2_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
5852 #define UMCCH1_2_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
5853 #define UMCCH1_2_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
5854 #define UMCCH1_2_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
5855 //UMCCH1_2_AddrHashBank0
5856 #define UMCCH1_2_AddrHashBank0__XorEnable__SHIFT                                                              0x0
5857 #define UMCCH1_2_AddrHashBank0__ColXor__SHIFT                                                                 0x1
5858 #define UMCCH1_2_AddrHashBank0__RowXor__SHIFT                                                                 0xe
5859 #define UMCCH1_2_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
5860 #define UMCCH1_2_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
5861 #define UMCCH1_2_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
5862 //UMCCH1_2_AddrHashBank1
5863 #define UMCCH1_2_AddrHashBank1__XorEnable__SHIFT                                                              0x0
5864 #define UMCCH1_2_AddrHashBank1__ColXor__SHIFT                                                                 0x1
5865 #define UMCCH1_2_AddrHashBank1__RowXor__SHIFT                                                                 0xe
5866 #define UMCCH1_2_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
5867 #define UMCCH1_2_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
5868 #define UMCCH1_2_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
5869 //UMCCH1_2_AddrHashBank2
5870 #define UMCCH1_2_AddrHashBank2__XorEnable__SHIFT                                                              0x0
5871 #define UMCCH1_2_AddrHashBank2__ColXor__SHIFT                                                                 0x1
5872 #define UMCCH1_2_AddrHashBank2__RowXor__SHIFT                                                                 0xe
5873 #define UMCCH1_2_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
5874 #define UMCCH1_2_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
5875 #define UMCCH1_2_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
5876 //UMCCH1_2_AddrHashBank3
5877 #define UMCCH1_2_AddrHashBank3__XorEnable__SHIFT                                                              0x0
5878 #define UMCCH1_2_AddrHashBank3__ColXor__SHIFT                                                                 0x1
5879 #define UMCCH1_2_AddrHashBank3__RowXor__SHIFT                                                                 0xe
5880 #define UMCCH1_2_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
5881 #define UMCCH1_2_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
5882 #define UMCCH1_2_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
5883 //UMCCH1_2_AddrHashBank4
5884 #define UMCCH1_2_AddrHashBank4__XorEnable__SHIFT                                                              0x0
5885 #define UMCCH1_2_AddrHashBank4__ColXor__SHIFT                                                                 0x1
5886 #define UMCCH1_2_AddrHashBank4__RowXor__SHIFT                                                                 0xe
5887 #define UMCCH1_2_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
5888 #define UMCCH1_2_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
5889 #define UMCCH1_2_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
5890 //UMCCH1_2_AddrHashBank5
5891 #define UMCCH1_2_AddrHashBank5__XorEnable__SHIFT                                                              0x0
5892 #define UMCCH1_2_AddrHashBank5__ColXor__SHIFT                                                                 0x1
5893 #define UMCCH1_2_AddrHashBank5__RowXor__SHIFT                                                                 0xe
5894 #define UMCCH1_2_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
5895 #define UMCCH1_2_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
5896 #define UMCCH1_2_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
5897 //UMCCH1_2_EccErrCntSel
5898 #define UMCCH1_2_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
5899 #define UMCCH1_2_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
5900 #define UMCCH1_2_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
5901 #define UMCCH1_2_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
5902 #define UMCCH1_2_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
5903 #define UMCCH1_2_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
5904 //UMCCH1_2_EccErrCnt
5905 #define UMCCH1_2_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
5906 #define UMCCH1_2_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
5907 //UMCCH1_2_PerfMonCtlClk
5908 #define UMCCH1_2_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
5909 #define UMCCH1_2_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
5910 #define UMCCH1_2_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
5911 #define UMCCH1_2_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
5912 #define UMCCH1_2_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
5913 #define UMCCH1_2_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
5914 #define UMCCH1_2_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
5915 #define UMCCH1_2_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
5916 #define UMCCH1_2_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
5917 #define UMCCH1_2_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
5918 #define UMCCH1_2_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
5919 #define UMCCH1_2_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
5920 //UMCCH1_2_PerfMonCtrClk_Lo
5921 #define UMCCH1_2_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
5922 #define UMCCH1_2_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
5923 //UMCCH1_2_PerfMonCtrClk_Hi
5924 #define UMCCH1_2_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
5925 #define UMCCH1_2_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
5926 #define UMCCH1_2_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
5927 #define UMCCH1_2_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
5928 //UMCCH1_2_PerfMonCtl1
5929 #define UMCCH1_2_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
5930 #define UMCCH1_2_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
5931 #define UMCCH1_2_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
5932 #define UMCCH1_2_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
5933 #define UMCCH1_2_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
5934 #define UMCCH1_2_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
5935 #define UMCCH1_2_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
5936 #define UMCCH1_2_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
5937 #define UMCCH1_2_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
5938 #define UMCCH1_2_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
5939 #define UMCCH1_2_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
5940 #define UMCCH1_2_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
5941 #define UMCCH1_2_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
5942 #define UMCCH1_2_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
5943 #define UMCCH1_2_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
5944 #define UMCCH1_2_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
5945 //UMCCH1_2_PerfMonCtr1_Lo
5946 #define UMCCH1_2_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
5947 #define UMCCH1_2_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
5948 //UMCCH1_2_PerfMonCtr1_Hi
5949 #define UMCCH1_2_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
5950 #define UMCCH1_2_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
5951 #define UMCCH1_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
5952 #define UMCCH1_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
5953 #define UMCCH1_2_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
5954 #define UMCCH1_2_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
5955 #define UMCCH1_2_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5956 #define UMCCH1_2_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5957 //UMCCH1_2_PerfMonCtl2
5958 #define UMCCH1_2_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
5959 #define UMCCH1_2_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
5960 #define UMCCH1_2_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
5961 #define UMCCH1_2_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
5962 #define UMCCH1_2_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
5963 #define UMCCH1_2_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
5964 #define UMCCH1_2_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
5965 #define UMCCH1_2_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
5966 #define UMCCH1_2_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
5967 #define UMCCH1_2_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
5968 #define UMCCH1_2_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
5969 #define UMCCH1_2_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
5970 #define UMCCH1_2_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
5971 #define UMCCH1_2_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
5972 #define UMCCH1_2_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
5973 #define UMCCH1_2_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
5974 //UMCCH1_2_PerfMonCtr2_Lo
5975 #define UMCCH1_2_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
5976 #define UMCCH1_2_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
5977 //UMCCH1_2_PerfMonCtr2_Hi
5978 #define UMCCH1_2_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
5979 #define UMCCH1_2_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
5980 #define UMCCH1_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
5981 #define UMCCH1_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
5982 #define UMCCH1_2_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
5983 #define UMCCH1_2_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
5984 #define UMCCH1_2_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
5985 #define UMCCH1_2_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
5986 //UMCCH1_2_PerfMonCtl3
5987 #define UMCCH1_2_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
5988 #define UMCCH1_2_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
5989 #define UMCCH1_2_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
5990 #define UMCCH1_2_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
5991 #define UMCCH1_2_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
5992 #define UMCCH1_2_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
5993 #define UMCCH1_2_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
5994 #define UMCCH1_2_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
5995 #define UMCCH1_2_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
5996 #define UMCCH1_2_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
5997 #define UMCCH1_2_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
5998 #define UMCCH1_2_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
5999 #define UMCCH1_2_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
6000 #define UMCCH1_2_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
6001 #define UMCCH1_2_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
6002 #define UMCCH1_2_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
6003 //UMCCH1_2_PerfMonCtr3_Lo
6004 #define UMCCH1_2_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
6005 #define UMCCH1_2_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
6006 //UMCCH1_2_PerfMonCtr3_Hi
6007 #define UMCCH1_2_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
6008 #define UMCCH1_2_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
6009 #define UMCCH1_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
6010 #define UMCCH1_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
6011 #define UMCCH1_2_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
6012 #define UMCCH1_2_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
6013 #define UMCCH1_2_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6014 #define UMCCH1_2_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6015 //UMCCH1_2_PerfMonCtl4
6016 #define UMCCH1_2_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
6017 #define UMCCH1_2_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
6018 #define UMCCH1_2_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
6019 #define UMCCH1_2_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
6020 #define UMCCH1_2_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
6021 #define UMCCH1_2_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
6022 #define UMCCH1_2_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
6023 #define UMCCH1_2_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
6024 #define UMCCH1_2_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
6025 #define UMCCH1_2_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
6026 #define UMCCH1_2_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
6027 #define UMCCH1_2_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
6028 #define UMCCH1_2_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
6029 #define UMCCH1_2_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
6030 #define UMCCH1_2_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
6031 #define UMCCH1_2_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
6032 //UMCCH1_2_PerfMonCtr4_Lo
6033 #define UMCCH1_2_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
6034 #define UMCCH1_2_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
6035 //UMCCH1_2_PerfMonCtr4_Hi
6036 #define UMCCH1_2_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
6037 #define UMCCH1_2_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
6038 #define UMCCH1_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
6039 #define UMCCH1_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
6040 #define UMCCH1_2_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
6041 #define UMCCH1_2_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
6042 #define UMCCH1_2_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6043 #define UMCCH1_2_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6044 //UMCCH1_2_PerfMonCtl5
6045 #define UMCCH1_2_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
6046 #define UMCCH1_2_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
6047 #define UMCCH1_2_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
6048 #define UMCCH1_2_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
6049 #define UMCCH1_2_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
6050 #define UMCCH1_2_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
6051 #define UMCCH1_2_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
6052 #define UMCCH1_2_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
6053 #define UMCCH1_2_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
6054 #define UMCCH1_2_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
6055 #define UMCCH1_2_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
6056 #define UMCCH1_2_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
6057 #define UMCCH1_2_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
6058 #define UMCCH1_2_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
6059 #define UMCCH1_2_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
6060 #define UMCCH1_2_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
6061 //UMCCH1_2_PerfMonCtr5_Lo
6062 #define UMCCH1_2_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
6063 #define UMCCH1_2_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
6064 //UMCCH1_2_PerfMonCtr5_Hi
6065 #define UMCCH1_2_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
6066 #define UMCCH1_2_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
6067 #define UMCCH1_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
6068 #define UMCCH1_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
6069 #define UMCCH1_2_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
6070 #define UMCCH1_2_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
6071 #define UMCCH1_2_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6072 #define UMCCH1_2_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6073 //UMCCH1_2_PerfMonCtl6
6074 #define UMCCH1_2_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
6075 #define UMCCH1_2_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
6076 #define UMCCH1_2_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
6077 #define UMCCH1_2_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
6078 #define UMCCH1_2_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
6079 #define UMCCH1_2_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
6080 #define UMCCH1_2_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
6081 #define UMCCH1_2_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
6082 #define UMCCH1_2_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
6083 #define UMCCH1_2_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
6084 #define UMCCH1_2_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
6085 #define UMCCH1_2_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
6086 #define UMCCH1_2_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
6087 #define UMCCH1_2_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
6088 #define UMCCH1_2_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
6089 #define UMCCH1_2_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
6090 //UMCCH1_2_PerfMonCtr6_Lo
6091 #define UMCCH1_2_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
6092 #define UMCCH1_2_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
6093 //UMCCH1_2_PerfMonCtr6_Hi
6094 #define UMCCH1_2_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
6095 #define UMCCH1_2_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
6096 #define UMCCH1_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
6097 #define UMCCH1_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
6098 #define UMCCH1_2_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
6099 #define UMCCH1_2_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
6100 #define UMCCH1_2_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6101 #define UMCCH1_2_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6102 //UMCCH1_2_PerfMonCtl7
6103 #define UMCCH1_2_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
6104 #define UMCCH1_2_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
6105 #define UMCCH1_2_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
6106 #define UMCCH1_2_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
6107 #define UMCCH1_2_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
6108 #define UMCCH1_2_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
6109 #define UMCCH1_2_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
6110 #define UMCCH1_2_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
6111 #define UMCCH1_2_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
6112 #define UMCCH1_2_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
6113 #define UMCCH1_2_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
6114 #define UMCCH1_2_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
6115 #define UMCCH1_2_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
6116 #define UMCCH1_2_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
6117 #define UMCCH1_2_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
6118 #define UMCCH1_2_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
6119 //UMCCH1_2_PerfMonCtr7_Lo
6120 #define UMCCH1_2_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
6121 #define UMCCH1_2_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
6122 //UMCCH1_2_PerfMonCtr7_Hi
6123 #define UMCCH1_2_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
6124 #define UMCCH1_2_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
6125 #define UMCCH1_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
6126 #define UMCCH1_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
6127 #define UMCCH1_2_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
6128 #define UMCCH1_2_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
6129 #define UMCCH1_2_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6130 #define UMCCH1_2_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6131 //UMCCH1_2_PerfMonCtl8
6132 #define UMCCH1_2_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
6133 #define UMCCH1_2_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
6134 #define UMCCH1_2_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
6135 #define UMCCH1_2_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
6136 #define UMCCH1_2_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
6137 #define UMCCH1_2_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
6138 #define UMCCH1_2_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
6139 #define UMCCH1_2_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
6140 #define UMCCH1_2_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
6141 #define UMCCH1_2_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
6142 #define UMCCH1_2_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
6143 #define UMCCH1_2_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
6144 #define UMCCH1_2_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
6145 #define UMCCH1_2_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
6146 #define UMCCH1_2_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
6147 #define UMCCH1_2_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
6148 //UMCCH1_2_PerfMonCtr8_Lo
6149 #define UMCCH1_2_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
6150 #define UMCCH1_2_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
6151 //UMCCH1_2_PerfMonCtr8_Hi
6152 #define UMCCH1_2_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
6153 #define UMCCH1_2_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
6154 #define UMCCH1_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
6155 #define UMCCH1_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
6156 #define UMCCH1_2_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
6157 #define UMCCH1_2_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
6158 #define UMCCH1_2_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6159 #define UMCCH1_2_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6160 
6161 
6162 // addressBlock: umc_w_phy_umc2_umcch2_umcchdec
6163 //UMCCH2_2_BaseAddrCS0
6164 #define UMCCH2_2_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
6165 #define UMCCH2_2_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
6166 #define UMCCH2_2_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
6167 #define UMCCH2_2_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
6168 //UMCCH2_2_AddrMaskCS01
6169 #define UMCCH2_2_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
6170 #define UMCCH2_2_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
6171 //UMCCH2_2_AddrSelCS01
6172 #define UMCCH2_2_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
6173 #define UMCCH2_2_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
6174 #define UMCCH2_2_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
6175 #define UMCCH2_2_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
6176 #define UMCCH2_2_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
6177 #define UMCCH2_2_AddrSelCS01__RowLo__SHIFT                                                                    0x18
6178 #define UMCCH2_2_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
6179 #define UMCCH2_2_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
6180 #define UMCCH2_2_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
6181 #define UMCCH2_2_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
6182 #define UMCCH2_2_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
6183 #define UMCCH2_2_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
6184 #define UMCCH2_2_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
6185 #define UMCCH2_2_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
6186 //UMCCH2_2_AddrHashBank0
6187 #define UMCCH2_2_AddrHashBank0__XorEnable__SHIFT                                                              0x0
6188 #define UMCCH2_2_AddrHashBank0__ColXor__SHIFT                                                                 0x1
6189 #define UMCCH2_2_AddrHashBank0__RowXor__SHIFT                                                                 0xe
6190 #define UMCCH2_2_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
6191 #define UMCCH2_2_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
6192 #define UMCCH2_2_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
6193 //UMCCH2_2_AddrHashBank1
6194 #define UMCCH2_2_AddrHashBank1__XorEnable__SHIFT                                                              0x0
6195 #define UMCCH2_2_AddrHashBank1__ColXor__SHIFT                                                                 0x1
6196 #define UMCCH2_2_AddrHashBank1__RowXor__SHIFT                                                                 0xe
6197 #define UMCCH2_2_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
6198 #define UMCCH2_2_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
6199 #define UMCCH2_2_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
6200 //UMCCH2_2_AddrHashBank2
6201 #define UMCCH2_2_AddrHashBank2__XorEnable__SHIFT                                                              0x0
6202 #define UMCCH2_2_AddrHashBank2__ColXor__SHIFT                                                                 0x1
6203 #define UMCCH2_2_AddrHashBank2__RowXor__SHIFT                                                                 0xe
6204 #define UMCCH2_2_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
6205 #define UMCCH2_2_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
6206 #define UMCCH2_2_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
6207 //UMCCH2_2_AddrHashBank3
6208 #define UMCCH2_2_AddrHashBank3__XorEnable__SHIFT                                                              0x0
6209 #define UMCCH2_2_AddrHashBank3__ColXor__SHIFT                                                                 0x1
6210 #define UMCCH2_2_AddrHashBank3__RowXor__SHIFT                                                                 0xe
6211 #define UMCCH2_2_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
6212 #define UMCCH2_2_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
6213 #define UMCCH2_2_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
6214 //UMCCH2_2_AddrHashBank4
6215 #define UMCCH2_2_AddrHashBank4__XorEnable__SHIFT                                                              0x0
6216 #define UMCCH2_2_AddrHashBank4__ColXor__SHIFT                                                                 0x1
6217 #define UMCCH2_2_AddrHashBank4__RowXor__SHIFT                                                                 0xe
6218 #define UMCCH2_2_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
6219 #define UMCCH2_2_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
6220 #define UMCCH2_2_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
6221 //UMCCH2_2_AddrHashBank5
6222 #define UMCCH2_2_AddrHashBank5__XorEnable__SHIFT                                                              0x0
6223 #define UMCCH2_2_AddrHashBank5__ColXor__SHIFT                                                                 0x1
6224 #define UMCCH2_2_AddrHashBank5__RowXor__SHIFT                                                                 0xe
6225 #define UMCCH2_2_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
6226 #define UMCCH2_2_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
6227 #define UMCCH2_2_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
6228 //UMCCH2_2_EccErrCntSel
6229 #define UMCCH2_2_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
6230 #define UMCCH2_2_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
6231 #define UMCCH2_2_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
6232 #define UMCCH2_2_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
6233 #define UMCCH2_2_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
6234 #define UMCCH2_2_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
6235 //UMCCH2_2_EccErrCnt
6236 #define UMCCH2_2_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
6237 #define UMCCH2_2_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
6238 //UMCCH2_2_PerfMonCtlClk
6239 #define UMCCH2_2_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
6240 #define UMCCH2_2_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
6241 #define UMCCH2_2_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
6242 #define UMCCH2_2_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
6243 #define UMCCH2_2_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
6244 #define UMCCH2_2_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
6245 #define UMCCH2_2_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
6246 #define UMCCH2_2_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
6247 #define UMCCH2_2_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
6248 #define UMCCH2_2_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
6249 #define UMCCH2_2_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
6250 #define UMCCH2_2_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
6251 //UMCCH2_2_PerfMonCtrClk_Lo
6252 #define UMCCH2_2_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
6253 #define UMCCH2_2_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
6254 //UMCCH2_2_PerfMonCtrClk_Hi
6255 #define UMCCH2_2_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
6256 #define UMCCH2_2_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
6257 #define UMCCH2_2_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
6258 #define UMCCH2_2_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
6259 //UMCCH2_2_PerfMonCtl1
6260 #define UMCCH2_2_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
6261 #define UMCCH2_2_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
6262 #define UMCCH2_2_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
6263 #define UMCCH2_2_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
6264 #define UMCCH2_2_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
6265 #define UMCCH2_2_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
6266 #define UMCCH2_2_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
6267 #define UMCCH2_2_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
6268 #define UMCCH2_2_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
6269 #define UMCCH2_2_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
6270 #define UMCCH2_2_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
6271 #define UMCCH2_2_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
6272 #define UMCCH2_2_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
6273 #define UMCCH2_2_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
6274 #define UMCCH2_2_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
6275 #define UMCCH2_2_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
6276 //UMCCH2_2_PerfMonCtr1_Lo
6277 #define UMCCH2_2_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
6278 #define UMCCH2_2_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
6279 //UMCCH2_2_PerfMonCtr1_Hi
6280 #define UMCCH2_2_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
6281 #define UMCCH2_2_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
6282 #define UMCCH2_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
6283 #define UMCCH2_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
6284 #define UMCCH2_2_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
6285 #define UMCCH2_2_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
6286 #define UMCCH2_2_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6287 #define UMCCH2_2_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6288 //UMCCH2_2_PerfMonCtl2
6289 #define UMCCH2_2_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
6290 #define UMCCH2_2_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
6291 #define UMCCH2_2_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
6292 #define UMCCH2_2_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
6293 #define UMCCH2_2_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
6294 #define UMCCH2_2_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
6295 #define UMCCH2_2_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
6296 #define UMCCH2_2_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
6297 #define UMCCH2_2_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
6298 #define UMCCH2_2_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
6299 #define UMCCH2_2_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
6300 #define UMCCH2_2_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
6301 #define UMCCH2_2_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
6302 #define UMCCH2_2_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
6303 #define UMCCH2_2_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
6304 #define UMCCH2_2_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
6305 //UMCCH2_2_PerfMonCtr2_Lo
6306 #define UMCCH2_2_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
6307 #define UMCCH2_2_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
6308 //UMCCH2_2_PerfMonCtr2_Hi
6309 #define UMCCH2_2_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
6310 #define UMCCH2_2_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
6311 #define UMCCH2_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
6312 #define UMCCH2_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
6313 #define UMCCH2_2_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
6314 #define UMCCH2_2_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
6315 #define UMCCH2_2_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6316 #define UMCCH2_2_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6317 //UMCCH2_2_PerfMonCtl3
6318 #define UMCCH2_2_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
6319 #define UMCCH2_2_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
6320 #define UMCCH2_2_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
6321 #define UMCCH2_2_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
6322 #define UMCCH2_2_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
6323 #define UMCCH2_2_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
6324 #define UMCCH2_2_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
6325 #define UMCCH2_2_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
6326 #define UMCCH2_2_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
6327 #define UMCCH2_2_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
6328 #define UMCCH2_2_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
6329 #define UMCCH2_2_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
6330 #define UMCCH2_2_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
6331 #define UMCCH2_2_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
6332 #define UMCCH2_2_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
6333 #define UMCCH2_2_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
6334 //UMCCH2_2_PerfMonCtr3_Lo
6335 #define UMCCH2_2_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
6336 #define UMCCH2_2_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
6337 //UMCCH2_2_PerfMonCtr3_Hi
6338 #define UMCCH2_2_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
6339 #define UMCCH2_2_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
6340 #define UMCCH2_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
6341 #define UMCCH2_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
6342 #define UMCCH2_2_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
6343 #define UMCCH2_2_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
6344 #define UMCCH2_2_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6345 #define UMCCH2_2_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6346 //UMCCH2_2_PerfMonCtl4
6347 #define UMCCH2_2_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
6348 #define UMCCH2_2_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
6349 #define UMCCH2_2_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
6350 #define UMCCH2_2_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
6351 #define UMCCH2_2_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
6352 #define UMCCH2_2_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
6353 #define UMCCH2_2_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
6354 #define UMCCH2_2_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
6355 #define UMCCH2_2_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
6356 #define UMCCH2_2_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
6357 #define UMCCH2_2_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
6358 #define UMCCH2_2_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
6359 #define UMCCH2_2_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
6360 #define UMCCH2_2_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
6361 #define UMCCH2_2_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
6362 #define UMCCH2_2_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
6363 //UMCCH2_2_PerfMonCtr4_Lo
6364 #define UMCCH2_2_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
6365 #define UMCCH2_2_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
6366 //UMCCH2_2_PerfMonCtr4_Hi
6367 #define UMCCH2_2_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
6368 #define UMCCH2_2_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
6369 #define UMCCH2_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
6370 #define UMCCH2_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
6371 #define UMCCH2_2_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
6372 #define UMCCH2_2_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
6373 #define UMCCH2_2_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6374 #define UMCCH2_2_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6375 //UMCCH2_2_PerfMonCtl5
6376 #define UMCCH2_2_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
6377 #define UMCCH2_2_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
6378 #define UMCCH2_2_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
6379 #define UMCCH2_2_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
6380 #define UMCCH2_2_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
6381 #define UMCCH2_2_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
6382 #define UMCCH2_2_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
6383 #define UMCCH2_2_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
6384 #define UMCCH2_2_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
6385 #define UMCCH2_2_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
6386 #define UMCCH2_2_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
6387 #define UMCCH2_2_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
6388 #define UMCCH2_2_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
6389 #define UMCCH2_2_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
6390 #define UMCCH2_2_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
6391 #define UMCCH2_2_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
6392 //UMCCH2_2_PerfMonCtr5_Lo
6393 #define UMCCH2_2_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
6394 #define UMCCH2_2_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
6395 //UMCCH2_2_PerfMonCtr5_Hi
6396 #define UMCCH2_2_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
6397 #define UMCCH2_2_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
6398 #define UMCCH2_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
6399 #define UMCCH2_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
6400 #define UMCCH2_2_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
6401 #define UMCCH2_2_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
6402 #define UMCCH2_2_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6403 #define UMCCH2_2_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6404 //UMCCH2_2_PerfMonCtl6
6405 #define UMCCH2_2_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
6406 #define UMCCH2_2_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
6407 #define UMCCH2_2_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
6408 #define UMCCH2_2_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
6409 #define UMCCH2_2_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
6410 #define UMCCH2_2_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
6411 #define UMCCH2_2_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
6412 #define UMCCH2_2_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
6413 #define UMCCH2_2_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
6414 #define UMCCH2_2_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
6415 #define UMCCH2_2_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
6416 #define UMCCH2_2_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
6417 #define UMCCH2_2_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
6418 #define UMCCH2_2_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
6419 #define UMCCH2_2_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
6420 #define UMCCH2_2_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
6421 //UMCCH2_2_PerfMonCtr6_Lo
6422 #define UMCCH2_2_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
6423 #define UMCCH2_2_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
6424 //UMCCH2_2_PerfMonCtr6_Hi
6425 #define UMCCH2_2_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
6426 #define UMCCH2_2_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
6427 #define UMCCH2_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
6428 #define UMCCH2_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
6429 #define UMCCH2_2_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
6430 #define UMCCH2_2_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
6431 #define UMCCH2_2_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6432 #define UMCCH2_2_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6433 //UMCCH2_2_PerfMonCtl7
6434 #define UMCCH2_2_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
6435 #define UMCCH2_2_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
6436 #define UMCCH2_2_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
6437 #define UMCCH2_2_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
6438 #define UMCCH2_2_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
6439 #define UMCCH2_2_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
6440 #define UMCCH2_2_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
6441 #define UMCCH2_2_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
6442 #define UMCCH2_2_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
6443 #define UMCCH2_2_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
6444 #define UMCCH2_2_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
6445 #define UMCCH2_2_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
6446 #define UMCCH2_2_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
6447 #define UMCCH2_2_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
6448 #define UMCCH2_2_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
6449 #define UMCCH2_2_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
6450 //UMCCH2_2_PerfMonCtr7_Lo
6451 #define UMCCH2_2_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
6452 #define UMCCH2_2_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
6453 //UMCCH2_2_PerfMonCtr7_Hi
6454 #define UMCCH2_2_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
6455 #define UMCCH2_2_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
6456 #define UMCCH2_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
6457 #define UMCCH2_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
6458 #define UMCCH2_2_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
6459 #define UMCCH2_2_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
6460 #define UMCCH2_2_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6461 #define UMCCH2_2_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6462 //UMCCH2_2_PerfMonCtl8
6463 #define UMCCH2_2_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
6464 #define UMCCH2_2_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
6465 #define UMCCH2_2_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
6466 #define UMCCH2_2_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
6467 #define UMCCH2_2_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
6468 #define UMCCH2_2_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
6469 #define UMCCH2_2_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
6470 #define UMCCH2_2_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
6471 #define UMCCH2_2_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
6472 #define UMCCH2_2_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
6473 #define UMCCH2_2_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
6474 #define UMCCH2_2_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
6475 #define UMCCH2_2_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
6476 #define UMCCH2_2_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
6477 #define UMCCH2_2_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
6478 #define UMCCH2_2_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
6479 //UMCCH2_2_PerfMonCtr8_Lo
6480 #define UMCCH2_2_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
6481 #define UMCCH2_2_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
6482 //UMCCH2_2_PerfMonCtr8_Hi
6483 #define UMCCH2_2_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
6484 #define UMCCH2_2_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
6485 #define UMCCH2_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
6486 #define UMCCH2_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
6487 #define UMCCH2_2_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
6488 #define UMCCH2_2_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
6489 #define UMCCH2_2_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6490 #define UMCCH2_2_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6491 
6492 
6493 // addressBlock: umc_w_phy_umc2_umcch3_umcchdec
6494 //UMCCH3_2_BaseAddrCS0
6495 #define UMCCH3_2_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
6496 #define UMCCH3_2_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
6497 #define UMCCH3_2_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
6498 #define UMCCH3_2_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
6499 //UMCCH3_2_AddrMaskCS01
6500 #define UMCCH3_2_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
6501 #define UMCCH3_2_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
6502 //UMCCH3_2_AddrSelCS01
6503 #define UMCCH3_2_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
6504 #define UMCCH3_2_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
6505 #define UMCCH3_2_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
6506 #define UMCCH3_2_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
6507 #define UMCCH3_2_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
6508 #define UMCCH3_2_AddrSelCS01__RowLo__SHIFT                                                                    0x18
6509 #define UMCCH3_2_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
6510 #define UMCCH3_2_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
6511 #define UMCCH3_2_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
6512 #define UMCCH3_2_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
6513 #define UMCCH3_2_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
6514 #define UMCCH3_2_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
6515 #define UMCCH3_2_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
6516 #define UMCCH3_2_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
6517 //UMCCH3_2_AddrHashBank0
6518 #define UMCCH3_2_AddrHashBank0__XorEnable__SHIFT                                                              0x0
6519 #define UMCCH3_2_AddrHashBank0__ColXor__SHIFT                                                                 0x1
6520 #define UMCCH3_2_AddrHashBank0__RowXor__SHIFT                                                                 0xe
6521 #define UMCCH3_2_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
6522 #define UMCCH3_2_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
6523 #define UMCCH3_2_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
6524 //UMCCH3_2_AddrHashBank1
6525 #define UMCCH3_2_AddrHashBank1__XorEnable__SHIFT                                                              0x0
6526 #define UMCCH3_2_AddrHashBank1__ColXor__SHIFT                                                                 0x1
6527 #define UMCCH3_2_AddrHashBank1__RowXor__SHIFT                                                                 0xe
6528 #define UMCCH3_2_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
6529 #define UMCCH3_2_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
6530 #define UMCCH3_2_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
6531 //UMCCH3_2_AddrHashBank2
6532 #define UMCCH3_2_AddrHashBank2__XorEnable__SHIFT                                                              0x0
6533 #define UMCCH3_2_AddrHashBank2__ColXor__SHIFT                                                                 0x1
6534 #define UMCCH3_2_AddrHashBank2__RowXor__SHIFT                                                                 0xe
6535 #define UMCCH3_2_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
6536 #define UMCCH3_2_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
6537 #define UMCCH3_2_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
6538 //UMCCH3_2_AddrHashBank3
6539 #define UMCCH3_2_AddrHashBank3__XorEnable__SHIFT                                                              0x0
6540 #define UMCCH3_2_AddrHashBank3__ColXor__SHIFT                                                                 0x1
6541 #define UMCCH3_2_AddrHashBank3__RowXor__SHIFT                                                                 0xe
6542 #define UMCCH3_2_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
6543 #define UMCCH3_2_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
6544 #define UMCCH3_2_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
6545 //UMCCH3_2_AddrHashBank4
6546 #define UMCCH3_2_AddrHashBank4__XorEnable__SHIFT                                                              0x0
6547 #define UMCCH3_2_AddrHashBank4__ColXor__SHIFT                                                                 0x1
6548 #define UMCCH3_2_AddrHashBank4__RowXor__SHIFT                                                                 0xe
6549 #define UMCCH3_2_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
6550 #define UMCCH3_2_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
6551 #define UMCCH3_2_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
6552 //UMCCH3_2_AddrHashBank5
6553 #define UMCCH3_2_AddrHashBank5__XorEnable__SHIFT                                                              0x0
6554 #define UMCCH3_2_AddrHashBank5__ColXor__SHIFT                                                                 0x1
6555 #define UMCCH3_2_AddrHashBank5__RowXor__SHIFT                                                                 0xe
6556 #define UMCCH3_2_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
6557 #define UMCCH3_2_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
6558 #define UMCCH3_2_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
6559 //UMCCH3_2_EccErrCntSel
6560 #define UMCCH3_2_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
6561 #define UMCCH3_2_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
6562 #define UMCCH3_2_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
6563 #define UMCCH3_2_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
6564 #define UMCCH3_2_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
6565 #define UMCCH3_2_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
6566 //UMCCH3_2_EccErrCnt
6567 #define UMCCH3_2_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
6568 #define UMCCH3_2_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
6569 //UMCCH3_2_PerfMonCtlClk
6570 #define UMCCH3_2_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
6571 #define UMCCH3_2_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
6572 #define UMCCH3_2_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
6573 #define UMCCH3_2_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
6574 #define UMCCH3_2_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
6575 #define UMCCH3_2_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
6576 #define UMCCH3_2_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
6577 #define UMCCH3_2_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
6578 #define UMCCH3_2_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
6579 #define UMCCH3_2_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
6580 #define UMCCH3_2_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
6581 #define UMCCH3_2_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
6582 //UMCCH3_2_PerfMonCtrClk_Lo
6583 #define UMCCH3_2_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
6584 #define UMCCH3_2_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
6585 //UMCCH3_2_PerfMonCtrClk_Hi
6586 #define UMCCH3_2_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
6587 #define UMCCH3_2_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
6588 #define UMCCH3_2_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
6589 #define UMCCH3_2_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
6590 //UMCCH3_2_PerfMonCtl1
6591 #define UMCCH3_2_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
6592 #define UMCCH3_2_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
6593 #define UMCCH3_2_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
6594 #define UMCCH3_2_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
6595 #define UMCCH3_2_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
6596 #define UMCCH3_2_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
6597 #define UMCCH3_2_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
6598 #define UMCCH3_2_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
6599 #define UMCCH3_2_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
6600 #define UMCCH3_2_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
6601 #define UMCCH3_2_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
6602 #define UMCCH3_2_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
6603 #define UMCCH3_2_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
6604 #define UMCCH3_2_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
6605 #define UMCCH3_2_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
6606 #define UMCCH3_2_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
6607 //UMCCH3_2_PerfMonCtr1_Lo
6608 #define UMCCH3_2_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
6609 #define UMCCH3_2_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
6610 //UMCCH3_2_PerfMonCtr1_Hi
6611 #define UMCCH3_2_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
6612 #define UMCCH3_2_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
6613 #define UMCCH3_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
6614 #define UMCCH3_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
6615 #define UMCCH3_2_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
6616 #define UMCCH3_2_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
6617 #define UMCCH3_2_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6618 #define UMCCH3_2_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6619 //UMCCH3_2_PerfMonCtl2
6620 #define UMCCH3_2_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
6621 #define UMCCH3_2_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
6622 #define UMCCH3_2_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
6623 #define UMCCH3_2_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
6624 #define UMCCH3_2_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
6625 #define UMCCH3_2_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
6626 #define UMCCH3_2_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
6627 #define UMCCH3_2_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
6628 #define UMCCH3_2_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
6629 #define UMCCH3_2_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
6630 #define UMCCH3_2_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
6631 #define UMCCH3_2_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
6632 #define UMCCH3_2_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
6633 #define UMCCH3_2_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
6634 #define UMCCH3_2_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
6635 #define UMCCH3_2_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
6636 //UMCCH3_2_PerfMonCtr2_Lo
6637 #define UMCCH3_2_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
6638 #define UMCCH3_2_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
6639 //UMCCH3_2_PerfMonCtr2_Hi
6640 #define UMCCH3_2_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
6641 #define UMCCH3_2_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
6642 #define UMCCH3_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
6643 #define UMCCH3_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
6644 #define UMCCH3_2_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
6645 #define UMCCH3_2_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
6646 #define UMCCH3_2_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6647 #define UMCCH3_2_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6648 //UMCCH3_2_PerfMonCtl3
6649 #define UMCCH3_2_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
6650 #define UMCCH3_2_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
6651 #define UMCCH3_2_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
6652 #define UMCCH3_2_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
6653 #define UMCCH3_2_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
6654 #define UMCCH3_2_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
6655 #define UMCCH3_2_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
6656 #define UMCCH3_2_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
6657 #define UMCCH3_2_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
6658 #define UMCCH3_2_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
6659 #define UMCCH3_2_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
6660 #define UMCCH3_2_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
6661 #define UMCCH3_2_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
6662 #define UMCCH3_2_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
6663 #define UMCCH3_2_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
6664 #define UMCCH3_2_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
6665 //UMCCH3_2_PerfMonCtr3_Lo
6666 #define UMCCH3_2_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
6667 #define UMCCH3_2_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
6668 //UMCCH3_2_PerfMonCtr3_Hi
6669 #define UMCCH3_2_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
6670 #define UMCCH3_2_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
6671 #define UMCCH3_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
6672 #define UMCCH3_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
6673 #define UMCCH3_2_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
6674 #define UMCCH3_2_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
6675 #define UMCCH3_2_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6676 #define UMCCH3_2_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6677 //UMCCH3_2_PerfMonCtl4
6678 #define UMCCH3_2_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
6679 #define UMCCH3_2_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
6680 #define UMCCH3_2_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
6681 #define UMCCH3_2_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
6682 #define UMCCH3_2_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
6683 #define UMCCH3_2_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
6684 #define UMCCH3_2_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
6685 #define UMCCH3_2_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
6686 #define UMCCH3_2_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
6687 #define UMCCH3_2_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
6688 #define UMCCH3_2_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
6689 #define UMCCH3_2_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
6690 #define UMCCH3_2_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
6691 #define UMCCH3_2_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
6692 #define UMCCH3_2_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
6693 #define UMCCH3_2_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
6694 //UMCCH3_2_PerfMonCtr4_Lo
6695 #define UMCCH3_2_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
6696 #define UMCCH3_2_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
6697 //UMCCH3_2_PerfMonCtr4_Hi
6698 #define UMCCH3_2_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
6699 #define UMCCH3_2_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
6700 #define UMCCH3_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
6701 #define UMCCH3_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
6702 #define UMCCH3_2_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
6703 #define UMCCH3_2_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
6704 #define UMCCH3_2_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6705 #define UMCCH3_2_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6706 //UMCCH3_2_PerfMonCtl5
6707 #define UMCCH3_2_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
6708 #define UMCCH3_2_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
6709 #define UMCCH3_2_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
6710 #define UMCCH3_2_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
6711 #define UMCCH3_2_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
6712 #define UMCCH3_2_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
6713 #define UMCCH3_2_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
6714 #define UMCCH3_2_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
6715 #define UMCCH3_2_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
6716 #define UMCCH3_2_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
6717 #define UMCCH3_2_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
6718 #define UMCCH3_2_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
6719 #define UMCCH3_2_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
6720 #define UMCCH3_2_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
6721 #define UMCCH3_2_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
6722 #define UMCCH3_2_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
6723 //UMCCH3_2_PerfMonCtr5_Lo
6724 #define UMCCH3_2_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
6725 #define UMCCH3_2_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
6726 //UMCCH3_2_PerfMonCtr5_Hi
6727 #define UMCCH3_2_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
6728 #define UMCCH3_2_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
6729 #define UMCCH3_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
6730 #define UMCCH3_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
6731 #define UMCCH3_2_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
6732 #define UMCCH3_2_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
6733 #define UMCCH3_2_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6734 #define UMCCH3_2_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6735 //UMCCH3_2_PerfMonCtl6
6736 #define UMCCH3_2_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
6737 #define UMCCH3_2_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
6738 #define UMCCH3_2_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
6739 #define UMCCH3_2_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
6740 #define UMCCH3_2_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
6741 #define UMCCH3_2_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
6742 #define UMCCH3_2_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
6743 #define UMCCH3_2_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
6744 #define UMCCH3_2_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
6745 #define UMCCH3_2_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
6746 #define UMCCH3_2_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
6747 #define UMCCH3_2_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
6748 #define UMCCH3_2_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
6749 #define UMCCH3_2_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
6750 #define UMCCH3_2_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
6751 #define UMCCH3_2_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
6752 //UMCCH3_2_PerfMonCtr6_Lo
6753 #define UMCCH3_2_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
6754 #define UMCCH3_2_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
6755 //UMCCH3_2_PerfMonCtr6_Hi
6756 #define UMCCH3_2_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
6757 #define UMCCH3_2_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
6758 #define UMCCH3_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
6759 #define UMCCH3_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
6760 #define UMCCH3_2_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
6761 #define UMCCH3_2_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
6762 #define UMCCH3_2_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6763 #define UMCCH3_2_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6764 //UMCCH3_2_PerfMonCtl7
6765 #define UMCCH3_2_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
6766 #define UMCCH3_2_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
6767 #define UMCCH3_2_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
6768 #define UMCCH3_2_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
6769 #define UMCCH3_2_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
6770 #define UMCCH3_2_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
6771 #define UMCCH3_2_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
6772 #define UMCCH3_2_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
6773 #define UMCCH3_2_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
6774 #define UMCCH3_2_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
6775 #define UMCCH3_2_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
6776 #define UMCCH3_2_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
6777 #define UMCCH3_2_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
6778 #define UMCCH3_2_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
6779 #define UMCCH3_2_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
6780 #define UMCCH3_2_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
6781 //UMCCH3_2_PerfMonCtr7_Lo
6782 #define UMCCH3_2_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
6783 #define UMCCH3_2_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
6784 //UMCCH3_2_PerfMonCtr7_Hi
6785 #define UMCCH3_2_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
6786 #define UMCCH3_2_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
6787 #define UMCCH3_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
6788 #define UMCCH3_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
6789 #define UMCCH3_2_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
6790 #define UMCCH3_2_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
6791 #define UMCCH3_2_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6792 #define UMCCH3_2_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6793 //UMCCH3_2_PerfMonCtl8
6794 #define UMCCH3_2_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
6795 #define UMCCH3_2_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
6796 #define UMCCH3_2_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
6797 #define UMCCH3_2_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
6798 #define UMCCH3_2_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
6799 #define UMCCH3_2_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
6800 #define UMCCH3_2_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
6801 #define UMCCH3_2_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
6802 #define UMCCH3_2_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
6803 #define UMCCH3_2_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
6804 #define UMCCH3_2_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
6805 #define UMCCH3_2_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
6806 #define UMCCH3_2_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
6807 #define UMCCH3_2_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
6808 #define UMCCH3_2_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
6809 #define UMCCH3_2_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
6810 //UMCCH3_2_PerfMonCtr8_Lo
6811 #define UMCCH3_2_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
6812 #define UMCCH3_2_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
6813 //UMCCH3_2_PerfMonCtr8_Hi
6814 #define UMCCH3_2_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
6815 #define UMCCH3_2_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
6816 #define UMCCH3_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
6817 #define UMCCH3_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
6818 #define UMCCH3_2_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
6819 #define UMCCH3_2_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
6820 #define UMCCH3_2_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6821 #define UMCCH3_2_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6822 
6823 
6824 // addressBlock: umc_w_phy_umc2_umcch4_umcchdec
6825 //UMCCH4_2_BaseAddrCS0
6826 #define UMCCH4_2_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
6827 #define UMCCH4_2_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
6828 #define UMCCH4_2_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
6829 #define UMCCH4_2_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
6830 //UMCCH4_2_AddrMaskCS01
6831 #define UMCCH4_2_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
6832 #define UMCCH4_2_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
6833 //UMCCH4_2_AddrSelCS01
6834 #define UMCCH4_2_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
6835 #define UMCCH4_2_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
6836 #define UMCCH4_2_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
6837 #define UMCCH4_2_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
6838 #define UMCCH4_2_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
6839 #define UMCCH4_2_AddrSelCS01__RowLo__SHIFT                                                                    0x18
6840 #define UMCCH4_2_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
6841 #define UMCCH4_2_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
6842 #define UMCCH4_2_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
6843 #define UMCCH4_2_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
6844 #define UMCCH4_2_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
6845 #define UMCCH4_2_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
6846 #define UMCCH4_2_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
6847 #define UMCCH4_2_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
6848 //UMCCH4_2_AddrHashBank0
6849 #define UMCCH4_2_AddrHashBank0__XorEnable__SHIFT                                                              0x0
6850 #define UMCCH4_2_AddrHashBank0__ColXor__SHIFT                                                                 0x1
6851 #define UMCCH4_2_AddrHashBank0__RowXor__SHIFT                                                                 0xe
6852 #define UMCCH4_2_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
6853 #define UMCCH4_2_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
6854 #define UMCCH4_2_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
6855 //UMCCH4_2_AddrHashBank1
6856 #define UMCCH4_2_AddrHashBank1__XorEnable__SHIFT                                                              0x0
6857 #define UMCCH4_2_AddrHashBank1__ColXor__SHIFT                                                                 0x1
6858 #define UMCCH4_2_AddrHashBank1__RowXor__SHIFT                                                                 0xe
6859 #define UMCCH4_2_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
6860 #define UMCCH4_2_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
6861 #define UMCCH4_2_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
6862 //UMCCH4_2_AddrHashBank2
6863 #define UMCCH4_2_AddrHashBank2__XorEnable__SHIFT                                                              0x0
6864 #define UMCCH4_2_AddrHashBank2__ColXor__SHIFT                                                                 0x1
6865 #define UMCCH4_2_AddrHashBank2__RowXor__SHIFT                                                                 0xe
6866 #define UMCCH4_2_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
6867 #define UMCCH4_2_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
6868 #define UMCCH4_2_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
6869 //UMCCH4_2_AddrHashBank3
6870 #define UMCCH4_2_AddrHashBank3__XorEnable__SHIFT                                                              0x0
6871 #define UMCCH4_2_AddrHashBank3__ColXor__SHIFT                                                                 0x1
6872 #define UMCCH4_2_AddrHashBank3__RowXor__SHIFT                                                                 0xe
6873 #define UMCCH4_2_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
6874 #define UMCCH4_2_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
6875 #define UMCCH4_2_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
6876 //UMCCH4_2_AddrHashBank4
6877 #define UMCCH4_2_AddrHashBank4__XorEnable__SHIFT                                                              0x0
6878 #define UMCCH4_2_AddrHashBank4__ColXor__SHIFT                                                                 0x1
6879 #define UMCCH4_2_AddrHashBank4__RowXor__SHIFT                                                                 0xe
6880 #define UMCCH4_2_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
6881 #define UMCCH4_2_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
6882 #define UMCCH4_2_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
6883 //UMCCH4_2_AddrHashBank5
6884 #define UMCCH4_2_AddrHashBank5__XorEnable__SHIFT                                                              0x0
6885 #define UMCCH4_2_AddrHashBank5__ColXor__SHIFT                                                                 0x1
6886 #define UMCCH4_2_AddrHashBank5__RowXor__SHIFT                                                                 0xe
6887 #define UMCCH4_2_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
6888 #define UMCCH4_2_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
6889 #define UMCCH4_2_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
6890 //UMCCH4_2_EccErrCntSel
6891 #define UMCCH4_2_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
6892 #define UMCCH4_2_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
6893 #define UMCCH4_2_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
6894 #define UMCCH4_2_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
6895 #define UMCCH4_2_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
6896 #define UMCCH4_2_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
6897 //UMCCH4_2_EccErrCnt
6898 #define UMCCH4_2_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
6899 #define UMCCH4_2_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
6900 //UMCCH4_2_PerfMonCtlClk
6901 #define UMCCH4_2_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
6902 #define UMCCH4_2_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
6903 #define UMCCH4_2_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
6904 #define UMCCH4_2_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
6905 #define UMCCH4_2_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
6906 #define UMCCH4_2_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
6907 #define UMCCH4_2_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
6908 #define UMCCH4_2_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
6909 #define UMCCH4_2_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
6910 #define UMCCH4_2_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
6911 #define UMCCH4_2_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
6912 #define UMCCH4_2_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
6913 //UMCCH4_2_PerfMonCtrClk_Lo
6914 #define UMCCH4_2_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
6915 #define UMCCH4_2_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
6916 //UMCCH4_2_PerfMonCtrClk_Hi
6917 #define UMCCH4_2_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
6918 #define UMCCH4_2_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
6919 #define UMCCH4_2_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
6920 #define UMCCH4_2_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
6921 //UMCCH4_2_PerfMonCtl1
6922 #define UMCCH4_2_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
6923 #define UMCCH4_2_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
6924 #define UMCCH4_2_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
6925 #define UMCCH4_2_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
6926 #define UMCCH4_2_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
6927 #define UMCCH4_2_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
6928 #define UMCCH4_2_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
6929 #define UMCCH4_2_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
6930 #define UMCCH4_2_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
6931 #define UMCCH4_2_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
6932 #define UMCCH4_2_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
6933 #define UMCCH4_2_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
6934 #define UMCCH4_2_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
6935 #define UMCCH4_2_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
6936 #define UMCCH4_2_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
6937 #define UMCCH4_2_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
6938 //UMCCH4_2_PerfMonCtr1_Lo
6939 #define UMCCH4_2_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
6940 #define UMCCH4_2_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
6941 //UMCCH4_2_PerfMonCtr1_Hi
6942 #define UMCCH4_2_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
6943 #define UMCCH4_2_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
6944 #define UMCCH4_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
6945 #define UMCCH4_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
6946 #define UMCCH4_2_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
6947 #define UMCCH4_2_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
6948 #define UMCCH4_2_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6949 #define UMCCH4_2_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6950 //UMCCH4_2_PerfMonCtl2
6951 #define UMCCH4_2_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
6952 #define UMCCH4_2_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
6953 #define UMCCH4_2_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
6954 #define UMCCH4_2_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
6955 #define UMCCH4_2_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
6956 #define UMCCH4_2_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
6957 #define UMCCH4_2_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
6958 #define UMCCH4_2_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
6959 #define UMCCH4_2_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
6960 #define UMCCH4_2_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
6961 #define UMCCH4_2_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
6962 #define UMCCH4_2_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
6963 #define UMCCH4_2_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
6964 #define UMCCH4_2_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
6965 #define UMCCH4_2_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
6966 #define UMCCH4_2_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
6967 //UMCCH4_2_PerfMonCtr2_Lo
6968 #define UMCCH4_2_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
6969 #define UMCCH4_2_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
6970 //UMCCH4_2_PerfMonCtr2_Hi
6971 #define UMCCH4_2_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
6972 #define UMCCH4_2_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
6973 #define UMCCH4_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
6974 #define UMCCH4_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
6975 #define UMCCH4_2_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
6976 #define UMCCH4_2_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
6977 #define UMCCH4_2_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
6978 #define UMCCH4_2_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
6979 //UMCCH4_2_PerfMonCtl3
6980 #define UMCCH4_2_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
6981 #define UMCCH4_2_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
6982 #define UMCCH4_2_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
6983 #define UMCCH4_2_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
6984 #define UMCCH4_2_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
6985 #define UMCCH4_2_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
6986 #define UMCCH4_2_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
6987 #define UMCCH4_2_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
6988 #define UMCCH4_2_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
6989 #define UMCCH4_2_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
6990 #define UMCCH4_2_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
6991 #define UMCCH4_2_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
6992 #define UMCCH4_2_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
6993 #define UMCCH4_2_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
6994 #define UMCCH4_2_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
6995 #define UMCCH4_2_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
6996 //UMCCH4_2_PerfMonCtr3_Lo
6997 #define UMCCH4_2_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
6998 #define UMCCH4_2_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
6999 //UMCCH4_2_PerfMonCtr3_Hi
7000 #define UMCCH4_2_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
7001 #define UMCCH4_2_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
7002 #define UMCCH4_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
7003 #define UMCCH4_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
7004 #define UMCCH4_2_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
7005 #define UMCCH4_2_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
7006 #define UMCCH4_2_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7007 #define UMCCH4_2_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7008 //UMCCH4_2_PerfMonCtl4
7009 #define UMCCH4_2_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
7010 #define UMCCH4_2_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
7011 #define UMCCH4_2_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
7012 #define UMCCH4_2_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
7013 #define UMCCH4_2_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
7014 #define UMCCH4_2_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
7015 #define UMCCH4_2_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
7016 #define UMCCH4_2_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
7017 #define UMCCH4_2_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
7018 #define UMCCH4_2_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
7019 #define UMCCH4_2_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
7020 #define UMCCH4_2_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
7021 #define UMCCH4_2_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
7022 #define UMCCH4_2_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
7023 #define UMCCH4_2_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
7024 #define UMCCH4_2_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
7025 //UMCCH4_2_PerfMonCtr4_Lo
7026 #define UMCCH4_2_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
7027 #define UMCCH4_2_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
7028 //UMCCH4_2_PerfMonCtr4_Hi
7029 #define UMCCH4_2_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
7030 #define UMCCH4_2_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
7031 #define UMCCH4_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
7032 #define UMCCH4_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
7033 #define UMCCH4_2_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
7034 #define UMCCH4_2_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
7035 #define UMCCH4_2_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7036 #define UMCCH4_2_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7037 //UMCCH4_2_PerfMonCtl5
7038 #define UMCCH4_2_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
7039 #define UMCCH4_2_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
7040 #define UMCCH4_2_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
7041 #define UMCCH4_2_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
7042 #define UMCCH4_2_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
7043 #define UMCCH4_2_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
7044 #define UMCCH4_2_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
7045 #define UMCCH4_2_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
7046 #define UMCCH4_2_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
7047 #define UMCCH4_2_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
7048 #define UMCCH4_2_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
7049 #define UMCCH4_2_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
7050 #define UMCCH4_2_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
7051 #define UMCCH4_2_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
7052 #define UMCCH4_2_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
7053 #define UMCCH4_2_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
7054 //UMCCH4_2_PerfMonCtr5_Lo
7055 #define UMCCH4_2_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
7056 #define UMCCH4_2_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
7057 //UMCCH4_2_PerfMonCtr5_Hi
7058 #define UMCCH4_2_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
7059 #define UMCCH4_2_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
7060 #define UMCCH4_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
7061 #define UMCCH4_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
7062 #define UMCCH4_2_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
7063 #define UMCCH4_2_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
7064 #define UMCCH4_2_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7065 #define UMCCH4_2_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7066 //UMCCH4_2_PerfMonCtl6
7067 #define UMCCH4_2_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
7068 #define UMCCH4_2_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
7069 #define UMCCH4_2_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
7070 #define UMCCH4_2_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
7071 #define UMCCH4_2_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
7072 #define UMCCH4_2_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
7073 #define UMCCH4_2_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
7074 #define UMCCH4_2_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
7075 #define UMCCH4_2_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
7076 #define UMCCH4_2_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
7077 #define UMCCH4_2_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
7078 #define UMCCH4_2_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
7079 #define UMCCH4_2_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
7080 #define UMCCH4_2_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
7081 #define UMCCH4_2_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
7082 #define UMCCH4_2_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
7083 //UMCCH4_2_PerfMonCtr6_Lo
7084 #define UMCCH4_2_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
7085 #define UMCCH4_2_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
7086 //UMCCH4_2_PerfMonCtr6_Hi
7087 #define UMCCH4_2_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
7088 #define UMCCH4_2_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
7089 #define UMCCH4_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
7090 #define UMCCH4_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
7091 #define UMCCH4_2_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
7092 #define UMCCH4_2_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
7093 #define UMCCH4_2_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7094 #define UMCCH4_2_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7095 //UMCCH4_2_PerfMonCtl7
7096 #define UMCCH4_2_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
7097 #define UMCCH4_2_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
7098 #define UMCCH4_2_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
7099 #define UMCCH4_2_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
7100 #define UMCCH4_2_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
7101 #define UMCCH4_2_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
7102 #define UMCCH4_2_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
7103 #define UMCCH4_2_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
7104 #define UMCCH4_2_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
7105 #define UMCCH4_2_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
7106 #define UMCCH4_2_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
7107 #define UMCCH4_2_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
7108 #define UMCCH4_2_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
7109 #define UMCCH4_2_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
7110 #define UMCCH4_2_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
7111 #define UMCCH4_2_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
7112 //UMCCH4_2_PerfMonCtr7_Lo
7113 #define UMCCH4_2_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
7114 #define UMCCH4_2_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
7115 //UMCCH4_2_PerfMonCtr7_Hi
7116 #define UMCCH4_2_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
7117 #define UMCCH4_2_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
7118 #define UMCCH4_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
7119 #define UMCCH4_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
7120 #define UMCCH4_2_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
7121 #define UMCCH4_2_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
7122 #define UMCCH4_2_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7123 #define UMCCH4_2_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7124 //UMCCH4_2_PerfMonCtl8
7125 #define UMCCH4_2_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
7126 #define UMCCH4_2_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
7127 #define UMCCH4_2_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
7128 #define UMCCH4_2_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
7129 #define UMCCH4_2_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
7130 #define UMCCH4_2_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
7131 #define UMCCH4_2_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
7132 #define UMCCH4_2_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
7133 #define UMCCH4_2_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
7134 #define UMCCH4_2_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
7135 #define UMCCH4_2_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
7136 #define UMCCH4_2_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
7137 #define UMCCH4_2_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
7138 #define UMCCH4_2_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
7139 #define UMCCH4_2_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
7140 #define UMCCH4_2_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
7141 //UMCCH4_2_PerfMonCtr8_Lo
7142 #define UMCCH4_2_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
7143 #define UMCCH4_2_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
7144 //UMCCH4_2_PerfMonCtr8_Hi
7145 #define UMCCH4_2_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
7146 #define UMCCH4_2_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
7147 #define UMCCH4_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
7148 #define UMCCH4_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
7149 #define UMCCH4_2_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
7150 #define UMCCH4_2_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
7151 #define UMCCH4_2_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7152 #define UMCCH4_2_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7153 
7154 
7155 // addressBlock: umc_w_phy_umc2_umcch5_umcchdec
7156 //UMCCH5_2_BaseAddrCS0
7157 #define UMCCH5_2_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
7158 #define UMCCH5_2_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
7159 #define UMCCH5_2_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
7160 #define UMCCH5_2_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
7161 //UMCCH5_2_AddrMaskCS01
7162 #define UMCCH5_2_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
7163 #define UMCCH5_2_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
7164 //UMCCH5_2_AddrSelCS01
7165 #define UMCCH5_2_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
7166 #define UMCCH5_2_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
7167 #define UMCCH5_2_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
7168 #define UMCCH5_2_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
7169 #define UMCCH5_2_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
7170 #define UMCCH5_2_AddrSelCS01__RowLo__SHIFT                                                                    0x18
7171 #define UMCCH5_2_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
7172 #define UMCCH5_2_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
7173 #define UMCCH5_2_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
7174 #define UMCCH5_2_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
7175 #define UMCCH5_2_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
7176 #define UMCCH5_2_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
7177 #define UMCCH5_2_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
7178 #define UMCCH5_2_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
7179 //UMCCH5_2_AddrHashBank0
7180 #define UMCCH5_2_AddrHashBank0__XorEnable__SHIFT                                                              0x0
7181 #define UMCCH5_2_AddrHashBank0__ColXor__SHIFT                                                                 0x1
7182 #define UMCCH5_2_AddrHashBank0__RowXor__SHIFT                                                                 0xe
7183 #define UMCCH5_2_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
7184 #define UMCCH5_2_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
7185 #define UMCCH5_2_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
7186 //UMCCH5_2_AddrHashBank1
7187 #define UMCCH5_2_AddrHashBank1__XorEnable__SHIFT                                                              0x0
7188 #define UMCCH5_2_AddrHashBank1__ColXor__SHIFT                                                                 0x1
7189 #define UMCCH5_2_AddrHashBank1__RowXor__SHIFT                                                                 0xe
7190 #define UMCCH5_2_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
7191 #define UMCCH5_2_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
7192 #define UMCCH5_2_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
7193 //UMCCH5_2_AddrHashBank2
7194 #define UMCCH5_2_AddrHashBank2__XorEnable__SHIFT                                                              0x0
7195 #define UMCCH5_2_AddrHashBank2__ColXor__SHIFT                                                                 0x1
7196 #define UMCCH5_2_AddrHashBank2__RowXor__SHIFT                                                                 0xe
7197 #define UMCCH5_2_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
7198 #define UMCCH5_2_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
7199 #define UMCCH5_2_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
7200 //UMCCH5_2_AddrHashBank3
7201 #define UMCCH5_2_AddrHashBank3__XorEnable__SHIFT                                                              0x0
7202 #define UMCCH5_2_AddrHashBank3__ColXor__SHIFT                                                                 0x1
7203 #define UMCCH5_2_AddrHashBank3__RowXor__SHIFT                                                                 0xe
7204 #define UMCCH5_2_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
7205 #define UMCCH5_2_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
7206 #define UMCCH5_2_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
7207 //UMCCH5_2_AddrHashBank4
7208 #define UMCCH5_2_AddrHashBank4__XorEnable__SHIFT                                                              0x0
7209 #define UMCCH5_2_AddrHashBank4__ColXor__SHIFT                                                                 0x1
7210 #define UMCCH5_2_AddrHashBank4__RowXor__SHIFT                                                                 0xe
7211 #define UMCCH5_2_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
7212 #define UMCCH5_2_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
7213 #define UMCCH5_2_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
7214 //UMCCH5_2_AddrHashBank5
7215 #define UMCCH5_2_AddrHashBank5__XorEnable__SHIFT                                                              0x0
7216 #define UMCCH5_2_AddrHashBank5__ColXor__SHIFT                                                                 0x1
7217 #define UMCCH5_2_AddrHashBank5__RowXor__SHIFT                                                                 0xe
7218 #define UMCCH5_2_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
7219 #define UMCCH5_2_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
7220 #define UMCCH5_2_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
7221 //UMCCH5_2_EccErrCntSel
7222 #define UMCCH5_2_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
7223 #define UMCCH5_2_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
7224 #define UMCCH5_2_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
7225 #define UMCCH5_2_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
7226 #define UMCCH5_2_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
7227 #define UMCCH5_2_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
7228 //UMCCH5_2_EccErrCnt
7229 #define UMCCH5_2_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
7230 #define UMCCH5_2_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
7231 //UMCCH5_2_PerfMonCtlClk
7232 #define UMCCH5_2_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
7233 #define UMCCH5_2_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
7234 #define UMCCH5_2_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
7235 #define UMCCH5_2_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
7236 #define UMCCH5_2_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
7237 #define UMCCH5_2_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
7238 #define UMCCH5_2_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
7239 #define UMCCH5_2_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
7240 #define UMCCH5_2_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
7241 #define UMCCH5_2_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
7242 #define UMCCH5_2_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
7243 #define UMCCH5_2_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
7244 //UMCCH5_2_PerfMonCtrClk_Lo
7245 #define UMCCH5_2_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
7246 #define UMCCH5_2_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
7247 //UMCCH5_2_PerfMonCtrClk_Hi
7248 #define UMCCH5_2_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
7249 #define UMCCH5_2_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
7250 #define UMCCH5_2_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
7251 #define UMCCH5_2_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
7252 //UMCCH5_2_PerfMonCtl1
7253 #define UMCCH5_2_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
7254 #define UMCCH5_2_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
7255 #define UMCCH5_2_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
7256 #define UMCCH5_2_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
7257 #define UMCCH5_2_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
7258 #define UMCCH5_2_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
7259 #define UMCCH5_2_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
7260 #define UMCCH5_2_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
7261 #define UMCCH5_2_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
7262 #define UMCCH5_2_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
7263 #define UMCCH5_2_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
7264 #define UMCCH5_2_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
7265 #define UMCCH5_2_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
7266 #define UMCCH5_2_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
7267 #define UMCCH5_2_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
7268 #define UMCCH5_2_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
7269 //UMCCH5_2_PerfMonCtr1_Lo
7270 #define UMCCH5_2_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
7271 #define UMCCH5_2_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
7272 //UMCCH5_2_PerfMonCtr1_Hi
7273 #define UMCCH5_2_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
7274 #define UMCCH5_2_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
7275 #define UMCCH5_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
7276 #define UMCCH5_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
7277 #define UMCCH5_2_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
7278 #define UMCCH5_2_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
7279 #define UMCCH5_2_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7280 #define UMCCH5_2_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7281 //UMCCH5_2_PerfMonCtl2
7282 #define UMCCH5_2_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
7283 #define UMCCH5_2_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
7284 #define UMCCH5_2_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
7285 #define UMCCH5_2_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
7286 #define UMCCH5_2_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
7287 #define UMCCH5_2_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
7288 #define UMCCH5_2_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
7289 #define UMCCH5_2_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
7290 #define UMCCH5_2_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
7291 #define UMCCH5_2_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
7292 #define UMCCH5_2_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
7293 #define UMCCH5_2_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
7294 #define UMCCH5_2_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
7295 #define UMCCH5_2_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
7296 #define UMCCH5_2_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
7297 #define UMCCH5_2_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
7298 //UMCCH5_2_PerfMonCtr2_Lo
7299 #define UMCCH5_2_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
7300 #define UMCCH5_2_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
7301 //UMCCH5_2_PerfMonCtr2_Hi
7302 #define UMCCH5_2_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
7303 #define UMCCH5_2_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
7304 #define UMCCH5_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
7305 #define UMCCH5_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
7306 #define UMCCH5_2_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
7307 #define UMCCH5_2_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
7308 #define UMCCH5_2_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7309 #define UMCCH5_2_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7310 //UMCCH5_2_PerfMonCtl3
7311 #define UMCCH5_2_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
7312 #define UMCCH5_2_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
7313 #define UMCCH5_2_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
7314 #define UMCCH5_2_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
7315 #define UMCCH5_2_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
7316 #define UMCCH5_2_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
7317 #define UMCCH5_2_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
7318 #define UMCCH5_2_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
7319 #define UMCCH5_2_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
7320 #define UMCCH5_2_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
7321 #define UMCCH5_2_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
7322 #define UMCCH5_2_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
7323 #define UMCCH5_2_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
7324 #define UMCCH5_2_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
7325 #define UMCCH5_2_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
7326 #define UMCCH5_2_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
7327 //UMCCH5_2_PerfMonCtr3_Lo
7328 #define UMCCH5_2_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
7329 #define UMCCH5_2_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
7330 //UMCCH5_2_PerfMonCtr3_Hi
7331 #define UMCCH5_2_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
7332 #define UMCCH5_2_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
7333 #define UMCCH5_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
7334 #define UMCCH5_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
7335 #define UMCCH5_2_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
7336 #define UMCCH5_2_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
7337 #define UMCCH5_2_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7338 #define UMCCH5_2_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7339 //UMCCH5_2_PerfMonCtl4
7340 #define UMCCH5_2_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
7341 #define UMCCH5_2_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
7342 #define UMCCH5_2_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
7343 #define UMCCH5_2_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
7344 #define UMCCH5_2_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
7345 #define UMCCH5_2_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
7346 #define UMCCH5_2_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
7347 #define UMCCH5_2_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
7348 #define UMCCH5_2_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
7349 #define UMCCH5_2_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
7350 #define UMCCH5_2_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
7351 #define UMCCH5_2_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
7352 #define UMCCH5_2_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
7353 #define UMCCH5_2_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
7354 #define UMCCH5_2_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
7355 #define UMCCH5_2_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
7356 //UMCCH5_2_PerfMonCtr4_Lo
7357 #define UMCCH5_2_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
7358 #define UMCCH5_2_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
7359 //UMCCH5_2_PerfMonCtr4_Hi
7360 #define UMCCH5_2_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
7361 #define UMCCH5_2_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
7362 #define UMCCH5_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
7363 #define UMCCH5_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
7364 #define UMCCH5_2_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
7365 #define UMCCH5_2_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
7366 #define UMCCH5_2_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7367 #define UMCCH5_2_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7368 //UMCCH5_2_PerfMonCtl5
7369 #define UMCCH5_2_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
7370 #define UMCCH5_2_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
7371 #define UMCCH5_2_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
7372 #define UMCCH5_2_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
7373 #define UMCCH5_2_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
7374 #define UMCCH5_2_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
7375 #define UMCCH5_2_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
7376 #define UMCCH5_2_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
7377 #define UMCCH5_2_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
7378 #define UMCCH5_2_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
7379 #define UMCCH5_2_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
7380 #define UMCCH5_2_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
7381 #define UMCCH5_2_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
7382 #define UMCCH5_2_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
7383 #define UMCCH5_2_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
7384 #define UMCCH5_2_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
7385 //UMCCH5_2_PerfMonCtr5_Lo
7386 #define UMCCH5_2_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
7387 #define UMCCH5_2_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
7388 //UMCCH5_2_PerfMonCtr5_Hi
7389 #define UMCCH5_2_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
7390 #define UMCCH5_2_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
7391 #define UMCCH5_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
7392 #define UMCCH5_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
7393 #define UMCCH5_2_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
7394 #define UMCCH5_2_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
7395 #define UMCCH5_2_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7396 #define UMCCH5_2_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7397 //UMCCH5_2_PerfMonCtl6
7398 #define UMCCH5_2_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
7399 #define UMCCH5_2_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
7400 #define UMCCH5_2_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
7401 #define UMCCH5_2_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
7402 #define UMCCH5_2_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
7403 #define UMCCH5_2_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
7404 #define UMCCH5_2_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
7405 #define UMCCH5_2_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
7406 #define UMCCH5_2_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
7407 #define UMCCH5_2_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
7408 #define UMCCH5_2_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
7409 #define UMCCH5_2_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
7410 #define UMCCH5_2_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
7411 #define UMCCH5_2_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
7412 #define UMCCH5_2_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
7413 #define UMCCH5_2_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
7414 //UMCCH5_2_PerfMonCtr6_Lo
7415 #define UMCCH5_2_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
7416 #define UMCCH5_2_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
7417 //UMCCH5_2_PerfMonCtr6_Hi
7418 #define UMCCH5_2_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
7419 #define UMCCH5_2_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
7420 #define UMCCH5_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
7421 #define UMCCH5_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
7422 #define UMCCH5_2_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
7423 #define UMCCH5_2_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
7424 #define UMCCH5_2_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7425 #define UMCCH5_2_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7426 //UMCCH5_2_PerfMonCtl7
7427 #define UMCCH5_2_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
7428 #define UMCCH5_2_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
7429 #define UMCCH5_2_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
7430 #define UMCCH5_2_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
7431 #define UMCCH5_2_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
7432 #define UMCCH5_2_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
7433 #define UMCCH5_2_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
7434 #define UMCCH5_2_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
7435 #define UMCCH5_2_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
7436 #define UMCCH5_2_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
7437 #define UMCCH5_2_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
7438 #define UMCCH5_2_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
7439 #define UMCCH5_2_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
7440 #define UMCCH5_2_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
7441 #define UMCCH5_2_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
7442 #define UMCCH5_2_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
7443 //UMCCH5_2_PerfMonCtr7_Lo
7444 #define UMCCH5_2_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
7445 #define UMCCH5_2_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
7446 //UMCCH5_2_PerfMonCtr7_Hi
7447 #define UMCCH5_2_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
7448 #define UMCCH5_2_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
7449 #define UMCCH5_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
7450 #define UMCCH5_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
7451 #define UMCCH5_2_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
7452 #define UMCCH5_2_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
7453 #define UMCCH5_2_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7454 #define UMCCH5_2_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7455 //UMCCH5_2_PerfMonCtl8
7456 #define UMCCH5_2_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
7457 #define UMCCH5_2_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
7458 #define UMCCH5_2_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
7459 #define UMCCH5_2_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
7460 #define UMCCH5_2_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
7461 #define UMCCH5_2_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
7462 #define UMCCH5_2_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
7463 #define UMCCH5_2_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
7464 #define UMCCH5_2_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
7465 #define UMCCH5_2_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
7466 #define UMCCH5_2_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
7467 #define UMCCH5_2_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
7468 #define UMCCH5_2_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
7469 #define UMCCH5_2_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
7470 #define UMCCH5_2_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
7471 #define UMCCH5_2_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
7472 //UMCCH5_2_PerfMonCtr8_Lo
7473 #define UMCCH5_2_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
7474 #define UMCCH5_2_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
7475 //UMCCH5_2_PerfMonCtr8_Hi
7476 #define UMCCH5_2_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
7477 #define UMCCH5_2_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
7478 #define UMCCH5_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
7479 #define UMCCH5_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
7480 #define UMCCH5_2_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
7481 #define UMCCH5_2_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
7482 #define UMCCH5_2_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7483 #define UMCCH5_2_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7484 
7485 
7486 // addressBlock: umc_w_phy_umc2_umcch6_umcchdec
7487 //UMCCH6_2_BaseAddrCS0
7488 #define UMCCH6_2_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
7489 #define UMCCH6_2_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
7490 #define UMCCH6_2_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
7491 #define UMCCH6_2_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
7492 //UMCCH6_2_AddrMaskCS01
7493 #define UMCCH6_2_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
7494 #define UMCCH6_2_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
7495 //UMCCH6_2_AddrSelCS01
7496 #define UMCCH6_2_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
7497 #define UMCCH6_2_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
7498 #define UMCCH6_2_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
7499 #define UMCCH6_2_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
7500 #define UMCCH6_2_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
7501 #define UMCCH6_2_AddrSelCS01__RowLo__SHIFT                                                                    0x18
7502 #define UMCCH6_2_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
7503 #define UMCCH6_2_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
7504 #define UMCCH6_2_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
7505 #define UMCCH6_2_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
7506 #define UMCCH6_2_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
7507 #define UMCCH6_2_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
7508 #define UMCCH6_2_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
7509 #define UMCCH6_2_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
7510 //UMCCH6_2_AddrHashBank0
7511 #define UMCCH6_2_AddrHashBank0__XorEnable__SHIFT                                                              0x0
7512 #define UMCCH6_2_AddrHashBank0__ColXor__SHIFT                                                                 0x1
7513 #define UMCCH6_2_AddrHashBank0__RowXor__SHIFT                                                                 0xe
7514 #define UMCCH6_2_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
7515 #define UMCCH6_2_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
7516 #define UMCCH6_2_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
7517 //UMCCH6_2_AddrHashBank1
7518 #define UMCCH6_2_AddrHashBank1__XorEnable__SHIFT                                                              0x0
7519 #define UMCCH6_2_AddrHashBank1__ColXor__SHIFT                                                                 0x1
7520 #define UMCCH6_2_AddrHashBank1__RowXor__SHIFT                                                                 0xe
7521 #define UMCCH6_2_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
7522 #define UMCCH6_2_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
7523 #define UMCCH6_2_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
7524 //UMCCH6_2_AddrHashBank2
7525 #define UMCCH6_2_AddrHashBank2__XorEnable__SHIFT                                                              0x0
7526 #define UMCCH6_2_AddrHashBank2__ColXor__SHIFT                                                                 0x1
7527 #define UMCCH6_2_AddrHashBank2__RowXor__SHIFT                                                                 0xe
7528 #define UMCCH6_2_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
7529 #define UMCCH6_2_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
7530 #define UMCCH6_2_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
7531 //UMCCH6_2_AddrHashBank3
7532 #define UMCCH6_2_AddrHashBank3__XorEnable__SHIFT                                                              0x0
7533 #define UMCCH6_2_AddrHashBank3__ColXor__SHIFT                                                                 0x1
7534 #define UMCCH6_2_AddrHashBank3__RowXor__SHIFT                                                                 0xe
7535 #define UMCCH6_2_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
7536 #define UMCCH6_2_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
7537 #define UMCCH6_2_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
7538 //UMCCH6_2_AddrHashBank4
7539 #define UMCCH6_2_AddrHashBank4__XorEnable__SHIFT                                                              0x0
7540 #define UMCCH6_2_AddrHashBank4__ColXor__SHIFT                                                                 0x1
7541 #define UMCCH6_2_AddrHashBank4__RowXor__SHIFT                                                                 0xe
7542 #define UMCCH6_2_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
7543 #define UMCCH6_2_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
7544 #define UMCCH6_2_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
7545 //UMCCH6_2_AddrHashBank5
7546 #define UMCCH6_2_AddrHashBank5__XorEnable__SHIFT                                                              0x0
7547 #define UMCCH6_2_AddrHashBank5__ColXor__SHIFT                                                                 0x1
7548 #define UMCCH6_2_AddrHashBank5__RowXor__SHIFT                                                                 0xe
7549 #define UMCCH6_2_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
7550 #define UMCCH6_2_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
7551 #define UMCCH6_2_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
7552 //UMCCH6_2_EccErrCntSel
7553 #define UMCCH6_2_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
7554 #define UMCCH6_2_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
7555 #define UMCCH6_2_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
7556 #define UMCCH6_2_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
7557 #define UMCCH6_2_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
7558 #define UMCCH6_2_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
7559 //UMCCH6_2_EccErrCnt
7560 #define UMCCH6_2_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
7561 #define UMCCH6_2_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
7562 //UMCCH6_2_PerfMonCtlClk
7563 #define UMCCH6_2_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
7564 #define UMCCH6_2_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
7565 #define UMCCH6_2_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
7566 #define UMCCH6_2_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
7567 #define UMCCH6_2_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
7568 #define UMCCH6_2_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
7569 #define UMCCH6_2_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
7570 #define UMCCH6_2_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
7571 #define UMCCH6_2_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
7572 #define UMCCH6_2_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
7573 #define UMCCH6_2_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
7574 #define UMCCH6_2_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
7575 //UMCCH6_2_PerfMonCtrClk_Lo
7576 #define UMCCH6_2_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
7577 #define UMCCH6_2_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
7578 //UMCCH6_2_PerfMonCtrClk_Hi
7579 #define UMCCH6_2_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
7580 #define UMCCH6_2_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
7581 #define UMCCH6_2_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
7582 #define UMCCH6_2_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
7583 //UMCCH6_2_PerfMonCtl1
7584 #define UMCCH6_2_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
7585 #define UMCCH6_2_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
7586 #define UMCCH6_2_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
7587 #define UMCCH6_2_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
7588 #define UMCCH6_2_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
7589 #define UMCCH6_2_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
7590 #define UMCCH6_2_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
7591 #define UMCCH6_2_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
7592 #define UMCCH6_2_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
7593 #define UMCCH6_2_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
7594 #define UMCCH6_2_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
7595 #define UMCCH6_2_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
7596 #define UMCCH6_2_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
7597 #define UMCCH6_2_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
7598 #define UMCCH6_2_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
7599 #define UMCCH6_2_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
7600 //UMCCH6_2_PerfMonCtr1_Lo
7601 #define UMCCH6_2_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
7602 #define UMCCH6_2_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
7603 //UMCCH6_2_PerfMonCtr1_Hi
7604 #define UMCCH6_2_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
7605 #define UMCCH6_2_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
7606 #define UMCCH6_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
7607 #define UMCCH6_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
7608 #define UMCCH6_2_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
7609 #define UMCCH6_2_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
7610 #define UMCCH6_2_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7611 #define UMCCH6_2_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7612 //UMCCH6_2_PerfMonCtl2
7613 #define UMCCH6_2_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
7614 #define UMCCH6_2_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
7615 #define UMCCH6_2_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
7616 #define UMCCH6_2_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
7617 #define UMCCH6_2_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
7618 #define UMCCH6_2_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
7619 #define UMCCH6_2_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
7620 #define UMCCH6_2_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
7621 #define UMCCH6_2_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
7622 #define UMCCH6_2_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
7623 #define UMCCH6_2_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
7624 #define UMCCH6_2_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
7625 #define UMCCH6_2_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
7626 #define UMCCH6_2_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
7627 #define UMCCH6_2_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
7628 #define UMCCH6_2_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
7629 //UMCCH6_2_PerfMonCtr2_Lo
7630 #define UMCCH6_2_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
7631 #define UMCCH6_2_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
7632 //UMCCH6_2_PerfMonCtr2_Hi
7633 #define UMCCH6_2_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
7634 #define UMCCH6_2_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
7635 #define UMCCH6_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
7636 #define UMCCH6_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
7637 #define UMCCH6_2_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
7638 #define UMCCH6_2_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
7639 #define UMCCH6_2_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7640 #define UMCCH6_2_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7641 //UMCCH6_2_PerfMonCtl3
7642 #define UMCCH6_2_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
7643 #define UMCCH6_2_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
7644 #define UMCCH6_2_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
7645 #define UMCCH6_2_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
7646 #define UMCCH6_2_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
7647 #define UMCCH6_2_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
7648 #define UMCCH6_2_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
7649 #define UMCCH6_2_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
7650 #define UMCCH6_2_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
7651 #define UMCCH6_2_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
7652 #define UMCCH6_2_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
7653 #define UMCCH6_2_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
7654 #define UMCCH6_2_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
7655 #define UMCCH6_2_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
7656 #define UMCCH6_2_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
7657 #define UMCCH6_2_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
7658 //UMCCH6_2_PerfMonCtr3_Lo
7659 #define UMCCH6_2_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
7660 #define UMCCH6_2_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
7661 //UMCCH6_2_PerfMonCtr3_Hi
7662 #define UMCCH6_2_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
7663 #define UMCCH6_2_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
7664 #define UMCCH6_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
7665 #define UMCCH6_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
7666 #define UMCCH6_2_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
7667 #define UMCCH6_2_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
7668 #define UMCCH6_2_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7669 #define UMCCH6_2_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7670 //UMCCH6_2_PerfMonCtl4
7671 #define UMCCH6_2_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
7672 #define UMCCH6_2_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
7673 #define UMCCH6_2_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
7674 #define UMCCH6_2_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
7675 #define UMCCH6_2_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
7676 #define UMCCH6_2_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
7677 #define UMCCH6_2_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
7678 #define UMCCH6_2_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
7679 #define UMCCH6_2_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
7680 #define UMCCH6_2_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
7681 #define UMCCH6_2_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
7682 #define UMCCH6_2_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
7683 #define UMCCH6_2_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
7684 #define UMCCH6_2_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
7685 #define UMCCH6_2_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
7686 #define UMCCH6_2_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
7687 //UMCCH6_2_PerfMonCtr4_Lo
7688 #define UMCCH6_2_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
7689 #define UMCCH6_2_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
7690 //UMCCH6_2_PerfMonCtr4_Hi
7691 #define UMCCH6_2_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
7692 #define UMCCH6_2_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
7693 #define UMCCH6_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
7694 #define UMCCH6_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
7695 #define UMCCH6_2_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
7696 #define UMCCH6_2_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
7697 #define UMCCH6_2_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7698 #define UMCCH6_2_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7699 //UMCCH6_2_PerfMonCtl5
7700 #define UMCCH6_2_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
7701 #define UMCCH6_2_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
7702 #define UMCCH6_2_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
7703 #define UMCCH6_2_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
7704 #define UMCCH6_2_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
7705 #define UMCCH6_2_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
7706 #define UMCCH6_2_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
7707 #define UMCCH6_2_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
7708 #define UMCCH6_2_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
7709 #define UMCCH6_2_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
7710 #define UMCCH6_2_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
7711 #define UMCCH6_2_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
7712 #define UMCCH6_2_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
7713 #define UMCCH6_2_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
7714 #define UMCCH6_2_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
7715 #define UMCCH6_2_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
7716 //UMCCH6_2_PerfMonCtr5_Lo
7717 #define UMCCH6_2_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
7718 #define UMCCH6_2_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
7719 //UMCCH6_2_PerfMonCtr5_Hi
7720 #define UMCCH6_2_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
7721 #define UMCCH6_2_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
7722 #define UMCCH6_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
7723 #define UMCCH6_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
7724 #define UMCCH6_2_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
7725 #define UMCCH6_2_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
7726 #define UMCCH6_2_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7727 #define UMCCH6_2_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7728 //UMCCH6_2_PerfMonCtl6
7729 #define UMCCH6_2_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
7730 #define UMCCH6_2_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
7731 #define UMCCH6_2_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
7732 #define UMCCH6_2_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
7733 #define UMCCH6_2_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
7734 #define UMCCH6_2_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
7735 #define UMCCH6_2_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
7736 #define UMCCH6_2_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
7737 #define UMCCH6_2_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
7738 #define UMCCH6_2_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
7739 #define UMCCH6_2_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
7740 #define UMCCH6_2_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
7741 #define UMCCH6_2_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
7742 #define UMCCH6_2_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
7743 #define UMCCH6_2_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
7744 #define UMCCH6_2_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
7745 //UMCCH6_2_PerfMonCtr6_Lo
7746 #define UMCCH6_2_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
7747 #define UMCCH6_2_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
7748 //UMCCH6_2_PerfMonCtr6_Hi
7749 #define UMCCH6_2_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
7750 #define UMCCH6_2_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
7751 #define UMCCH6_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
7752 #define UMCCH6_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
7753 #define UMCCH6_2_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
7754 #define UMCCH6_2_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
7755 #define UMCCH6_2_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7756 #define UMCCH6_2_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7757 //UMCCH6_2_PerfMonCtl7
7758 #define UMCCH6_2_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
7759 #define UMCCH6_2_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
7760 #define UMCCH6_2_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
7761 #define UMCCH6_2_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
7762 #define UMCCH6_2_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
7763 #define UMCCH6_2_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
7764 #define UMCCH6_2_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
7765 #define UMCCH6_2_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
7766 #define UMCCH6_2_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
7767 #define UMCCH6_2_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
7768 #define UMCCH6_2_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
7769 #define UMCCH6_2_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
7770 #define UMCCH6_2_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
7771 #define UMCCH6_2_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
7772 #define UMCCH6_2_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
7773 #define UMCCH6_2_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
7774 //UMCCH6_2_PerfMonCtr7_Lo
7775 #define UMCCH6_2_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
7776 #define UMCCH6_2_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
7777 //UMCCH6_2_PerfMonCtr7_Hi
7778 #define UMCCH6_2_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
7779 #define UMCCH6_2_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
7780 #define UMCCH6_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
7781 #define UMCCH6_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
7782 #define UMCCH6_2_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
7783 #define UMCCH6_2_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
7784 #define UMCCH6_2_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7785 #define UMCCH6_2_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7786 //UMCCH6_2_PerfMonCtl8
7787 #define UMCCH6_2_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
7788 #define UMCCH6_2_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
7789 #define UMCCH6_2_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
7790 #define UMCCH6_2_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
7791 #define UMCCH6_2_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
7792 #define UMCCH6_2_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
7793 #define UMCCH6_2_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
7794 #define UMCCH6_2_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
7795 #define UMCCH6_2_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
7796 #define UMCCH6_2_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
7797 #define UMCCH6_2_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
7798 #define UMCCH6_2_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
7799 #define UMCCH6_2_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
7800 #define UMCCH6_2_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
7801 #define UMCCH6_2_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
7802 #define UMCCH6_2_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
7803 //UMCCH6_2_PerfMonCtr8_Lo
7804 #define UMCCH6_2_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
7805 #define UMCCH6_2_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
7806 //UMCCH6_2_PerfMonCtr8_Hi
7807 #define UMCCH6_2_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
7808 #define UMCCH6_2_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
7809 #define UMCCH6_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
7810 #define UMCCH6_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
7811 #define UMCCH6_2_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
7812 #define UMCCH6_2_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
7813 #define UMCCH6_2_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7814 #define UMCCH6_2_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7815 
7816 
7817 // addressBlock: umc_w_phy_umc2_umcch7_umcchdec
7818 //UMCCH7_2_BaseAddrCS0
7819 #define UMCCH7_2_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
7820 #define UMCCH7_2_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
7821 #define UMCCH7_2_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
7822 #define UMCCH7_2_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
7823 //UMCCH7_2_AddrMaskCS01
7824 #define UMCCH7_2_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
7825 #define UMCCH7_2_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
7826 //UMCCH7_2_AddrSelCS01
7827 #define UMCCH7_2_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
7828 #define UMCCH7_2_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
7829 #define UMCCH7_2_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
7830 #define UMCCH7_2_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
7831 #define UMCCH7_2_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
7832 #define UMCCH7_2_AddrSelCS01__RowLo__SHIFT                                                                    0x18
7833 #define UMCCH7_2_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
7834 #define UMCCH7_2_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
7835 #define UMCCH7_2_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
7836 #define UMCCH7_2_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
7837 #define UMCCH7_2_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
7838 #define UMCCH7_2_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
7839 #define UMCCH7_2_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
7840 #define UMCCH7_2_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
7841 //UMCCH7_2_AddrHashBank0
7842 #define UMCCH7_2_AddrHashBank0__XorEnable__SHIFT                                                              0x0
7843 #define UMCCH7_2_AddrHashBank0__ColXor__SHIFT                                                                 0x1
7844 #define UMCCH7_2_AddrHashBank0__RowXor__SHIFT                                                                 0xe
7845 #define UMCCH7_2_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
7846 #define UMCCH7_2_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
7847 #define UMCCH7_2_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
7848 //UMCCH7_2_AddrHashBank1
7849 #define UMCCH7_2_AddrHashBank1__XorEnable__SHIFT                                                              0x0
7850 #define UMCCH7_2_AddrHashBank1__ColXor__SHIFT                                                                 0x1
7851 #define UMCCH7_2_AddrHashBank1__RowXor__SHIFT                                                                 0xe
7852 #define UMCCH7_2_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
7853 #define UMCCH7_2_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
7854 #define UMCCH7_2_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
7855 //UMCCH7_2_AddrHashBank2
7856 #define UMCCH7_2_AddrHashBank2__XorEnable__SHIFT                                                              0x0
7857 #define UMCCH7_2_AddrHashBank2__ColXor__SHIFT                                                                 0x1
7858 #define UMCCH7_2_AddrHashBank2__RowXor__SHIFT                                                                 0xe
7859 #define UMCCH7_2_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
7860 #define UMCCH7_2_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
7861 #define UMCCH7_2_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
7862 //UMCCH7_2_AddrHashBank3
7863 #define UMCCH7_2_AddrHashBank3__XorEnable__SHIFT                                                              0x0
7864 #define UMCCH7_2_AddrHashBank3__ColXor__SHIFT                                                                 0x1
7865 #define UMCCH7_2_AddrHashBank3__RowXor__SHIFT                                                                 0xe
7866 #define UMCCH7_2_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
7867 #define UMCCH7_2_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
7868 #define UMCCH7_2_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
7869 //UMCCH7_2_AddrHashBank4
7870 #define UMCCH7_2_AddrHashBank4__XorEnable__SHIFT                                                              0x0
7871 #define UMCCH7_2_AddrHashBank4__ColXor__SHIFT                                                                 0x1
7872 #define UMCCH7_2_AddrHashBank4__RowXor__SHIFT                                                                 0xe
7873 #define UMCCH7_2_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
7874 #define UMCCH7_2_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
7875 #define UMCCH7_2_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
7876 //UMCCH7_2_AddrHashBank5
7877 #define UMCCH7_2_AddrHashBank5__XorEnable__SHIFT                                                              0x0
7878 #define UMCCH7_2_AddrHashBank5__ColXor__SHIFT                                                                 0x1
7879 #define UMCCH7_2_AddrHashBank5__RowXor__SHIFT                                                                 0xe
7880 #define UMCCH7_2_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
7881 #define UMCCH7_2_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
7882 #define UMCCH7_2_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
7883 //UMCCH7_2_EccErrCntSel
7884 #define UMCCH7_2_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
7885 #define UMCCH7_2_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
7886 #define UMCCH7_2_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
7887 #define UMCCH7_2_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
7888 #define UMCCH7_2_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
7889 #define UMCCH7_2_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
7890 //UMCCH7_2_EccErrCnt
7891 #define UMCCH7_2_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
7892 #define UMCCH7_2_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
7893 //UMCCH7_2_PerfMonCtlClk
7894 #define UMCCH7_2_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
7895 #define UMCCH7_2_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
7896 #define UMCCH7_2_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
7897 #define UMCCH7_2_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
7898 #define UMCCH7_2_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
7899 #define UMCCH7_2_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
7900 #define UMCCH7_2_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
7901 #define UMCCH7_2_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
7902 #define UMCCH7_2_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
7903 #define UMCCH7_2_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
7904 #define UMCCH7_2_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
7905 #define UMCCH7_2_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
7906 //UMCCH7_2_PerfMonCtrClk_Lo
7907 #define UMCCH7_2_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
7908 #define UMCCH7_2_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
7909 //UMCCH7_2_PerfMonCtrClk_Hi
7910 #define UMCCH7_2_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
7911 #define UMCCH7_2_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
7912 #define UMCCH7_2_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
7913 #define UMCCH7_2_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
7914 //UMCCH7_2_PerfMonCtl1
7915 #define UMCCH7_2_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
7916 #define UMCCH7_2_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
7917 #define UMCCH7_2_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
7918 #define UMCCH7_2_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
7919 #define UMCCH7_2_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
7920 #define UMCCH7_2_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
7921 #define UMCCH7_2_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
7922 #define UMCCH7_2_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
7923 #define UMCCH7_2_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
7924 #define UMCCH7_2_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
7925 #define UMCCH7_2_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
7926 #define UMCCH7_2_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
7927 #define UMCCH7_2_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
7928 #define UMCCH7_2_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
7929 #define UMCCH7_2_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
7930 #define UMCCH7_2_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
7931 //UMCCH7_2_PerfMonCtr1_Lo
7932 #define UMCCH7_2_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
7933 #define UMCCH7_2_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
7934 //UMCCH7_2_PerfMonCtr1_Hi
7935 #define UMCCH7_2_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
7936 #define UMCCH7_2_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
7937 #define UMCCH7_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
7938 #define UMCCH7_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
7939 #define UMCCH7_2_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
7940 #define UMCCH7_2_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
7941 #define UMCCH7_2_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7942 #define UMCCH7_2_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7943 //UMCCH7_2_PerfMonCtl2
7944 #define UMCCH7_2_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
7945 #define UMCCH7_2_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
7946 #define UMCCH7_2_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
7947 #define UMCCH7_2_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
7948 #define UMCCH7_2_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
7949 #define UMCCH7_2_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
7950 #define UMCCH7_2_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
7951 #define UMCCH7_2_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
7952 #define UMCCH7_2_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
7953 #define UMCCH7_2_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
7954 #define UMCCH7_2_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
7955 #define UMCCH7_2_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
7956 #define UMCCH7_2_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
7957 #define UMCCH7_2_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
7958 #define UMCCH7_2_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
7959 #define UMCCH7_2_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
7960 //UMCCH7_2_PerfMonCtr2_Lo
7961 #define UMCCH7_2_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
7962 #define UMCCH7_2_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
7963 //UMCCH7_2_PerfMonCtr2_Hi
7964 #define UMCCH7_2_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
7965 #define UMCCH7_2_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
7966 #define UMCCH7_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
7967 #define UMCCH7_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
7968 #define UMCCH7_2_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
7969 #define UMCCH7_2_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
7970 #define UMCCH7_2_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
7971 #define UMCCH7_2_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
7972 //UMCCH7_2_PerfMonCtl3
7973 #define UMCCH7_2_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
7974 #define UMCCH7_2_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
7975 #define UMCCH7_2_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
7976 #define UMCCH7_2_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
7977 #define UMCCH7_2_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
7978 #define UMCCH7_2_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
7979 #define UMCCH7_2_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
7980 #define UMCCH7_2_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
7981 #define UMCCH7_2_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
7982 #define UMCCH7_2_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
7983 #define UMCCH7_2_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
7984 #define UMCCH7_2_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
7985 #define UMCCH7_2_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
7986 #define UMCCH7_2_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
7987 #define UMCCH7_2_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
7988 #define UMCCH7_2_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
7989 //UMCCH7_2_PerfMonCtr3_Lo
7990 #define UMCCH7_2_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
7991 #define UMCCH7_2_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
7992 //UMCCH7_2_PerfMonCtr3_Hi
7993 #define UMCCH7_2_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
7994 #define UMCCH7_2_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
7995 #define UMCCH7_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
7996 #define UMCCH7_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
7997 #define UMCCH7_2_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
7998 #define UMCCH7_2_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
7999 #define UMCCH7_2_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8000 #define UMCCH7_2_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8001 //UMCCH7_2_PerfMonCtl4
8002 #define UMCCH7_2_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
8003 #define UMCCH7_2_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
8004 #define UMCCH7_2_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
8005 #define UMCCH7_2_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
8006 #define UMCCH7_2_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
8007 #define UMCCH7_2_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
8008 #define UMCCH7_2_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
8009 #define UMCCH7_2_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
8010 #define UMCCH7_2_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
8011 #define UMCCH7_2_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
8012 #define UMCCH7_2_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
8013 #define UMCCH7_2_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
8014 #define UMCCH7_2_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
8015 #define UMCCH7_2_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
8016 #define UMCCH7_2_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
8017 #define UMCCH7_2_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
8018 //UMCCH7_2_PerfMonCtr4_Lo
8019 #define UMCCH7_2_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
8020 #define UMCCH7_2_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
8021 //UMCCH7_2_PerfMonCtr4_Hi
8022 #define UMCCH7_2_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
8023 #define UMCCH7_2_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
8024 #define UMCCH7_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
8025 #define UMCCH7_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
8026 #define UMCCH7_2_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
8027 #define UMCCH7_2_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
8028 #define UMCCH7_2_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8029 #define UMCCH7_2_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8030 //UMCCH7_2_PerfMonCtl5
8031 #define UMCCH7_2_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
8032 #define UMCCH7_2_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
8033 #define UMCCH7_2_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
8034 #define UMCCH7_2_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
8035 #define UMCCH7_2_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
8036 #define UMCCH7_2_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
8037 #define UMCCH7_2_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
8038 #define UMCCH7_2_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
8039 #define UMCCH7_2_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
8040 #define UMCCH7_2_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
8041 #define UMCCH7_2_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
8042 #define UMCCH7_2_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
8043 #define UMCCH7_2_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
8044 #define UMCCH7_2_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
8045 #define UMCCH7_2_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
8046 #define UMCCH7_2_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
8047 //UMCCH7_2_PerfMonCtr5_Lo
8048 #define UMCCH7_2_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
8049 #define UMCCH7_2_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
8050 //UMCCH7_2_PerfMonCtr5_Hi
8051 #define UMCCH7_2_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
8052 #define UMCCH7_2_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
8053 #define UMCCH7_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
8054 #define UMCCH7_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
8055 #define UMCCH7_2_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
8056 #define UMCCH7_2_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
8057 #define UMCCH7_2_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8058 #define UMCCH7_2_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8059 //UMCCH7_2_PerfMonCtl6
8060 #define UMCCH7_2_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
8061 #define UMCCH7_2_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
8062 #define UMCCH7_2_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
8063 #define UMCCH7_2_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
8064 #define UMCCH7_2_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
8065 #define UMCCH7_2_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
8066 #define UMCCH7_2_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
8067 #define UMCCH7_2_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
8068 #define UMCCH7_2_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
8069 #define UMCCH7_2_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
8070 #define UMCCH7_2_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
8071 #define UMCCH7_2_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
8072 #define UMCCH7_2_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
8073 #define UMCCH7_2_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
8074 #define UMCCH7_2_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
8075 #define UMCCH7_2_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
8076 //UMCCH7_2_PerfMonCtr6_Lo
8077 #define UMCCH7_2_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
8078 #define UMCCH7_2_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
8079 //UMCCH7_2_PerfMonCtr6_Hi
8080 #define UMCCH7_2_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
8081 #define UMCCH7_2_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
8082 #define UMCCH7_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
8083 #define UMCCH7_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
8084 #define UMCCH7_2_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
8085 #define UMCCH7_2_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
8086 #define UMCCH7_2_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8087 #define UMCCH7_2_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8088 //UMCCH7_2_PerfMonCtl7
8089 #define UMCCH7_2_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
8090 #define UMCCH7_2_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
8091 #define UMCCH7_2_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
8092 #define UMCCH7_2_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
8093 #define UMCCH7_2_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
8094 #define UMCCH7_2_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
8095 #define UMCCH7_2_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
8096 #define UMCCH7_2_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
8097 #define UMCCH7_2_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
8098 #define UMCCH7_2_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
8099 #define UMCCH7_2_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
8100 #define UMCCH7_2_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
8101 #define UMCCH7_2_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
8102 #define UMCCH7_2_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
8103 #define UMCCH7_2_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
8104 #define UMCCH7_2_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
8105 //UMCCH7_2_PerfMonCtr7_Lo
8106 #define UMCCH7_2_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
8107 #define UMCCH7_2_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
8108 //UMCCH7_2_PerfMonCtr7_Hi
8109 #define UMCCH7_2_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
8110 #define UMCCH7_2_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
8111 #define UMCCH7_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
8112 #define UMCCH7_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
8113 #define UMCCH7_2_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
8114 #define UMCCH7_2_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
8115 #define UMCCH7_2_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8116 #define UMCCH7_2_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8117 //UMCCH7_2_PerfMonCtl8
8118 #define UMCCH7_2_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
8119 #define UMCCH7_2_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
8120 #define UMCCH7_2_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
8121 #define UMCCH7_2_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
8122 #define UMCCH7_2_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
8123 #define UMCCH7_2_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
8124 #define UMCCH7_2_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
8125 #define UMCCH7_2_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
8126 #define UMCCH7_2_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
8127 #define UMCCH7_2_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
8128 #define UMCCH7_2_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
8129 #define UMCCH7_2_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
8130 #define UMCCH7_2_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
8131 #define UMCCH7_2_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
8132 #define UMCCH7_2_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
8133 #define UMCCH7_2_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
8134 //UMCCH7_2_PerfMonCtr8_Lo
8135 #define UMCCH7_2_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
8136 #define UMCCH7_2_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
8137 //UMCCH7_2_PerfMonCtr8_Hi
8138 #define UMCCH7_2_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
8139 #define UMCCH7_2_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
8140 #define UMCCH7_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
8141 #define UMCCH7_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
8142 #define UMCCH7_2_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
8143 #define UMCCH7_2_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
8144 #define UMCCH7_2_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8145 #define UMCCH7_2_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8146 
8147 
8148 // addressBlock: umc_w_phy_umc3_umcch0_umcchdec
8149 //UMCCH0_3_BaseAddrCS0
8150 #define UMCCH0_3_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
8151 #define UMCCH0_3_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
8152 #define UMCCH0_3_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
8153 #define UMCCH0_3_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
8154 //UMCCH0_3_AddrMaskCS01
8155 #define UMCCH0_3_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
8156 #define UMCCH0_3_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
8157 //UMCCH0_3_AddrSelCS01
8158 #define UMCCH0_3_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
8159 #define UMCCH0_3_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
8160 #define UMCCH0_3_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
8161 #define UMCCH0_3_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
8162 #define UMCCH0_3_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
8163 #define UMCCH0_3_AddrSelCS01__RowLo__SHIFT                                                                    0x18
8164 #define UMCCH0_3_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
8165 #define UMCCH0_3_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
8166 #define UMCCH0_3_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
8167 #define UMCCH0_3_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
8168 #define UMCCH0_3_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
8169 #define UMCCH0_3_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
8170 #define UMCCH0_3_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
8171 #define UMCCH0_3_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
8172 //UMCCH0_3_AddrHashBank0
8173 #define UMCCH0_3_AddrHashBank0__XorEnable__SHIFT                                                              0x0
8174 #define UMCCH0_3_AddrHashBank0__ColXor__SHIFT                                                                 0x1
8175 #define UMCCH0_3_AddrHashBank0__RowXor__SHIFT                                                                 0xe
8176 #define UMCCH0_3_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
8177 #define UMCCH0_3_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
8178 #define UMCCH0_3_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
8179 //UMCCH0_3_AddrHashBank1
8180 #define UMCCH0_3_AddrHashBank1__XorEnable__SHIFT                                                              0x0
8181 #define UMCCH0_3_AddrHashBank1__ColXor__SHIFT                                                                 0x1
8182 #define UMCCH0_3_AddrHashBank1__RowXor__SHIFT                                                                 0xe
8183 #define UMCCH0_3_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
8184 #define UMCCH0_3_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
8185 #define UMCCH0_3_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
8186 //UMCCH0_3_AddrHashBank2
8187 #define UMCCH0_3_AddrHashBank2__XorEnable__SHIFT                                                              0x0
8188 #define UMCCH0_3_AddrHashBank2__ColXor__SHIFT                                                                 0x1
8189 #define UMCCH0_3_AddrHashBank2__RowXor__SHIFT                                                                 0xe
8190 #define UMCCH0_3_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
8191 #define UMCCH0_3_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
8192 #define UMCCH0_3_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
8193 //UMCCH0_3_AddrHashBank3
8194 #define UMCCH0_3_AddrHashBank3__XorEnable__SHIFT                                                              0x0
8195 #define UMCCH0_3_AddrHashBank3__ColXor__SHIFT                                                                 0x1
8196 #define UMCCH0_3_AddrHashBank3__RowXor__SHIFT                                                                 0xe
8197 #define UMCCH0_3_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
8198 #define UMCCH0_3_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
8199 #define UMCCH0_3_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
8200 //UMCCH0_3_AddrHashBank4
8201 #define UMCCH0_3_AddrHashBank4__XorEnable__SHIFT                                                              0x0
8202 #define UMCCH0_3_AddrHashBank4__ColXor__SHIFT                                                                 0x1
8203 #define UMCCH0_3_AddrHashBank4__RowXor__SHIFT                                                                 0xe
8204 #define UMCCH0_3_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
8205 #define UMCCH0_3_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
8206 #define UMCCH0_3_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
8207 //UMCCH0_3_AddrHashBank5
8208 #define UMCCH0_3_AddrHashBank5__XorEnable__SHIFT                                                              0x0
8209 #define UMCCH0_3_AddrHashBank5__ColXor__SHIFT                                                                 0x1
8210 #define UMCCH0_3_AddrHashBank5__RowXor__SHIFT                                                                 0xe
8211 #define UMCCH0_3_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
8212 #define UMCCH0_3_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
8213 #define UMCCH0_3_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
8214 //UMCCH0_3_EccErrCntSel
8215 #define UMCCH0_3_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
8216 #define UMCCH0_3_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
8217 #define UMCCH0_3_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
8218 #define UMCCH0_3_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
8219 #define UMCCH0_3_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
8220 #define UMCCH0_3_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
8221 //UMCCH0_3_EccErrCnt
8222 #define UMCCH0_3_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
8223 #define UMCCH0_3_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
8224 //UMCCH0_3_PerfMonCtlClk
8225 #define UMCCH0_3_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
8226 #define UMCCH0_3_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
8227 #define UMCCH0_3_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
8228 #define UMCCH0_3_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
8229 #define UMCCH0_3_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
8230 #define UMCCH0_3_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
8231 #define UMCCH0_3_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
8232 #define UMCCH0_3_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
8233 #define UMCCH0_3_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
8234 #define UMCCH0_3_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
8235 #define UMCCH0_3_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
8236 #define UMCCH0_3_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
8237 //UMCCH0_3_PerfMonCtrClk_Lo
8238 #define UMCCH0_3_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
8239 #define UMCCH0_3_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
8240 //UMCCH0_3_PerfMonCtrClk_Hi
8241 #define UMCCH0_3_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
8242 #define UMCCH0_3_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
8243 #define UMCCH0_3_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
8244 #define UMCCH0_3_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
8245 //UMCCH0_3_PerfMonCtl1
8246 #define UMCCH0_3_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
8247 #define UMCCH0_3_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
8248 #define UMCCH0_3_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
8249 #define UMCCH0_3_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
8250 #define UMCCH0_3_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
8251 #define UMCCH0_3_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
8252 #define UMCCH0_3_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
8253 #define UMCCH0_3_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
8254 #define UMCCH0_3_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
8255 #define UMCCH0_3_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
8256 #define UMCCH0_3_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
8257 #define UMCCH0_3_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
8258 #define UMCCH0_3_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
8259 #define UMCCH0_3_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
8260 #define UMCCH0_3_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
8261 #define UMCCH0_3_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
8262 //UMCCH0_3_PerfMonCtr1_Lo
8263 #define UMCCH0_3_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
8264 #define UMCCH0_3_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
8265 //UMCCH0_3_PerfMonCtr1_Hi
8266 #define UMCCH0_3_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
8267 #define UMCCH0_3_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
8268 #define UMCCH0_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
8269 #define UMCCH0_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
8270 #define UMCCH0_3_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
8271 #define UMCCH0_3_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
8272 #define UMCCH0_3_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8273 #define UMCCH0_3_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8274 //UMCCH0_3_PerfMonCtl2
8275 #define UMCCH0_3_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
8276 #define UMCCH0_3_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
8277 #define UMCCH0_3_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
8278 #define UMCCH0_3_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
8279 #define UMCCH0_3_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
8280 #define UMCCH0_3_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
8281 #define UMCCH0_3_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
8282 #define UMCCH0_3_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
8283 #define UMCCH0_3_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
8284 #define UMCCH0_3_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
8285 #define UMCCH0_3_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
8286 #define UMCCH0_3_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
8287 #define UMCCH0_3_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
8288 #define UMCCH0_3_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
8289 #define UMCCH0_3_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
8290 #define UMCCH0_3_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
8291 //UMCCH0_3_PerfMonCtr2_Lo
8292 #define UMCCH0_3_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
8293 #define UMCCH0_3_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
8294 //UMCCH0_3_PerfMonCtr2_Hi
8295 #define UMCCH0_3_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
8296 #define UMCCH0_3_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
8297 #define UMCCH0_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
8298 #define UMCCH0_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
8299 #define UMCCH0_3_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
8300 #define UMCCH0_3_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
8301 #define UMCCH0_3_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8302 #define UMCCH0_3_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8303 //UMCCH0_3_PerfMonCtl3
8304 #define UMCCH0_3_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
8305 #define UMCCH0_3_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
8306 #define UMCCH0_3_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
8307 #define UMCCH0_3_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
8308 #define UMCCH0_3_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
8309 #define UMCCH0_3_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
8310 #define UMCCH0_3_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
8311 #define UMCCH0_3_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
8312 #define UMCCH0_3_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
8313 #define UMCCH0_3_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
8314 #define UMCCH0_3_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
8315 #define UMCCH0_3_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
8316 #define UMCCH0_3_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
8317 #define UMCCH0_3_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
8318 #define UMCCH0_3_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
8319 #define UMCCH0_3_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
8320 //UMCCH0_3_PerfMonCtr3_Lo
8321 #define UMCCH0_3_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
8322 #define UMCCH0_3_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
8323 //UMCCH0_3_PerfMonCtr3_Hi
8324 #define UMCCH0_3_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
8325 #define UMCCH0_3_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
8326 #define UMCCH0_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
8327 #define UMCCH0_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
8328 #define UMCCH0_3_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
8329 #define UMCCH0_3_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
8330 #define UMCCH0_3_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8331 #define UMCCH0_3_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8332 //UMCCH0_3_PerfMonCtl4
8333 #define UMCCH0_3_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
8334 #define UMCCH0_3_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
8335 #define UMCCH0_3_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
8336 #define UMCCH0_3_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
8337 #define UMCCH0_3_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
8338 #define UMCCH0_3_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
8339 #define UMCCH0_3_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
8340 #define UMCCH0_3_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
8341 #define UMCCH0_3_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
8342 #define UMCCH0_3_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
8343 #define UMCCH0_3_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
8344 #define UMCCH0_3_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
8345 #define UMCCH0_3_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
8346 #define UMCCH0_3_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
8347 #define UMCCH0_3_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
8348 #define UMCCH0_3_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
8349 //UMCCH0_3_PerfMonCtr4_Lo
8350 #define UMCCH0_3_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
8351 #define UMCCH0_3_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
8352 //UMCCH0_3_PerfMonCtr4_Hi
8353 #define UMCCH0_3_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
8354 #define UMCCH0_3_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
8355 #define UMCCH0_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
8356 #define UMCCH0_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
8357 #define UMCCH0_3_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
8358 #define UMCCH0_3_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
8359 #define UMCCH0_3_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8360 #define UMCCH0_3_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8361 //UMCCH0_3_PerfMonCtl5
8362 #define UMCCH0_3_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
8363 #define UMCCH0_3_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
8364 #define UMCCH0_3_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
8365 #define UMCCH0_3_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
8366 #define UMCCH0_3_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
8367 #define UMCCH0_3_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
8368 #define UMCCH0_3_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
8369 #define UMCCH0_3_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
8370 #define UMCCH0_3_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
8371 #define UMCCH0_3_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
8372 #define UMCCH0_3_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
8373 #define UMCCH0_3_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
8374 #define UMCCH0_3_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
8375 #define UMCCH0_3_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
8376 #define UMCCH0_3_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
8377 #define UMCCH0_3_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
8378 //UMCCH0_3_PerfMonCtr5_Lo
8379 #define UMCCH0_3_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
8380 #define UMCCH0_3_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
8381 //UMCCH0_3_PerfMonCtr5_Hi
8382 #define UMCCH0_3_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
8383 #define UMCCH0_3_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
8384 #define UMCCH0_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
8385 #define UMCCH0_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
8386 #define UMCCH0_3_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
8387 #define UMCCH0_3_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
8388 #define UMCCH0_3_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8389 #define UMCCH0_3_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8390 //UMCCH0_3_PerfMonCtl6
8391 #define UMCCH0_3_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
8392 #define UMCCH0_3_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
8393 #define UMCCH0_3_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
8394 #define UMCCH0_3_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
8395 #define UMCCH0_3_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
8396 #define UMCCH0_3_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
8397 #define UMCCH0_3_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
8398 #define UMCCH0_3_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
8399 #define UMCCH0_3_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
8400 #define UMCCH0_3_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
8401 #define UMCCH0_3_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
8402 #define UMCCH0_3_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
8403 #define UMCCH0_3_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
8404 #define UMCCH0_3_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
8405 #define UMCCH0_3_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
8406 #define UMCCH0_3_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
8407 //UMCCH0_3_PerfMonCtr6_Lo
8408 #define UMCCH0_3_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
8409 #define UMCCH0_3_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
8410 //UMCCH0_3_PerfMonCtr6_Hi
8411 #define UMCCH0_3_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
8412 #define UMCCH0_3_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
8413 #define UMCCH0_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
8414 #define UMCCH0_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
8415 #define UMCCH0_3_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
8416 #define UMCCH0_3_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
8417 #define UMCCH0_3_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8418 #define UMCCH0_3_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8419 //UMCCH0_3_PerfMonCtl7
8420 #define UMCCH0_3_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
8421 #define UMCCH0_3_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
8422 #define UMCCH0_3_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
8423 #define UMCCH0_3_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
8424 #define UMCCH0_3_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
8425 #define UMCCH0_3_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
8426 #define UMCCH0_3_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
8427 #define UMCCH0_3_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
8428 #define UMCCH0_3_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
8429 #define UMCCH0_3_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
8430 #define UMCCH0_3_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
8431 #define UMCCH0_3_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
8432 #define UMCCH0_3_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
8433 #define UMCCH0_3_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
8434 #define UMCCH0_3_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
8435 #define UMCCH0_3_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
8436 //UMCCH0_3_PerfMonCtr7_Lo
8437 #define UMCCH0_3_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
8438 #define UMCCH0_3_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
8439 //UMCCH0_3_PerfMonCtr7_Hi
8440 #define UMCCH0_3_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
8441 #define UMCCH0_3_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
8442 #define UMCCH0_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
8443 #define UMCCH0_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
8444 #define UMCCH0_3_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
8445 #define UMCCH0_3_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
8446 #define UMCCH0_3_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8447 #define UMCCH0_3_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8448 //UMCCH0_3_PerfMonCtl8
8449 #define UMCCH0_3_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
8450 #define UMCCH0_3_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
8451 #define UMCCH0_3_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
8452 #define UMCCH0_3_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
8453 #define UMCCH0_3_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
8454 #define UMCCH0_3_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
8455 #define UMCCH0_3_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
8456 #define UMCCH0_3_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
8457 #define UMCCH0_3_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
8458 #define UMCCH0_3_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
8459 #define UMCCH0_3_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
8460 #define UMCCH0_3_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
8461 #define UMCCH0_3_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
8462 #define UMCCH0_3_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
8463 #define UMCCH0_3_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
8464 #define UMCCH0_3_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
8465 //UMCCH0_3_PerfMonCtr8_Lo
8466 #define UMCCH0_3_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
8467 #define UMCCH0_3_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
8468 //UMCCH0_3_PerfMonCtr8_Hi
8469 #define UMCCH0_3_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
8470 #define UMCCH0_3_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
8471 #define UMCCH0_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
8472 #define UMCCH0_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
8473 #define UMCCH0_3_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
8474 #define UMCCH0_3_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
8475 #define UMCCH0_3_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8476 #define UMCCH0_3_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8477 
8478 
8479 // addressBlock: umc_w_phy_umc3_umcch1_umcchdec
8480 //UMCCH1_3_BaseAddrCS0
8481 #define UMCCH1_3_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
8482 #define UMCCH1_3_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
8483 #define UMCCH1_3_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
8484 #define UMCCH1_3_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
8485 //UMCCH1_3_AddrMaskCS01
8486 #define UMCCH1_3_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
8487 #define UMCCH1_3_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
8488 //UMCCH1_3_AddrSelCS01
8489 #define UMCCH1_3_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
8490 #define UMCCH1_3_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
8491 #define UMCCH1_3_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
8492 #define UMCCH1_3_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
8493 #define UMCCH1_3_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
8494 #define UMCCH1_3_AddrSelCS01__RowLo__SHIFT                                                                    0x18
8495 #define UMCCH1_3_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
8496 #define UMCCH1_3_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
8497 #define UMCCH1_3_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
8498 #define UMCCH1_3_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
8499 #define UMCCH1_3_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
8500 #define UMCCH1_3_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
8501 #define UMCCH1_3_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
8502 #define UMCCH1_3_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
8503 //UMCCH1_3_AddrHashBank0
8504 #define UMCCH1_3_AddrHashBank0__XorEnable__SHIFT                                                              0x0
8505 #define UMCCH1_3_AddrHashBank0__ColXor__SHIFT                                                                 0x1
8506 #define UMCCH1_3_AddrHashBank0__RowXor__SHIFT                                                                 0xe
8507 #define UMCCH1_3_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
8508 #define UMCCH1_3_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
8509 #define UMCCH1_3_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
8510 //UMCCH1_3_AddrHashBank1
8511 #define UMCCH1_3_AddrHashBank1__XorEnable__SHIFT                                                              0x0
8512 #define UMCCH1_3_AddrHashBank1__ColXor__SHIFT                                                                 0x1
8513 #define UMCCH1_3_AddrHashBank1__RowXor__SHIFT                                                                 0xe
8514 #define UMCCH1_3_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
8515 #define UMCCH1_3_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
8516 #define UMCCH1_3_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
8517 //UMCCH1_3_AddrHashBank2
8518 #define UMCCH1_3_AddrHashBank2__XorEnable__SHIFT                                                              0x0
8519 #define UMCCH1_3_AddrHashBank2__ColXor__SHIFT                                                                 0x1
8520 #define UMCCH1_3_AddrHashBank2__RowXor__SHIFT                                                                 0xe
8521 #define UMCCH1_3_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
8522 #define UMCCH1_3_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
8523 #define UMCCH1_3_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
8524 //UMCCH1_3_AddrHashBank3
8525 #define UMCCH1_3_AddrHashBank3__XorEnable__SHIFT                                                              0x0
8526 #define UMCCH1_3_AddrHashBank3__ColXor__SHIFT                                                                 0x1
8527 #define UMCCH1_3_AddrHashBank3__RowXor__SHIFT                                                                 0xe
8528 #define UMCCH1_3_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
8529 #define UMCCH1_3_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
8530 #define UMCCH1_3_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
8531 //UMCCH1_3_AddrHashBank4
8532 #define UMCCH1_3_AddrHashBank4__XorEnable__SHIFT                                                              0x0
8533 #define UMCCH1_3_AddrHashBank4__ColXor__SHIFT                                                                 0x1
8534 #define UMCCH1_3_AddrHashBank4__RowXor__SHIFT                                                                 0xe
8535 #define UMCCH1_3_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
8536 #define UMCCH1_3_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
8537 #define UMCCH1_3_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
8538 //UMCCH1_3_AddrHashBank5
8539 #define UMCCH1_3_AddrHashBank5__XorEnable__SHIFT                                                              0x0
8540 #define UMCCH1_3_AddrHashBank5__ColXor__SHIFT                                                                 0x1
8541 #define UMCCH1_3_AddrHashBank5__RowXor__SHIFT                                                                 0xe
8542 #define UMCCH1_3_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
8543 #define UMCCH1_3_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
8544 #define UMCCH1_3_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
8545 //UMCCH1_3_EccErrCntSel
8546 #define UMCCH1_3_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
8547 #define UMCCH1_3_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
8548 #define UMCCH1_3_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
8549 #define UMCCH1_3_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
8550 #define UMCCH1_3_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
8551 #define UMCCH1_3_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
8552 //UMCCH1_3_EccErrCnt
8553 #define UMCCH1_3_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
8554 #define UMCCH1_3_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
8555 //UMCCH1_3_PerfMonCtlClk
8556 #define UMCCH1_3_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
8557 #define UMCCH1_3_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
8558 #define UMCCH1_3_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
8559 #define UMCCH1_3_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
8560 #define UMCCH1_3_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
8561 #define UMCCH1_3_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
8562 #define UMCCH1_3_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
8563 #define UMCCH1_3_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
8564 #define UMCCH1_3_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
8565 #define UMCCH1_3_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
8566 #define UMCCH1_3_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
8567 #define UMCCH1_3_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
8568 //UMCCH1_3_PerfMonCtrClk_Lo
8569 #define UMCCH1_3_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
8570 #define UMCCH1_3_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
8571 //UMCCH1_3_PerfMonCtrClk_Hi
8572 #define UMCCH1_3_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
8573 #define UMCCH1_3_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
8574 #define UMCCH1_3_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
8575 #define UMCCH1_3_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
8576 //UMCCH1_3_PerfMonCtl1
8577 #define UMCCH1_3_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
8578 #define UMCCH1_3_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
8579 #define UMCCH1_3_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
8580 #define UMCCH1_3_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
8581 #define UMCCH1_3_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
8582 #define UMCCH1_3_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
8583 #define UMCCH1_3_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
8584 #define UMCCH1_3_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
8585 #define UMCCH1_3_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
8586 #define UMCCH1_3_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
8587 #define UMCCH1_3_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
8588 #define UMCCH1_3_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
8589 #define UMCCH1_3_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
8590 #define UMCCH1_3_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
8591 #define UMCCH1_3_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
8592 #define UMCCH1_3_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
8593 //UMCCH1_3_PerfMonCtr1_Lo
8594 #define UMCCH1_3_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
8595 #define UMCCH1_3_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
8596 //UMCCH1_3_PerfMonCtr1_Hi
8597 #define UMCCH1_3_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
8598 #define UMCCH1_3_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
8599 #define UMCCH1_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
8600 #define UMCCH1_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
8601 #define UMCCH1_3_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
8602 #define UMCCH1_3_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
8603 #define UMCCH1_3_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8604 #define UMCCH1_3_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8605 //UMCCH1_3_PerfMonCtl2
8606 #define UMCCH1_3_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
8607 #define UMCCH1_3_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
8608 #define UMCCH1_3_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
8609 #define UMCCH1_3_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
8610 #define UMCCH1_3_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
8611 #define UMCCH1_3_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
8612 #define UMCCH1_3_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
8613 #define UMCCH1_3_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
8614 #define UMCCH1_3_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
8615 #define UMCCH1_3_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
8616 #define UMCCH1_3_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
8617 #define UMCCH1_3_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
8618 #define UMCCH1_3_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
8619 #define UMCCH1_3_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
8620 #define UMCCH1_3_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
8621 #define UMCCH1_3_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
8622 //UMCCH1_3_PerfMonCtr2_Lo
8623 #define UMCCH1_3_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
8624 #define UMCCH1_3_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
8625 //UMCCH1_3_PerfMonCtr2_Hi
8626 #define UMCCH1_3_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
8627 #define UMCCH1_3_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
8628 #define UMCCH1_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
8629 #define UMCCH1_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
8630 #define UMCCH1_3_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
8631 #define UMCCH1_3_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
8632 #define UMCCH1_3_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8633 #define UMCCH1_3_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8634 //UMCCH1_3_PerfMonCtl3
8635 #define UMCCH1_3_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
8636 #define UMCCH1_3_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
8637 #define UMCCH1_3_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
8638 #define UMCCH1_3_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
8639 #define UMCCH1_3_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
8640 #define UMCCH1_3_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
8641 #define UMCCH1_3_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
8642 #define UMCCH1_3_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
8643 #define UMCCH1_3_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
8644 #define UMCCH1_3_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
8645 #define UMCCH1_3_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
8646 #define UMCCH1_3_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
8647 #define UMCCH1_3_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
8648 #define UMCCH1_3_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
8649 #define UMCCH1_3_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
8650 #define UMCCH1_3_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
8651 //UMCCH1_3_PerfMonCtr3_Lo
8652 #define UMCCH1_3_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
8653 #define UMCCH1_3_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
8654 //UMCCH1_3_PerfMonCtr3_Hi
8655 #define UMCCH1_3_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
8656 #define UMCCH1_3_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
8657 #define UMCCH1_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
8658 #define UMCCH1_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
8659 #define UMCCH1_3_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
8660 #define UMCCH1_3_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
8661 #define UMCCH1_3_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8662 #define UMCCH1_3_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8663 //UMCCH1_3_PerfMonCtl4
8664 #define UMCCH1_3_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
8665 #define UMCCH1_3_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
8666 #define UMCCH1_3_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
8667 #define UMCCH1_3_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
8668 #define UMCCH1_3_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
8669 #define UMCCH1_3_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
8670 #define UMCCH1_3_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
8671 #define UMCCH1_3_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
8672 #define UMCCH1_3_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
8673 #define UMCCH1_3_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
8674 #define UMCCH1_3_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
8675 #define UMCCH1_3_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
8676 #define UMCCH1_3_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
8677 #define UMCCH1_3_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
8678 #define UMCCH1_3_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
8679 #define UMCCH1_3_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
8680 //UMCCH1_3_PerfMonCtr4_Lo
8681 #define UMCCH1_3_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
8682 #define UMCCH1_3_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
8683 //UMCCH1_3_PerfMonCtr4_Hi
8684 #define UMCCH1_3_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
8685 #define UMCCH1_3_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
8686 #define UMCCH1_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
8687 #define UMCCH1_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
8688 #define UMCCH1_3_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
8689 #define UMCCH1_3_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
8690 #define UMCCH1_3_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8691 #define UMCCH1_3_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8692 //UMCCH1_3_PerfMonCtl5
8693 #define UMCCH1_3_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
8694 #define UMCCH1_3_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
8695 #define UMCCH1_3_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
8696 #define UMCCH1_3_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
8697 #define UMCCH1_3_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
8698 #define UMCCH1_3_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
8699 #define UMCCH1_3_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
8700 #define UMCCH1_3_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
8701 #define UMCCH1_3_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
8702 #define UMCCH1_3_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
8703 #define UMCCH1_3_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
8704 #define UMCCH1_3_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
8705 #define UMCCH1_3_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
8706 #define UMCCH1_3_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
8707 #define UMCCH1_3_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
8708 #define UMCCH1_3_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
8709 //UMCCH1_3_PerfMonCtr5_Lo
8710 #define UMCCH1_3_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
8711 #define UMCCH1_3_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
8712 //UMCCH1_3_PerfMonCtr5_Hi
8713 #define UMCCH1_3_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
8714 #define UMCCH1_3_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
8715 #define UMCCH1_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
8716 #define UMCCH1_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
8717 #define UMCCH1_3_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
8718 #define UMCCH1_3_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
8719 #define UMCCH1_3_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8720 #define UMCCH1_3_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8721 //UMCCH1_3_PerfMonCtl6
8722 #define UMCCH1_3_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
8723 #define UMCCH1_3_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
8724 #define UMCCH1_3_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
8725 #define UMCCH1_3_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
8726 #define UMCCH1_3_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
8727 #define UMCCH1_3_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
8728 #define UMCCH1_3_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
8729 #define UMCCH1_3_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
8730 #define UMCCH1_3_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
8731 #define UMCCH1_3_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
8732 #define UMCCH1_3_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
8733 #define UMCCH1_3_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
8734 #define UMCCH1_3_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
8735 #define UMCCH1_3_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
8736 #define UMCCH1_3_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
8737 #define UMCCH1_3_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
8738 //UMCCH1_3_PerfMonCtr6_Lo
8739 #define UMCCH1_3_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
8740 #define UMCCH1_3_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
8741 //UMCCH1_3_PerfMonCtr6_Hi
8742 #define UMCCH1_3_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
8743 #define UMCCH1_3_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
8744 #define UMCCH1_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
8745 #define UMCCH1_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
8746 #define UMCCH1_3_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
8747 #define UMCCH1_3_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
8748 #define UMCCH1_3_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8749 #define UMCCH1_3_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8750 //UMCCH1_3_PerfMonCtl7
8751 #define UMCCH1_3_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
8752 #define UMCCH1_3_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
8753 #define UMCCH1_3_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
8754 #define UMCCH1_3_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
8755 #define UMCCH1_3_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
8756 #define UMCCH1_3_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
8757 #define UMCCH1_3_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
8758 #define UMCCH1_3_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
8759 #define UMCCH1_3_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
8760 #define UMCCH1_3_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
8761 #define UMCCH1_3_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
8762 #define UMCCH1_3_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
8763 #define UMCCH1_3_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
8764 #define UMCCH1_3_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
8765 #define UMCCH1_3_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
8766 #define UMCCH1_3_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
8767 //UMCCH1_3_PerfMonCtr7_Lo
8768 #define UMCCH1_3_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
8769 #define UMCCH1_3_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
8770 //UMCCH1_3_PerfMonCtr7_Hi
8771 #define UMCCH1_3_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
8772 #define UMCCH1_3_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
8773 #define UMCCH1_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
8774 #define UMCCH1_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
8775 #define UMCCH1_3_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
8776 #define UMCCH1_3_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
8777 #define UMCCH1_3_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8778 #define UMCCH1_3_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8779 //UMCCH1_3_PerfMonCtl8
8780 #define UMCCH1_3_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
8781 #define UMCCH1_3_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
8782 #define UMCCH1_3_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
8783 #define UMCCH1_3_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
8784 #define UMCCH1_3_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
8785 #define UMCCH1_3_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
8786 #define UMCCH1_3_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
8787 #define UMCCH1_3_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
8788 #define UMCCH1_3_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
8789 #define UMCCH1_3_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
8790 #define UMCCH1_3_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
8791 #define UMCCH1_3_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
8792 #define UMCCH1_3_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
8793 #define UMCCH1_3_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
8794 #define UMCCH1_3_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
8795 #define UMCCH1_3_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
8796 //UMCCH1_3_PerfMonCtr8_Lo
8797 #define UMCCH1_3_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
8798 #define UMCCH1_3_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
8799 //UMCCH1_3_PerfMonCtr8_Hi
8800 #define UMCCH1_3_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
8801 #define UMCCH1_3_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
8802 #define UMCCH1_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
8803 #define UMCCH1_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
8804 #define UMCCH1_3_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
8805 #define UMCCH1_3_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
8806 #define UMCCH1_3_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8807 #define UMCCH1_3_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8808 
8809 
8810 // addressBlock: umc_w_phy_umc3_umcch2_umcchdec
8811 //UMCCH2_3_BaseAddrCS0
8812 #define UMCCH2_3_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
8813 #define UMCCH2_3_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
8814 #define UMCCH2_3_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
8815 #define UMCCH2_3_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
8816 //UMCCH2_3_AddrMaskCS01
8817 #define UMCCH2_3_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
8818 #define UMCCH2_3_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
8819 //UMCCH2_3_AddrSelCS01
8820 #define UMCCH2_3_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
8821 #define UMCCH2_3_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
8822 #define UMCCH2_3_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
8823 #define UMCCH2_3_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
8824 #define UMCCH2_3_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
8825 #define UMCCH2_3_AddrSelCS01__RowLo__SHIFT                                                                    0x18
8826 #define UMCCH2_3_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
8827 #define UMCCH2_3_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
8828 #define UMCCH2_3_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
8829 #define UMCCH2_3_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
8830 #define UMCCH2_3_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
8831 #define UMCCH2_3_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
8832 #define UMCCH2_3_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
8833 #define UMCCH2_3_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
8834 //UMCCH2_3_AddrHashBank0
8835 #define UMCCH2_3_AddrHashBank0__XorEnable__SHIFT                                                              0x0
8836 #define UMCCH2_3_AddrHashBank0__ColXor__SHIFT                                                                 0x1
8837 #define UMCCH2_3_AddrHashBank0__RowXor__SHIFT                                                                 0xe
8838 #define UMCCH2_3_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
8839 #define UMCCH2_3_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
8840 #define UMCCH2_3_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
8841 //UMCCH2_3_AddrHashBank1
8842 #define UMCCH2_3_AddrHashBank1__XorEnable__SHIFT                                                              0x0
8843 #define UMCCH2_3_AddrHashBank1__ColXor__SHIFT                                                                 0x1
8844 #define UMCCH2_3_AddrHashBank1__RowXor__SHIFT                                                                 0xe
8845 #define UMCCH2_3_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
8846 #define UMCCH2_3_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
8847 #define UMCCH2_3_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
8848 //UMCCH2_3_AddrHashBank2
8849 #define UMCCH2_3_AddrHashBank2__XorEnable__SHIFT                                                              0x0
8850 #define UMCCH2_3_AddrHashBank2__ColXor__SHIFT                                                                 0x1
8851 #define UMCCH2_3_AddrHashBank2__RowXor__SHIFT                                                                 0xe
8852 #define UMCCH2_3_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
8853 #define UMCCH2_3_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
8854 #define UMCCH2_3_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
8855 //UMCCH2_3_AddrHashBank3
8856 #define UMCCH2_3_AddrHashBank3__XorEnable__SHIFT                                                              0x0
8857 #define UMCCH2_3_AddrHashBank3__ColXor__SHIFT                                                                 0x1
8858 #define UMCCH2_3_AddrHashBank3__RowXor__SHIFT                                                                 0xe
8859 #define UMCCH2_3_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
8860 #define UMCCH2_3_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
8861 #define UMCCH2_3_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
8862 //UMCCH2_3_AddrHashBank4
8863 #define UMCCH2_3_AddrHashBank4__XorEnable__SHIFT                                                              0x0
8864 #define UMCCH2_3_AddrHashBank4__ColXor__SHIFT                                                                 0x1
8865 #define UMCCH2_3_AddrHashBank4__RowXor__SHIFT                                                                 0xe
8866 #define UMCCH2_3_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
8867 #define UMCCH2_3_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
8868 #define UMCCH2_3_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
8869 //UMCCH2_3_AddrHashBank5
8870 #define UMCCH2_3_AddrHashBank5__XorEnable__SHIFT                                                              0x0
8871 #define UMCCH2_3_AddrHashBank5__ColXor__SHIFT                                                                 0x1
8872 #define UMCCH2_3_AddrHashBank5__RowXor__SHIFT                                                                 0xe
8873 #define UMCCH2_3_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
8874 #define UMCCH2_3_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
8875 #define UMCCH2_3_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
8876 //UMCCH2_3_EccErrCntSel
8877 #define UMCCH2_3_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
8878 #define UMCCH2_3_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
8879 #define UMCCH2_3_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
8880 #define UMCCH2_3_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
8881 #define UMCCH2_3_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
8882 #define UMCCH2_3_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
8883 //UMCCH2_3_EccErrCnt
8884 #define UMCCH2_3_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
8885 #define UMCCH2_3_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
8886 //UMCCH2_3_PerfMonCtlClk
8887 #define UMCCH2_3_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
8888 #define UMCCH2_3_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
8889 #define UMCCH2_3_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
8890 #define UMCCH2_3_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
8891 #define UMCCH2_3_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
8892 #define UMCCH2_3_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
8893 #define UMCCH2_3_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
8894 #define UMCCH2_3_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
8895 #define UMCCH2_3_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
8896 #define UMCCH2_3_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
8897 #define UMCCH2_3_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
8898 #define UMCCH2_3_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
8899 //UMCCH2_3_PerfMonCtrClk_Lo
8900 #define UMCCH2_3_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
8901 #define UMCCH2_3_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
8902 //UMCCH2_3_PerfMonCtrClk_Hi
8903 #define UMCCH2_3_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
8904 #define UMCCH2_3_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
8905 #define UMCCH2_3_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
8906 #define UMCCH2_3_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
8907 //UMCCH2_3_PerfMonCtl1
8908 #define UMCCH2_3_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
8909 #define UMCCH2_3_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
8910 #define UMCCH2_3_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
8911 #define UMCCH2_3_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
8912 #define UMCCH2_3_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
8913 #define UMCCH2_3_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
8914 #define UMCCH2_3_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
8915 #define UMCCH2_3_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
8916 #define UMCCH2_3_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
8917 #define UMCCH2_3_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
8918 #define UMCCH2_3_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
8919 #define UMCCH2_3_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
8920 #define UMCCH2_3_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
8921 #define UMCCH2_3_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
8922 #define UMCCH2_3_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
8923 #define UMCCH2_3_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
8924 //UMCCH2_3_PerfMonCtr1_Lo
8925 #define UMCCH2_3_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
8926 #define UMCCH2_3_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
8927 //UMCCH2_3_PerfMonCtr1_Hi
8928 #define UMCCH2_3_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
8929 #define UMCCH2_3_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
8930 #define UMCCH2_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
8931 #define UMCCH2_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
8932 #define UMCCH2_3_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
8933 #define UMCCH2_3_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
8934 #define UMCCH2_3_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8935 #define UMCCH2_3_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8936 //UMCCH2_3_PerfMonCtl2
8937 #define UMCCH2_3_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
8938 #define UMCCH2_3_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
8939 #define UMCCH2_3_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
8940 #define UMCCH2_3_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
8941 #define UMCCH2_3_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
8942 #define UMCCH2_3_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
8943 #define UMCCH2_3_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
8944 #define UMCCH2_3_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
8945 #define UMCCH2_3_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
8946 #define UMCCH2_3_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
8947 #define UMCCH2_3_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
8948 #define UMCCH2_3_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
8949 #define UMCCH2_3_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
8950 #define UMCCH2_3_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
8951 #define UMCCH2_3_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
8952 #define UMCCH2_3_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
8953 //UMCCH2_3_PerfMonCtr2_Lo
8954 #define UMCCH2_3_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
8955 #define UMCCH2_3_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
8956 //UMCCH2_3_PerfMonCtr2_Hi
8957 #define UMCCH2_3_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
8958 #define UMCCH2_3_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
8959 #define UMCCH2_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
8960 #define UMCCH2_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
8961 #define UMCCH2_3_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
8962 #define UMCCH2_3_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
8963 #define UMCCH2_3_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8964 #define UMCCH2_3_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8965 //UMCCH2_3_PerfMonCtl3
8966 #define UMCCH2_3_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
8967 #define UMCCH2_3_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
8968 #define UMCCH2_3_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
8969 #define UMCCH2_3_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
8970 #define UMCCH2_3_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
8971 #define UMCCH2_3_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
8972 #define UMCCH2_3_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
8973 #define UMCCH2_3_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
8974 #define UMCCH2_3_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
8975 #define UMCCH2_3_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
8976 #define UMCCH2_3_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
8977 #define UMCCH2_3_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
8978 #define UMCCH2_3_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
8979 #define UMCCH2_3_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
8980 #define UMCCH2_3_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
8981 #define UMCCH2_3_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
8982 //UMCCH2_3_PerfMonCtr3_Lo
8983 #define UMCCH2_3_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
8984 #define UMCCH2_3_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
8985 //UMCCH2_3_PerfMonCtr3_Hi
8986 #define UMCCH2_3_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
8987 #define UMCCH2_3_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
8988 #define UMCCH2_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
8989 #define UMCCH2_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
8990 #define UMCCH2_3_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
8991 #define UMCCH2_3_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
8992 #define UMCCH2_3_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
8993 #define UMCCH2_3_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
8994 //UMCCH2_3_PerfMonCtl4
8995 #define UMCCH2_3_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
8996 #define UMCCH2_3_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
8997 #define UMCCH2_3_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
8998 #define UMCCH2_3_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
8999 #define UMCCH2_3_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
9000 #define UMCCH2_3_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
9001 #define UMCCH2_3_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
9002 #define UMCCH2_3_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
9003 #define UMCCH2_3_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
9004 #define UMCCH2_3_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
9005 #define UMCCH2_3_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
9006 #define UMCCH2_3_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
9007 #define UMCCH2_3_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
9008 #define UMCCH2_3_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
9009 #define UMCCH2_3_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
9010 #define UMCCH2_3_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
9011 //UMCCH2_3_PerfMonCtr4_Lo
9012 #define UMCCH2_3_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
9013 #define UMCCH2_3_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
9014 //UMCCH2_3_PerfMonCtr4_Hi
9015 #define UMCCH2_3_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
9016 #define UMCCH2_3_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
9017 #define UMCCH2_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
9018 #define UMCCH2_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
9019 #define UMCCH2_3_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
9020 #define UMCCH2_3_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
9021 #define UMCCH2_3_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9022 #define UMCCH2_3_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9023 //UMCCH2_3_PerfMonCtl5
9024 #define UMCCH2_3_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
9025 #define UMCCH2_3_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
9026 #define UMCCH2_3_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
9027 #define UMCCH2_3_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
9028 #define UMCCH2_3_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
9029 #define UMCCH2_3_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
9030 #define UMCCH2_3_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
9031 #define UMCCH2_3_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
9032 #define UMCCH2_3_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
9033 #define UMCCH2_3_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
9034 #define UMCCH2_3_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
9035 #define UMCCH2_3_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
9036 #define UMCCH2_3_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
9037 #define UMCCH2_3_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
9038 #define UMCCH2_3_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
9039 #define UMCCH2_3_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
9040 //UMCCH2_3_PerfMonCtr5_Lo
9041 #define UMCCH2_3_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
9042 #define UMCCH2_3_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
9043 //UMCCH2_3_PerfMonCtr5_Hi
9044 #define UMCCH2_3_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
9045 #define UMCCH2_3_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
9046 #define UMCCH2_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
9047 #define UMCCH2_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
9048 #define UMCCH2_3_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
9049 #define UMCCH2_3_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
9050 #define UMCCH2_3_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9051 #define UMCCH2_3_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9052 //UMCCH2_3_PerfMonCtl6
9053 #define UMCCH2_3_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
9054 #define UMCCH2_3_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
9055 #define UMCCH2_3_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
9056 #define UMCCH2_3_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
9057 #define UMCCH2_3_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
9058 #define UMCCH2_3_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
9059 #define UMCCH2_3_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
9060 #define UMCCH2_3_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
9061 #define UMCCH2_3_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
9062 #define UMCCH2_3_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
9063 #define UMCCH2_3_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
9064 #define UMCCH2_3_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
9065 #define UMCCH2_3_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
9066 #define UMCCH2_3_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
9067 #define UMCCH2_3_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
9068 #define UMCCH2_3_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
9069 //UMCCH2_3_PerfMonCtr6_Lo
9070 #define UMCCH2_3_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
9071 #define UMCCH2_3_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
9072 //UMCCH2_3_PerfMonCtr6_Hi
9073 #define UMCCH2_3_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
9074 #define UMCCH2_3_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
9075 #define UMCCH2_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
9076 #define UMCCH2_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
9077 #define UMCCH2_3_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
9078 #define UMCCH2_3_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
9079 #define UMCCH2_3_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9080 #define UMCCH2_3_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9081 //UMCCH2_3_PerfMonCtl7
9082 #define UMCCH2_3_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
9083 #define UMCCH2_3_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
9084 #define UMCCH2_3_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
9085 #define UMCCH2_3_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
9086 #define UMCCH2_3_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
9087 #define UMCCH2_3_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
9088 #define UMCCH2_3_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
9089 #define UMCCH2_3_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
9090 #define UMCCH2_3_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
9091 #define UMCCH2_3_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
9092 #define UMCCH2_3_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
9093 #define UMCCH2_3_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
9094 #define UMCCH2_3_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
9095 #define UMCCH2_3_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
9096 #define UMCCH2_3_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
9097 #define UMCCH2_3_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
9098 //UMCCH2_3_PerfMonCtr7_Lo
9099 #define UMCCH2_3_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
9100 #define UMCCH2_3_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
9101 //UMCCH2_3_PerfMonCtr7_Hi
9102 #define UMCCH2_3_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
9103 #define UMCCH2_3_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
9104 #define UMCCH2_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
9105 #define UMCCH2_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
9106 #define UMCCH2_3_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
9107 #define UMCCH2_3_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
9108 #define UMCCH2_3_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9109 #define UMCCH2_3_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9110 //UMCCH2_3_PerfMonCtl8
9111 #define UMCCH2_3_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
9112 #define UMCCH2_3_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
9113 #define UMCCH2_3_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
9114 #define UMCCH2_3_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
9115 #define UMCCH2_3_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
9116 #define UMCCH2_3_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
9117 #define UMCCH2_3_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
9118 #define UMCCH2_3_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
9119 #define UMCCH2_3_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
9120 #define UMCCH2_3_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
9121 #define UMCCH2_3_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
9122 #define UMCCH2_3_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
9123 #define UMCCH2_3_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
9124 #define UMCCH2_3_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
9125 #define UMCCH2_3_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
9126 #define UMCCH2_3_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
9127 //UMCCH2_3_PerfMonCtr8_Lo
9128 #define UMCCH2_3_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
9129 #define UMCCH2_3_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
9130 //UMCCH2_3_PerfMonCtr8_Hi
9131 #define UMCCH2_3_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
9132 #define UMCCH2_3_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
9133 #define UMCCH2_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
9134 #define UMCCH2_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
9135 #define UMCCH2_3_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
9136 #define UMCCH2_3_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
9137 #define UMCCH2_3_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9138 #define UMCCH2_3_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9139 
9140 
9141 // addressBlock: umc_w_phy_umc3_umcch3_umcchdec
9142 //UMCCH3_3_BaseAddrCS0
9143 #define UMCCH3_3_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
9144 #define UMCCH3_3_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
9145 #define UMCCH3_3_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
9146 #define UMCCH3_3_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
9147 //UMCCH3_3_AddrMaskCS01
9148 #define UMCCH3_3_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
9149 #define UMCCH3_3_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
9150 //UMCCH3_3_AddrSelCS01
9151 #define UMCCH3_3_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
9152 #define UMCCH3_3_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
9153 #define UMCCH3_3_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
9154 #define UMCCH3_3_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
9155 #define UMCCH3_3_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
9156 #define UMCCH3_3_AddrSelCS01__RowLo__SHIFT                                                                    0x18
9157 #define UMCCH3_3_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
9158 #define UMCCH3_3_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
9159 #define UMCCH3_3_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
9160 #define UMCCH3_3_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
9161 #define UMCCH3_3_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
9162 #define UMCCH3_3_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
9163 #define UMCCH3_3_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
9164 #define UMCCH3_3_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
9165 //UMCCH3_3_AddrHashBank0
9166 #define UMCCH3_3_AddrHashBank0__XorEnable__SHIFT                                                              0x0
9167 #define UMCCH3_3_AddrHashBank0__ColXor__SHIFT                                                                 0x1
9168 #define UMCCH3_3_AddrHashBank0__RowXor__SHIFT                                                                 0xe
9169 #define UMCCH3_3_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
9170 #define UMCCH3_3_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
9171 #define UMCCH3_3_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
9172 //UMCCH3_3_AddrHashBank1
9173 #define UMCCH3_3_AddrHashBank1__XorEnable__SHIFT                                                              0x0
9174 #define UMCCH3_3_AddrHashBank1__ColXor__SHIFT                                                                 0x1
9175 #define UMCCH3_3_AddrHashBank1__RowXor__SHIFT                                                                 0xe
9176 #define UMCCH3_3_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
9177 #define UMCCH3_3_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
9178 #define UMCCH3_3_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
9179 //UMCCH3_3_AddrHashBank2
9180 #define UMCCH3_3_AddrHashBank2__XorEnable__SHIFT                                                              0x0
9181 #define UMCCH3_3_AddrHashBank2__ColXor__SHIFT                                                                 0x1
9182 #define UMCCH3_3_AddrHashBank2__RowXor__SHIFT                                                                 0xe
9183 #define UMCCH3_3_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
9184 #define UMCCH3_3_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
9185 #define UMCCH3_3_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
9186 //UMCCH3_3_AddrHashBank3
9187 #define UMCCH3_3_AddrHashBank3__XorEnable__SHIFT                                                              0x0
9188 #define UMCCH3_3_AddrHashBank3__ColXor__SHIFT                                                                 0x1
9189 #define UMCCH3_3_AddrHashBank3__RowXor__SHIFT                                                                 0xe
9190 #define UMCCH3_3_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
9191 #define UMCCH3_3_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
9192 #define UMCCH3_3_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
9193 //UMCCH3_3_AddrHashBank4
9194 #define UMCCH3_3_AddrHashBank4__XorEnable__SHIFT                                                              0x0
9195 #define UMCCH3_3_AddrHashBank4__ColXor__SHIFT                                                                 0x1
9196 #define UMCCH3_3_AddrHashBank4__RowXor__SHIFT                                                                 0xe
9197 #define UMCCH3_3_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
9198 #define UMCCH3_3_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
9199 #define UMCCH3_3_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
9200 //UMCCH3_3_AddrHashBank5
9201 #define UMCCH3_3_AddrHashBank5__XorEnable__SHIFT                                                              0x0
9202 #define UMCCH3_3_AddrHashBank5__ColXor__SHIFT                                                                 0x1
9203 #define UMCCH3_3_AddrHashBank5__RowXor__SHIFT                                                                 0xe
9204 #define UMCCH3_3_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
9205 #define UMCCH3_3_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
9206 #define UMCCH3_3_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
9207 //UMCCH3_3_EccErrCntSel
9208 #define UMCCH3_3_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
9209 #define UMCCH3_3_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
9210 #define UMCCH3_3_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
9211 #define UMCCH3_3_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
9212 #define UMCCH3_3_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
9213 #define UMCCH3_3_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
9214 //UMCCH3_3_EccErrCnt
9215 #define UMCCH3_3_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
9216 #define UMCCH3_3_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
9217 //UMCCH3_3_PerfMonCtlClk
9218 #define UMCCH3_3_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
9219 #define UMCCH3_3_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
9220 #define UMCCH3_3_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
9221 #define UMCCH3_3_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
9222 #define UMCCH3_3_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
9223 #define UMCCH3_3_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
9224 #define UMCCH3_3_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
9225 #define UMCCH3_3_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
9226 #define UMCCH3_3_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
9227 #define UMCCH3_3_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
9228 #define UMCCH3_3_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
9229 #define UMCCH3_3_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
9230 //UMCCH3_3_PerfMonCtrClk_Lo
9231 #define UMCCH3_3_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
9232 #define UMCCH3_3_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
9233 //UMCCH3_3_PerfMonCtrClk_Hi
9234 #define UMCCH3_3_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
9235 #define UMCCH3_3_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
9236 #define UMCCH3_3_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
9237 #define UMCCH3_3_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
9238 //UMCCH3_3_PerfMonCtl1
9239 #define UMCCH3_3_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
9240 #define UMCCH3_3_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
9241 #define UMCCH3_3_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
9242 #define UMCCH3_3_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
9243 #define UMCCH3_3_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
9244 #define UMCCH3_3_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
9245 #define UMCCH3_3_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
9246 #define UMCCH3_3_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
9247 #define UMCCH3_3_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
9248 #define UMCCH3_3_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
9249 #define UMCCH3_3_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
9250 #define UMCCH3_3_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
9251 #define UMCCH3_3_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
9252 #define UMCCH3_3_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
9253 #define UMCCH3_3_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
9254 #define UMCCH3_3_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
9255 //UMCCH3_3_PerfMonCtr1_Lo
9256 #define UMCCH3_3_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
9257 #define UMCCH3_3_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
9258 //UMCCH3_3_PerfMonCtr1_Hi
9259 #define UMCCH3_3_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
9260 #define UMCCH3_3_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
9261 #define UMCCH3_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
9262 #define UMCCH3_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
9263 #define UMCCH3_3_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
9264 #define UMCCH3_3_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
9265 #define UMCCH3_3_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9266 #define UMCCH3_3_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9267 //UMCCH3_3_PerfMonCtl2
9268 #define UMCCH3_3_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
9269 #define UMCCH3_3_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
9270 #define UMCCH3_3_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
9271 #define UMCCH3_3_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
9272 #define UMCCH3_3_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
9273 #define UMCCH3_3_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
9274 #define UMCCH3_3_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
9275 #define UMCCH3_3_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
9276 #define UMCCH3_3_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
9277 #define UMCCH3_3_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
9278 #define UMCCH3_3_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
9279 #define UMCCH3_3_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
9280 #define UMCCH3_3_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
9281 #define UMCCH3_3_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
9282 #define UMCCH3_3_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
9283 #define UMCCH3_3_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
9284 //UMCCH3_3_PerfMonCtr2_Lo
9285 #define UMCCH3_3_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
9286 #define UMCCH3_3_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
9287 //UMCCH3_3_PerfMonCtr2_Hi
9288 #define UMCCH3_3_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
9289 #define UMCCH3_3_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
9290 #define UMCCH3_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
9291 #define UMCCH3_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
9292 #define UMCCH3_3_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
9293 #define UMCCH3_3_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
9294 #define UMCCH3_3_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9295 #define UMCCH3_3_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9296 //UMCCH3_3_PerfMonCtl3
9297 #define UMCCH3_3_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
9298 #define UMCCH3_3_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
9299 #define UMCCH3_3_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
9300 #define UMCCH3_3_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
9301 #define UMCCH3_3_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
9302 #define UMCCH3_3_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
9303 #define UMCCH3_3_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
9304 #define UMCCH3_3_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
9305 #define UMCCH3_3_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
9306 #define UMCCH3_3_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
9307 #define UMCCH3_3_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
9308 #define UMCCH3_3_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
9309 #define UMCCH3_3_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
9310 #define UMCCH3_3_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
9311 #define UMCCH3_3_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
9312 #define UMCCH3_3_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
9313 //UMCCH3_3_PerfMonCtr3_Lo
9314 #define UMCCH3_3_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
9315 #define UMCCH3_3_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
9316 //UMCCH3_3_PerfMonCtr3_Hi
9317 #define UMCCH3_3_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
9318 #define UMCCH3_3_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
9319 #define UMCCH3_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
9320 #define UMCCH3_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
9321 #define UMCCH3_3_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
9322 #define UMCCH3_3_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
9323 #define UMCCH3_3_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9324 #define UMCCH3_3_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9325 //UMCCH3_3_PerfMonCtl4
9326 #define UMCCH3_3_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
9327 #define UMCCH3_3_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
9328 #define UMCCH3_3_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
9329 #define UMCCH3_3_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
9330 #define UMCCH3_3_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
9331 #define UMCCH3_3_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
9332 #define UMCCH3_3_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
9333 #define UMCCH3_3_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
9334 #define UMCCH3_3_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
9335 #define UMCCH3_3_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
9336 #define UMCCH3_3_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
9337 #define UMCCH3_3_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
9338 #define UMCCH3_3_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
9339 #define UMCCH3_3_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
9340 #define UMCCH3_3_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
9341 #define UMCCH3_3_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
9342 //UMCCH3_3_PerfMonCtr4_Lo
9343 #define UMCCH3_3_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
9344 #define UMCCH3_3_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
9345 //UMCCH3_3_PerfMonCtr4_Hi
9346 #define UMCCH3_3_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
9347 #define UMCCH3_3_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
9348 #define UMCCH3_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
9349 #define UMCCH3_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
9350 #define UMCCH3_3_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
9351 #define UMCCH3_3_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
9352 #define UMCCH3_3_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9353 #define UMCCH3_3_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9354 //UMCCH3_3_PerfMonCtl5
9355 #define UMCCH3_3_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
9356 #define UMCCH3_3_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
9357 #define UMCCH3_3_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
9358 #define UMCCH3_3_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
9359 #define UMCCH3_3_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
9360 #define UMCCH3_3_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
9361 #define UMCCH3_3_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
9362 #define UMCCH3_3_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
9363 #define UMCCH3_3_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
9364 #define UMCCH3_3_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
9365 #define UMCCH3_3_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
9366 #define UMCCH3_3_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
9367 #define UMCCH3_3_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
9368 #define UMCCH3_3_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
9369 #define UMCCH3_3_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
9370 #define UMCCH3_3_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
9371 //UMCCH3_3_PerfMonCtr5_Lo
9372 #define UMCCH3_3_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
9373 #define UMCCH3_3_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
9374 //UMCCH3_3_PerfMonCtr5_Hi
9375 #define UMCCH3_3_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
9376 #define UMCCH3_3_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
9377 #define UMCCH3_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
9378 #define UMCCH3_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
9379 #define UMCCH3_3_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
9380 #define UMCCH3_3_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
9381 #define UMCCH3_3_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9382 #define UMCCH3_3_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9383 //UMCCH3_3_PerfMonCtl6
9384 #define UMCCH3_3_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
9385 #define UMCCH3_3_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
9386 #define UMCCH3_3_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
9387 #define UMCCH3_3_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
9388 #define UMCCH3_3_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
9389 #define UMCCH3_3_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
9390 #define UMCCH3_3_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
9391 #define UMCCH3_3_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
9392 #define UMCCH3_3_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
9393 #define UMCCH3_3_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
9394 #define UMCCH3_3_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
9395 #define UMCCH3_3_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
9396 #define UMCCH3_3_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
9397 #define UMCCH3_3_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
9398 #define UMCCH3_3_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
9399 #define UMCCH3_3_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
9400 //UMCCH3_3_PerfMonCtr6_Lo
9401 #define UMCCH3_3_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
9402 #define UMCCH3_3_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
9403 //UMCCH3_3_PerfMonCtr6_Hi
9404 #define UMCCH3_3_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
9405 #define UMCCH3_3_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
9406 #define UMCCH3_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
9407 #define UMCCH3_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
9408 #define UMCCH3_3_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
9409 #define UMCCH3_3_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
9410 #define UMCCH3_3_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9411 #define UMCCH3_3_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9412 //UMCCH3_3_PerfMonCtl7
9413 #define UMCCH3_3_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
9414 #define UMCCH3_3_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
9415 #define UMCCH3_3_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
9416 #define UMCCH3_3_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
9417 #define UMCCH3_3_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
9418 #define UMCCH3_3_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
9419 #define UMCCH3_3_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
9420 #define UMCCH3_3_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
9421 #define UMCCH3_3_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
9422 #define UMCCH3_3_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
9423 #define UMCCH3_3_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
9424 #define UMCCH3_3_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
9425 #define UMCCH3_3_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
9426 #define UMCCH3_3_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
9427 #define UMCCH3_3_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
9428 #define UMCCH3_3_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
9429 //UMCCH3_3_PerfMonCtr7_Lo
9430 #define UMCCH3_3_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
9431 #define UMCCH3_3_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
9432 //UMCCH3_3_PerfMonCtr7_Hi
9433 #define UMCCH3_3_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
9434 #define UMCCH3_3_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
9435 #define UMCCH3_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
9436 #define UMCCH3_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
9437 #define UMCCH3_3_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
9438 #define UMCCH3_3_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
9439 #define UMCCH3_3_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9440 #define UMCCH3_3_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9441 //UMCCH3_3_PerfMonCtl8
9442 #define UMCCH3_3_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
9443 #define UMCCH3_3_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
9444 #define UMCCH3_3_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
9445 #define UMCCH3_3_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
9446 #define UMCCH3_3_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
9447 #define UMCCH3_3_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
9448 #define UMCCH3_3_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
9449 #define UMCCH3_3_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
9450 #define UMCCH3_3_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
9451 #define UMCCH3_3_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
9452 #define UMCCH3_3_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
9453 #define UMCCH3_3_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
9454 #define UMCCH3_3_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
9455 #define UMCCH3_3_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
9456 #define UMCCH3_3_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
9457 #define UMCCH3_3_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
9458 //UMCCH3_3_PerfMonCtr8_Lo
9459 #define UMCCH3_3_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
9460 #define UMCCH3_3_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
9461 //UMCCH3_3_PerfMonCtr8_Hi
9462 #define UMCCH3_3_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
9463 #define UMCCH3_3_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
9464 #define UMCCH3_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
9465 #define UMCCH3_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
9466 #define UMCCH3_3_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
9467 #define UMCCH3_3_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
9468 #define UMCCH3_3_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9469 #define UMCCH3_3_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9470 
9471 
9472 // addressBlock: umc_w_phy_umc3_umcch4_umcchdec
9473 //UMCCH4_3_BaseAddrCS0
9474 #define UMCCH4_3_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
9475 #define UMCCH4_3_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
9476 #define UMCCH4_3_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
9477 #define UMCCH4_3_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
9478 //UMCCH4_3_AddrMaskCS01
9479 #define UMCCH4_3_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
9480 #define UMCCH4_3_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
9481 //UMCCH4_3_AddrSelCS01
9482 #define UMCCH4_3_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
9483 #define UMCCH4_3_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
9484 #define UMCCH4_3_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
9485 #define UMCCH4_3_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
9486 #define UMCCH4_3_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
9487 #define UMCCH4_3_AddrSelCS01__RowLo__SHIFT                                                                    0x18
9488 #define UMCCH4_3_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
9489 #define UMCCH4_3_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
9490 #define UMCCH4_3_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
9491 #define UMCCH4_3_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
9492 #define UMCCH4_3_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
9493 #define UMCCH4_3_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
9494 #define UMCCH4_3_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
9495 #define UMCCH4_3_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
9496 //UMCCH4_3_AddrHashBank0
9497 #define UMCCH4_3_AddrHashBank0__XorEnable__SHIFT                                                              0x0
9498 #define UMCCH4_3_AddrHashBank0__ColXor__SHIFT                                                                 0x1
9499 #define UMCCH4_3_AddrHashBank0__RowXor__SHIFT                                                                 0xe
9500 #define UMCCH4_3_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
9501 #define UMCCH4_3_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
9502 #define UMCCH4_3_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
9503 //UMCCH4_3_AddrHashBank1
9504 #define UMCCH4_3_AddrHashBank1__XorEnable__SHIFT                                                              0x0
9505 #define UMCCH4_3_AddrHashBank1__ColXor__SHIFT                                                                 0x1
9506 #define UMCCH4_3_AddrHashBank1__RowXor__SHIFT                                                                 0xe
9507 #define UMCCH4_3_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
9508 #define UMCCH4_3_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
9509 #define UMCCH4_3_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
9510 //UMCCH4_3_AddrHashBank2
9511 #define UMCCH4_3_AddrHashBank2__XorEnable__SHIFT                                                              0x0
9512 #define UMCCH4_3_AddrHashBank2__ColXor__SHIFT                                                                 0x1
9513 #define UMCCH4_3_AddrHashBank2__RowXor__SHIFT                                                                 0xe
9514 #define UMCCH4_3_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
9515 #define UMCCH4_3_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
9516 #define UMCCH4_3_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
9517 //UMCCH4_3_AddrHashBank3
9518 #define UMCCH4_3_AddrHashBank3__XorEnable__SHIFT                                                              0x0
9519 #define UMCCH4_3_AddrHashBank3__ColXor__SHIFT                                                                 0x1
9520 #define UMCCH4_3_AddrHashBank3__RowXor__SHIFT                                                                 0xe
9521 #define UMCCH4_3_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
9522 #define UMCCH4_3_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
9523 #define UMCCH4_3_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
9524 //UMCCH4_3_AddrHashBank4
9525 #define UMCCH4_3_AddrHashBank4__XorEnable__SHIFT                                                              0x0
9526 #define UMCCH4_3_AddrHashBank4__ColXor__SHIFT                                                                 0x1
9527 #define UMCCH4_3_AddrHashBank4__RowXor__SHIFT                                                                 0xe
9528 #define UMCCH4_3_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
9529 #define UMCCH4_3_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
9530 #define UMCCH4_3_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
9531 //UMCCH4_3_AddrHashBank5
9532 #define UMCCH4_3_AddrHashBank5__XorEnable__SHIFT                                                              0x0
9533 #define UMCCH4_3_AddrHashBank5__ColXor__SHIFT                                                                 0x1
9534 #define UMCCH4_3_AddrHashBank5__RowXor__SHIFT                                                                 0xe
9535 #define UMCCH4_3_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
9536 #define UMCCH4_3_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
9537 #define UMCCH4_3_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
9538 //UMCCH4_3_EccErrCntSel
9539 #define UMCCH4_3_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
9540 #define UMCCH4_3_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
9541 #define UMCCH4_3_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
9542 #define UMCCH4_3_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
9543 #define UMCCH4_3_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
9544 #define UMCCH4_3_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
9545 //UMCCH4_3_EccErrCnt
9546 #define UMCCH4_3_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
9547 #define UMCCH4_3_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
9548 //UMCCH4_3_PerfMonCtlClk
9549 #define UMCCH4_3_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
9550 #define UMCCH4_3_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
9551 #define UMCCH4_3_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
9552 #define UMCCH4_3_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
9553 #define UMCCH4_3_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
9554 #define UMCCH4_3_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
9555 #define UMCCH4_3_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
9556 #define UMCCH4_3_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
9557 #define UMCCH4_3_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
9558 #define UMCCH4_3_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
9559 #define UMCCH4_3_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
9560 #define UMCCH4_3_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
9561 //UMCCH4_3_PerfMonCtrClk_Lo
9562 #define UMCCH4_3_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
9563 #define UMCCH4_3_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
9564 //UMCCH4_3_PerfMonCtrClk_Hi
9565 #define UMCCH4_3_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
9566 #define UMCCH4_3_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
9567 #define UMCCH4_3_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
9568 #define UMCCH4_3_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
9569 //UMCCH4_3_PerfMonCtl1
9570 #define UMCCH4_3_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
9571 #define UMCCH4_3_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
9572 #define UMCCH4_3_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
9573 #define UMCCH4_3_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
9574 #define UMCCH4_3_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
9575 #define UMCCH4_3_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
9576 #define UMCCH4_3_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
9577 #define UMCCH4_3_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
9578 #define UMCCH4_3_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
9579 #define UMCCH4_3_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
9580 #define UMCCH4_3_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
9581 #define UMCCH4_3_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
9582 #define UMCCH4_3_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
9583 #define UMCCH4_3_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
9584 #define UMCCH4_3_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
9585 #define UMCCH4_3_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
9586 //UMCCH4_3_PerfMonCtr1_Lo
9587 #define UMCCH4_3_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
9588 #define UMCCH4_3_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
9589 //UMCCH4_3_PerfMonCtr1_Hi
9590 #define UMCCH4_3_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
9591 #define UMCCH4_3_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
9592 #define UMCCH4_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
9593 #define UMCCH4_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
9594 #define UMCCH4_3_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
9595 #define UMCCH4_3_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
9596 #define UMCCH4_3_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9597 #define UMCCH4_3_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9598 //UMCCH4_3_PerfMonCtl2
9599 #define UMCCH4_3_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
9600 #define UMCCH4_3_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
9601 #define UMCCH4_3_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
9602 #define UMCCH4_3_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
9603 #define UMCCH4_3_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
9604 #define UMCCH4_3_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
9605 #define UMCCH4_3_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
9606 #define UMCCH4_3_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
9607 #define UMCCH4_3_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
9608 #define UMCCH4_3_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
9609 #define UMCCH4_3_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
9610 #define UMCCH4_3_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
9611 #define UMCCH4_3_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
9612 #define UMCCH4_3_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
9613 #define UMCCH4_3_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
9614 #define UMCCH4_3_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
9615 //UMCCH4_3_PerfMonCtr2_Lo
9616 #define UMCCH4_3_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
9617 #define UMCCH4_3_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
9618 //UMCCH4_3_PerfMonCtr2_Hi
9619 #define UMCCH4_3_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
9620 #define UMCCH4_3_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
9621 #define UMCCH4_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
9622 #define UMCCH4_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
9623 #define UMCCH4_3_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
9624 #define UMCCH4_3_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
9625 #define UMCCH4_3_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9626 #define UMCCH4_3_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9627 //UMCCH4_3_PerfMonCtl3
9628 #define UMCCH4_3_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
9629 #define UMCCH4_3_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
9630 #define UMCCH4_3_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
9631 #define UMCCH4_3_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
9632 #define UMCCH4_3_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
9633 #define UMCCH4_3_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
9634 #define UMCCH4_3_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
9635 #define UMCCH4_3_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
9636 #define UMCCH4_3_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
9637 #define UMCCH4_3_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
9638 #define UMCCH4_3_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
9639 #define UMCCH4_3_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
9640 #define UMCCH4_3_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
9641 #define UMCCH4_3_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
9642 #define UMCCH4_3_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
9643 #define UMCCH4_3_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
9644 //UMCCH4_3_PerfMonCtr3_Lo
9645 #define UMCCH4_3_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
9646 #define UMCCH4_3_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
9647 //UMCCH4_3_PerfMonCtr3_Hi
9648 #define UMCCH4_3_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
9649 #define UMCCH4_3_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
9650 #define UMCCH4_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
9651 #define UMCCH4_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
9652 #define UMCCH4_3_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
9653 #define UMCCH4_3_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
9654 #define UMCCH4_3_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9655 #define UMCCH4_3_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9656 //UMCCH4_3_PerfMonCtl4
9657 #define UMCCH4_3_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
9658 #define UMCCH4_3_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
9659 #define UMCCH4_3_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
9660 #define UMCCH4_3_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
9661 #define UMCCH4_3_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
9662 #define UMCCH4_3_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
9663 #define UMCCH4_3_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
9664 #define UMCCH4_3_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
9665 #define UMCCH4_3_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
9666 #define UMCCH4_3_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
9667 #define UMCCH4_3_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
9668 #define UMCCH4_3_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
9669 #define UMCCH4_3_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
9670 #define UMCCH4_3_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
9671 #define UMCCH4_3_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
9672 #define UMCCH4_3_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
9673 //UMCCH4_3_PerfMonCtr4_Lo
9674 #define UMCCH4_3_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
9675 #define UMCCH4_3_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
9676 //UMCCH4_3_PerfMonCtr4_Hi
9677 #define UMCCH4_3_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
9678 #define UMCCH4_3_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
9679 #define UMCCH4_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
9680 #define UMCCH4_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
9681 #define UMCCH4_3_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
9682 #define UMCCH4_3_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
9683 #define UMCCH4_3_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9684 #define UMCCH4_3_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9685 //UMCCH4_3_PerfMonCtl5
9686 #define UMCCH4_3_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
9687 #define UMCCH4_3_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
9688 #define UMCCH4_3_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
9689 #define UMCCH4_3_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
9690 #define UMCCH4_3_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
9691 #define UMCCH4_3_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
9692 #define UMCCH4_3_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
9693 #define UMCCH4_3_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
9694 #define UMCCH4_3_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
9695 #define UMCCH4_3_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
9696 #define UMCCH4_3_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
9697 #define UMCCH4_3_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
9698 #define UMCCH4_3_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
9699 #define UMCCH4_3_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
9700 #define UMCCH4_3_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
9701 #define UMCCH4_3_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
9702 //UMCCH4_3_PerfMonCtr5_Lo
9703 #define UMCCH4_3_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
9704 #define UMCCH4_3_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
9705 //UMCCH4_3_PerfMonCtr5_Hi
9706 #define UMCCH4_3_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
9707 #define UMCCH4_3_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
9708 #define UMCCH4_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
9709 #define UMCCH4_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
9710 #define UMCCH4_3_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
9711 #define UMCCH4_3_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
9712 #define UMCCH4_3_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9713 #define UMCCH4_3_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9714 //UMCCH4_3_PerfMonCtl6
9715 #define UMCCH4_3_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
9716 #define UMCCH4_3_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
9717 #define UMCCH4_3_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
9718 #define UMCCH4_3_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
9719 #define UMCCH4_3_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
9720 #define UMCCH4_3_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
9721 #define UMCCH4_3_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
9722 #define UMCCH4_3_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
9723 #define UMCCH4_3_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
9724 #define UMCCH4_3_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
9725 #define UMCCH4_3_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
9726 #define UMCCH4_3_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
9727 #define UMCCH4_3_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
9728 #define UMCCH4_3_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
9729 #define UMCCH4_3_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
9730 #define UMCCH4_3_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
9731 //UMCCH4_3_PerfMonCtr6_Lo
9732 #define UMCCH4_3_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
9733 #define UMCCH4_3_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
9734 //UMCCH4_3_PerfMonCtr6_Hi
9735 #define UMCCH4_3_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
9736 #define UMCCH4_3_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
9737 #define UMCCH4_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
9738 #define UMCCH4_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
9739 #define UMCCH4_3_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
9740 #define UMCCH4_3_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
9741 #define UMCCH4_3_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9742 #define UMCCH4_3_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9743 //UMCCH4_3_PerfMonCtl7
9744 #define UMCCH4_3_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
9745 #define UMCCH4_3_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
9746 #define UMCCH4_3_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
9747 #define UMCCH4_3_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
9748 #define UMCCH4_3_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
9749 #define UMCCH4_3_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
9750 #define UMCCH4_3_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
9751 #define UMCCH4_3_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
9752 #define UMCCH4_3_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
9753 #define UMCCH4_3_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
9754 #define UMCCH4_3_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
9755 #define UMCCH4_3_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
9756 #define UMCCH4_3_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
9757 #define UMCCH4_3_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
9758 #define UMCCH4_3_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
9759 #define UMCCH4_3_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
9760 //UMCCH4_3_PerfMonCtr7_Lo
9761 #define UMCCH4_3_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
9762 #define UMCCH4_3_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
9763 //UMCCH4_3_PerfMonCtr7_Hi
9764 #define UMCCH4_3_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
9765 #define UMCCH4_3_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
9766 #define UMCCH4_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
9767 #define UMCCH4_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
9768 #define UMCCH4_3_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
9769 #define UMCCH4_3_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
9770 #define UMCCH4_3_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9771 #define UMCCH4_3_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9772 //UMCCH4_3_PerfMonCtl8
9773 #define UMCCH4_3_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
9774 #define UMCCH4_3_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
9775 #define UMCCH4_3_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
9776 #define UMCCH4_3_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
9777 #define UMCCH4_3_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
9778 #define UMCCH4_3_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
9779 #define UMCCH4_3_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
9780 #define UMCCH4_3_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
9781 #define UMCCH4_3_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
9782 #define UMCCH4_3_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
9783 #define UMCCH4_3_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
9784 #define UMCCH4_3_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
9785 #define UMCCH4_3_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
9786 #define UMCCH4_3_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
9787 #define UMCCH4_3_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
9788 #define UMCCH4_3_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
9789 //UMCCH4_3_PerfMonCtr8_Lo
9790 #define UMCCH4_3_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
9791 #define UMCCH4_3_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
9792 //UMCCH4_3_PerfMonCtr8_Hi
9793 #define UMCCH4_3_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
9794 #define UMCCH4_3_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
9795 #define UMCCH4_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
9796 #define UMCCH4_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
9797 #define UMCCH4_3_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
9798 #define UMCCH4_3_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
9799 #define UMCCH4_3_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9800 #define UMCCH4_3_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9801 
9802 
9803 // addressBlock: umc_w_phy_umc3_umcch5_umcchdec
9804 //UMCCH5_3_BaseAddrCS0
9805 #define UMCCH5_3_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
9806 #define UMCCH5_3_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
9807 #define UMCCH5_3_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
9808 #define UMCCH5_3_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
9809 //UMCCH5_3_AddrMaskCS01
9810 #define UMCCH5_3_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
9811 #define UMCCH5_3_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
9812 //UMCCH5_3_AddrSelCS01
9813 #define UMCCH5_3_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
9814 #define UMCCH5_3_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
9815 #define UMCCH5_3_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
9816 #define UMCCH5_3_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
9817 #define UMCCH5_3_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
9818 #define UMCCH5_3_AddrSelCS01__RowLo__SHIFT                                                                    0x18
9819 #define UMCCH5_3_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
9820 #define UMCCH5_3_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
9821 #define UMCCH5_3_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
9822 #define UMCCH5_3_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
9823 #define UMCCH5_3_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
9824 #define UMCCH5_3_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
9825 #define UMCCH5_3_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
9826 #define UMCCH5_3_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
9827 //UMCCH5_3_AddrHashBank0
9828 #define UMCCH5_3_AddrHashBank0__XorEnable__SHIFT                                                              0x0
9829 #define UMCCH5_3_AddrHashBank0__ColXor__SHIFT                                                                 0x1
9830 #define UMCCH5_3_AddrHashBank0__RowXor__SHIFT                                                                 0xe
9831 #define UMCCH5_3_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
9832 #define UMCCH5_3_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
9833 #define UMCCH5_3_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
9834 //UMCCH5_3_AddrHashBank1
9835 #define UMCCH5_3_AddrHashBank1__XorEnable__SHIFT                                                              0x0
9836 #define UMCCH5_3_AddrHashBank1__ColXor__SHIFT                                                                 0x1
9837 #define UMCCH5_3_AddrHashBank1__RowXor__SHIFT                                                                 0xe
9838 #define UMCCH5_3_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
9839 #define UMCCH5_3_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
9840 #define UMCCH5_3_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
9841 //UMCCH5_3_AddrHashBank2
9842 #define UMCCH5_3_AddrHashBank2__XorEnable__SHIFT                                                              0x0
9843 #define UMCCH5_3_AddrHashBank2__ColXor__SHIFT                                                                 0x1
9844 #define UMCCH5_3_AddrHashBank2__RowXor__SHIFT                                                                 0xe
9845 #define UMCCH5_3_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
9846 #define UMCCH5_3_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
9847 #define UMCCH5_3_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
9848 //UMCCH5_3_AddrHashBank3
9849 #define UMCCH5_3_AddrHashBank3__XorEnable__SHIFT                                                              0x0
9850 #define UMCCH5_3_AddrHashBank3__ColXor__SHIFT                                                                 0x1
9851 #define UMCCH5_3_AddrHashBank3__RowXor__SHIFT                                                                 0xe
9852 #define UMCCH5_3_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
9853 #define UMCCH5_3_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
9854 #define UMCCH5_3_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
9855 //UMCCH5_3_AddrHashBank4
9856 #define UMCCH5_3_AddrHashBank4__XorEnable__SHIFT                                                              0x0
9857 #define UMCCH5_3_AddrHashBank4__ColXor__SHIFT                                                                 0x1
9858 #define UMCCH5_3_AddrHashBank4__RowXor__SHIFT                                                                 0xe
9859 #define UMCCH5_3_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
9860 #define UMCCH5_3_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
9861 #define UMCCH5_3_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
9862 //UMCCH5_3_AddrHashBank5
9863 #define UMCCH5_3_AddrHashBank5__XorEnable__SHIFT                                                              0x0
9864 #define UMCCH5_3_AddrHashBank5__ColXor__SHIFT                                                                 0x1
9865 #define UMCCH5_3_AddrHashBank5__RowXor__SHIFT                                                                 0xe
9866 #define UMCCH5_3_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
9867 #define UMCCH5_3_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
9868 #define UMCCH5_3_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
9869 //UMCCH5_3_EccErrCntSel
9870 #define UMCCH5_3_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
9871 #define UMCCH5_3_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
9872 #define UMCCH5_3_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
9873 #define UMCCH5_3_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
9874 #define UMCCH5_3_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
9875 #define UMCCH5_3_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
9876 //UMCCH5_3_EccErrCnt
9877 #define UMCCH5_3_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
9878 #define UMCCH5_3_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
9879 //UMCCH5_3_PerfMonCtlClk
9880 #define UMCCH5_3_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
9881 #define UMCCH5_3_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
9882 #define UMCCH5_3_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
9883 #define UMCCH5_3_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
9884 #define UMCCH5_3_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
9885 #define UMCCH5_3_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
9886 #define UMCCH5_3_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
9887 #define UMCCH5_3_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
9888 #define UMCCH5_3_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
9889 #define UMCCH5_3_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
9890 #define UMCCH5_3_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
9891 #define UMCCH5_3_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
9892 //UMCCH5_3_PerfMonCtrClk_Lo
9893 #define UMCCH5_3_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
9894 #define UMCCH5_3_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
9895 //UMCCH5_3_PerfMonCtrClk_Hi
9896 #define UMCCH5_3_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
9897 #define UMCCH5_3_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
9898 #define UMCCH5_3_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
9899 #define UMCCH5_3_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
9900 //UMCCH5_3_PerfMonCtl1
9901 #define UMCCH5_3_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
9902 #define UMCCH5_3_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
9903 #define UMCCH5_3_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
9904 #define UMCCH5_3_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
9905 #define UMCCH5_3_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
9906 #define UMCCH5_3_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
9907 #define UMCCH5_3_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
9908 #define UMCCH5_3_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
9909 #define UMCCH5_3_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
9910 #define UMCCH5_3_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
9911 #define UMCCH5_3_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
9912 #define UMCCH5_3_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
9913 #define UMCCH5_3_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
9914 #define UMCCH5_3_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
9915 #define UMCCH5_3_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
9916 #define UMCCH5_3_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
9917 //UMCCH5_3_PerfMonCtr1_Lo
9918 #define UMCCH5_3_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
9919 #define UMCCH5_3_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
9920 //UMCCH5_3_PerfMonCtr1_Hi
9921 #define UMCCH5_3_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
9922 #define UMCCH5_3_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
9923 #define UMCCH5_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
9924 #define UMCCH5_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
9925 #define UMCCH5_3_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
9926 #define UMCCH5_3_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
9927 #define UMCCH5_3_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9928 #define UMCCH5_3_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9929 //UMCCH5_3_PerfMonCtl2
9930 #define UMCCH5_3_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
9931 #define UMCCH5_3_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
9932 #define UMCCH5_3_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
9933 #define UMCCH5_3_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
9934 #define UMCCH5_3_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
9935 #define UMCCH5_3_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
9936 #define UMCCH5_3_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
9937 #define UMCCH5_3_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
9938 #define UMCCH5_3_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
9939 #define UMCCH5_3_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
9940 #define UMCCH5_3_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
9941 #define UMCCH5_3_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
9942 #define UMCCH5_3_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
9943 #define UMCCH5_3_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
9944 #define UMCCH5_3_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
9945 #define UMCCH5_3_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
9946 //UMCCH5_3_PerfMonCtr2_Lo
9947 #define UMCCH5_3_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
9948 #define UMCCH5_3_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
9949 //UMCCH5_3_PerfMonCtr2_Hi
9950 #define UMCCH5_3_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
9951 #define UMCCH5_3_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
9952 #define UMCCH5_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
9953 #define UMCCH5_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
9954 #define UMCCH5_3_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
9955 #define UMCCH5_3_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
9956 #define UMCCH5_3_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9957 #define UMCCH5_3_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9958 //UMCCH5_3_PerfMonCtl3
9959 #define UMCCH5_3_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
9960 #define UMCCH5_3_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
9961 #define UMCCH5_3_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
9962 #define UMCCH5_3_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
9963 #define UMCCH5_3_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
9964 #define UMCCH5_3_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
9965 #define UMCCH5_3_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
9966 #define UMCCH5_3_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
9967 #define UMCCH5_3_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
9968 #define UMCCH5_3_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
9969 #define UMCCH5_3_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
9970 #define UMCCH5_3_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
9971 #define UMCCH5_3_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
9972 #define UMCCH5_3_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
9973 #define UMCCH5_3_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
9974 #define UMCCH5_3_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
9975 //UMCCH5_3_PerfMonCtr3_Lo
9976 #define UMCCH5_3_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
9977 #define UMCCH5_3_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
9978 //UMCCH5_3_PerfMonCtr3_Hi
9979 #define UMCCH5_3_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
9980 #define UMCCH5_3_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
9981 #define UMCCH5_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
9982 #define UMCCH5_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
9983 #define UMCCH5_3_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
9984 #define UMCCH5_3_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
9985 #define UMCCH5_3_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
9986 #define UMCCH5_3_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
9987 //UMCCH5_3_PerfMonCtl4
9988 #define UMCCH5_3_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
9989 #define UMCCH5_3_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
9990 #define UMCCH5_3_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
9991 #define UMCCH5_3_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
9992 #define UMCCH5_3_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
9993 #define UMCCH5_3_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
9994 #define UMCCH5_3_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
9995 #define UMCCH5_3_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
9996 #define UMCCH5_3_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
9997 #define UMCCH5_3_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
9998 #define UMCCH5_3_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
9999 #define UMCCH5_3_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
10000 #define UMCCH5_3_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
10001 #define UMCCH5_3_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
10002 #define UMCCH5_3_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
10003 #define UMCCH5_3_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
10004 //UMCCH5_3_PerfMonCtr4_Lo
10005 #define UMCCH5_3_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
10006 #define UMCCH5_3_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
10007 //UMCCH5_3_PerfMonCtr4_Hi
10008 #define UMCCH5_3_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
10009 #define UMCCH5_3_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
10010 #define UMCCH5_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
10011 #define UMCCH5_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
10012 #define UMCCH5_3_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
10013 #define UMCCH5_3_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
10014 #define UMCCH5_3_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10015 #define UMCCH5_3_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10016 //UMCCH5_3_PerfMonCtl5
10017 #define UMCCH5_3_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
10018 #define UMCCH5_3_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
10019 #define UMCCH5_3_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
10020 #define UMCCH5_3_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
10021 #define UMCCH5_3_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
10022 #define UMCCH5_3_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
10023 #define UMCCH5_3_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
10024 #define UMCCH5_3_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
10025 #define UMCCH5_3_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
10026 #define UMCCH5_3_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
10027 #define UMCCH5_3_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
10028 #define UMCCH5_3_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
10029 #define UMCCH5_3_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
10030 #define UMCCH5_3_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
10031 #define UMCCH5_3_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
10032 #define UMCCH5_3_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
10033 //UMCCH5_3_PerfMonCtr5_Lo
10034 #define UMCCH5_3_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
10035 #define UMCCH5_3_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
10036 //UMCCH5_3_PerfMonCtr5_Hi
10037 #define UMCCH5_3_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
10038 #define UMCCH5_3_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
10039 #define UMCCH5_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
10040 #define UMCCH5_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
10041 #define UMCCH5_3_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
10042 #define UMCCH5_3_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
10043 #define UMCCH5_3_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10044 #define UMCCH5_3_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10045 //UMCCH5_3_PerfMonCtl6
10046 #define UMCCH5_3_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
10047 #define UMCCH5_3_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
10048 #define UMCCH5_3_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
10049 #define UMCCH5_3_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
10050 #define UMCCH5_3_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
10051 #define UMCCH5_3_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
10052 #define UMCCH5_3_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
10053 #define UMCCH5_3_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
10054 #define UMCCH5_3_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
10055 #define UMCCH5_3_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
10056 #define UMCCH5_3_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
10057 #define UMCCH5_3_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
10058 #define UMCCH5_3_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
10059 #define UMCCH5_3_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
10060 #define UMCCH5_3_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
10061 #define UMCCH5_3_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
10062 //UMCCH5_3_PerfMonCtr6_Lo
10063 #define UMCCH5_3_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
10064 #define UMCCH5_3_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
10065 //UMCCH5_3_PerfMonCtr6_Hi
10066 #define UMCCH5_3_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
10067 #define UMCCH5_3_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
10068 #define UMCCH5_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
10069 #define UMCCH5_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
10070 #define UMCCH5_3_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
10071 #define UMCCH5_3_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
10072 #define UMCCH5_3_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10073 #define UMCCH5_3_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10074 //UMCCH5_3_PerfMonCtl7
10075 #define UMCCH5_3_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
10076 #define UMCCH5_3_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
10077 #define UMCCH5_3_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
10078 #define UMCCH5_3_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
10079 #define UMCCH5_3_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
10080 #define UMCCH5_3_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
10081 #define UMCCH5_3_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
10082 #define UMCCH5_3_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
10083 #define UMCCH5_3_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
10084 #define UMCCH5_3_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
10085 #define UMCCH5_3_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
10086 #define UMCCH5_3_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
10087 #define UMCCH5_3_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
10088 #define UMCCH5_3_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
10089 #define UMCCH5_3_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
10090 #define UMCCH5_3_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
10091 //UMCCH5_3_PerfMonCtr7_Lo
10092 #define UMCCH5_3_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
10093 #define UMCCH5_3_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
10094 //UMCCH5_3_PerfMonCtr7_Hi
10095 #define UMCCH5_3_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
10096 #define UMCCH5_3_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
10097 #define UMCCH5_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
10098 #define UMCCH5_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
10099 #define UMCCH5_3_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
10100 #define UMCCH5_3_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
10101 #define UMCCH5_3_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10102 #define UMCCH5_3_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10103 //UMCCH5_3_PerfMonCtl8
10104 #define UMCCH5_3_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
10105 #define UMCCH5_3_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
10106 #define UMCCH5_3_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
10107 #define UMCCH5_3_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
10108 #define UMCCH5_3_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
10109 #define UMCCH5_3_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
10110 #define UMCCH5_3_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
10111 #define UMCCH5_3_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
10112 #define UMCCH5_3_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
10113 #define UMCCH5_3_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
10114 #define UMCCH5_3_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
10115 #define UMCCH5_3_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
10116 #define UMCCH5_3_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
10117 #define UMCCH5_3_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
10118 #define UMCCH5_3_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
10119 #define UMCCH5_3_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
10120 //UMCCH5_3_PerfMonCtr8_Lo
10121 #define UMCCH5_3_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
10122 #define UMCCH5_3_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
10123 //UMCCH5_3_PerfMonCtr8_Hi
10124 #define UMCCH5_3_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
10125 #define UMCCH5_3_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
10126 #define UMCCH5_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
10127 #define UMCCH5_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
10128 #define UMCCH5_3_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
10129 #define UMCCH5_3_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
10130 #define UMCCH5_3_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10131 #define UMCCH5_3_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10132 
10133 
10134 // addressBlock: umc_w_phy_umc3_umcch6_umcchdec
10135 //UMCCH6_3_BaseAddrCS0
10136 #define UMCCH6_3_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
10137 #define UMCCH6_3_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
10138 #define UMCCH6_3_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
10139 #define UMCCH6_3_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
10140 //UMCCH6_3_AddrMaskCS01
10141 #define UMCCH6_3_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
10142 #define UMCCH6_3_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
10143 //UMCCH6_3_AddrSelCS01
10144 #define UMCCH6_3_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
10145 #define UMCCH6_3_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
10146 #define UMCCH6_3_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
10147 #define UMCCH6_3_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
10148 #define UMCCH6_3_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
10149 #define UMCCH6_3_AddrSelCS01__RowLo__SHIFT                                                                    0x18
10150 #define UMCCH6_3_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
10151 #define UMCCH6_3_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
10152 #define UMCCH6_3_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
10153 #define UMCCH6_3_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
10154 #define UMCCH6_3_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
10155 #define UMCCH6_3_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
10156 #define UMCCH6_3_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
10157 #define UMCCH6_3_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
10158 //UMCCH6_3_AddrHashBank0
10159 #define UMCCH6_3_AddrHashBank0__XorEnable__SHIFT                                                              0x0
10160 #define UMCCH6_3_AddrHashBank0__ColXor__SHIFT                                                                 0x1
10161 #define UMCCH6_3_AddrHashBank0__RowXor__SHIFT                                                                 0xe
10162 #define UMCCH6_3_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
10163 #define UMCCH6_3_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
10164 #define UMCCH6_3_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
10165 //UMCCH6_3_AddrHashBank1
10166 #define UMCCH6_3_AddrHashBank1__XorEnable__SHIFT                                                              0x0
10167 #define UMCCH6_3_AddrHashBank1__ColXor__SHIFT                                                                 0x1
10168 #define UMCCH6_3_AddrHashBank1__RowXor__SHIFT                                                                 0xe
10169 #define UMCCH6_3_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
10170 #define UMCCH6_3_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
10171 #define UMCCH6_3_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
10172 //UMCCH6_3_AddrHashBank2
10173 #define UMCCH6_3_AddrHashBank2__XorEnable__SHIFT                                                              0x0
10174 #define UMCCH6_3_AddrHashBank2__ColXor__SHIFT                                                                 0x1
10175 #define UMCCH6_3_AddrHashBank2__RowXor__SHIFT                                                                 0xe
10176 #define UMCCH6_3_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
10177 #define UMCCH6_3_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
10178 #define UMCCH6_3_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
10179 //UMCCH6_3_AddrHashBank3
10180 #define UMCCH6_3_AddrHashBank3__XorEnable__SHIFT                                                              0x0
10181 #define UMCCH6_3_AddrHashBank3__ColXor__SHIFT                                                                 0x1
10182 #define UMCCH6_3_AddrHashBank3__RowXor__SHIFT                                                                 0xe
10183 #define UMCCH6_3_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
10184 #define UMCCH6_3_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
10185 #define UMCCH6_3_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
10186 //UMCCH6_3_AddrHashBank4
10187 #define UMCCH6_3_AddrHashBank4__XorEnable__SHIFT                                                              0x0
10188 #define UMCCH6_3_AddrHashBank4__ColXor__SHIFT                                                                 0x1
10189 #define UMCCH6_3_AddrHashBank4__RowXor__SHIFT                                                                 0xe
10190 #define UMCCH6_3_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
10191 #define UMCCH6_3_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
10192 #define UMCCH6_3_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
10193 //UMCCH6_3_AddrHashBank5
10194 #define UMCCH6_3_AddrHashBank5__XorEnable__SHIFT                                                              0x0
10195 #define UMCCH6_3_AddrHashBank5__ColXor__SHIFT                                                                 0x1
10196 #define UMCCH6_3_AddrHashBank5__RowXor__SHIFT                                                                 0xe
10197 #define UMCCH6_3_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
10198 #define UMCCH6_3_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
10199 #define UMCCH6_3_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
10200 //UMCCH6_3_EccErrCntSel
10201 #define UMCCH6_3_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
10202 #define UMCCH6_3_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
10203 #define UMCCH6_3_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
10204 #define UMCCH6_3_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
10205 #define UMCCH6_3_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
10206 #define UMCCH6_3_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
10207 //UMCCH6_3_EccErrCnt
10208 #define UMCCH6_3_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
10209 #define UMCCH6_3_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
10210 //UMCCH6_3_PerfMonCtlClk
10211 #define UMCCH6_3_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
10212 #define UMCCH6_3_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
10213 #define UMCCH6_3_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
10214 #define UMCCH6_3_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
10215 #define UMCCH6_3_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
10216 #define UMCCH6_3_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
10217 #define UMCCH6_3_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
10218 #define UMCCH6_3_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
10219 #define UMCCH6_3_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
10220 #define UMCCH6_3_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
10221 #define UMCCH6_3_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
10222 #define UMCCH6_3_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
10223 //UMCCH6_3_PerfMonCtrClk_Lo
10224 #define UMCCH6_3_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
10225 #define UMCCH6_3_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
10226 //UMCCH6_3_PerfMonCtrClk_Hi
10227 #define UMCCH6_3_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
10228 #define UMCCH6_3_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
10229 #define UMCCH6_3_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
10230 #define UMCCH6_3_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
10231 //UMCCH6_3_PerfMonCtl1
10232 #define UMCCH6_3_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
10233 #define UMCCH6_3_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
10234 #define UMCCH6_3_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
10235 #define UMCCH6_3_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
10236 #define UMCCH6_3_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
10237 #define UMCCH6_3_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
10238 #define UMCCH6_3_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
10239 #define UMCCH6_3_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
10240 #define UMCCH6_3_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
10241 #define UMCCH6_3_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
10242 #define UMCCH6_3_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
10243 #define UMCCH6_3_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
10244 #define UMCCH6_3_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
10245 #define UMCCH6_3_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
10246 #define UMCCH6_3_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
10247 #define UMCCH6_3_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
10248 //UMCCH6_3_PerfMonCtr1_Lo
10249 #define UMCCH6_3_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
10250 #define UMCCH6_3_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
10251 //UMCCH6_3_PerfMonCtr1_Hi
10252 #define UMCCH6_3_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
10253 #define UMCCH6_3_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
10254 #define UMCCH6_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
10255 #define UMCCH6_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
10256 #define UMCCH6_3_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
10257 #define UMCCH6_3_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
10258 #define UMCCH6_3_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10259 #define UMCCH6_3_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10260 //UMCCH6_3_PerfMonCtl2
10261 #define UMCCH6_3_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
10262 #define UMCCH6_3_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
10263 #define UMCCH6_3_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
10264 #define UMCCH6_3_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
10265 #define UMCCH6_3_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
10266 #define UMCCH6_3_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
10267 #define UMCCH6_3_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
10268 #define UMCCH6_3_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
10269 #define UMCCH6_3_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
10270 #define UMCCH6_3_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
10271 #define UMCCH6_3_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
10272 #define UMCCH6_3_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
10273 #define UMCCH6_3_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
10274 #define UMCCH6_3_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
10275 #define UMCCH6_3_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
10276 #define UMCCH6_3_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
10277 //UMCCH6_3_PerfMonCtr2_Lo
10278 #define UMCCH6_3_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
10279 #define UMCCH6_3_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
10280 //UMCCH6_3_PerfMonCtr2_Hi
10281 #define UMCCH6_3_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
10282 #define UMCCH6_3_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
10283 #define UMCCH6_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
10284 #define UMCCH6_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
10285 #define UMCCH6_3_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
10286 #define UMCCH6_3_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
10287 #define UMCCH6_3_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10288 #define UMCCH6_3_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10289 //UMCCH6_3_PerfMonCtl3
10290 #define UMCCH6_3_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
10291 #define UMCCH6_3_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
10292 #define UMCCH6_3_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
10293 #define UMCCH6_3_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
10294 #define UMCCH6_3_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
10295 #define UMCCH6_3_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
10296 #define UMCCH6_3_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
10297 #define UMCCH6_3_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
10298 #define UMCCH6_3_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
10299 #define UMCCH6_3_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
10300 #define UMCCH6_3_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
10301 #define UMCCH6_3_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
10302 #define UMCCH6_3_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
10303 #define UMCCH6_3_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
10304 #define UMCCH6_3_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
10305 #define UMCCH6_3_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
10306 //UMCCH6_3_PerfMonCtr3_Lo
10307 #define UMCCH6_3_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
10308 #define UMCCH6_3_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
10309 //UMCCH6_3_PerfMonCtr3_Hi
10310 #define UMCCH6_3_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
10311 #define UMCCH6_3_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
10312 #define UMCCH6_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
10313 #define UMCCH6_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
10314 #define UMCCH6_3_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
10315 #define UMCCH6_3_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
10316 #define UMCCH6_3_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10317 #define UMCCH6_3_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10318 //UMCCH6_3_PerfMonCtl4
10319 #define UMCCH6_3_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
10320 #define UMCCH6_3_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
10321 #define UMCCH6_3_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
10322 #define UMCCH6_3_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
10323 #define UMCCH6_3_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
10324 #define UMCCH6_3_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
10325 #define UMCCH6_3_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
10326 #define UMCCH6_3_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
10327 #define UMCCH6_3_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
10328 #define UMCCH6_3_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
10329 #define UMCCH6_3_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
10330 #define UMCCH6_3_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
10331 #define UMCCH6_3_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
10332 #define UMCCH6_3_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
10333 #define UMCCH6_3_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
10334 #define UMCCH6_3_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
10335 //UMCCH6_3_PerfMonCtr4_Lo
10336 #define UMCCH6_3_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
10337 #define UMCCH6_3_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
10338 //UMCCH6_3_PerfMonCtr4_Hi
10339 #define UMCCH6_3_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
10340 #define UMCCH6_3_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
10341 #define UMCCH6_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
10342 #define UMCCH6_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
10343 #define UMCCH6_3_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
10344 #define UMCCH6_3_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
10345 #define UMCCH6_3_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10346 #define UMCCH6_3_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10347 //UMCCH6_3_PerfMonCtl5
10348 #define UMCCH6_3_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
10349 #define UMCCH6_3_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
10350 #define UMCCH6_3_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
10351 #define UMCCH6_3_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
10352 #define UMCCH6_3_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
10353 #define UMCCH6_3_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
10354 #define UMCCH6_3_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
10355 #define UMCCH6_3_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
10356 #define UMCCH6_3_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
10357 #define UMCCH6_3_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
10358 #define UMCCH6_3_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
10359 #define UMCCH6_3_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
10360 #define UMCCH6_3_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
10361 #define UMCCH6_3_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
10362 #define UMCCH6_3_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
10363 #define UMCCH6_3_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
10364 //UMCCH6_3_PerfMonCtr5_Lo
10365 #define UMCCH6_3_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
10366 #define UMCCH6_3_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
10367 //UMCCH6_3_PerfMonCtr5_Hi
10368 #define UMCCH6_3_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
10369 #define UMCCH6_3_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
10370 #define UMCCH6_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
10371 #define UMCCH6_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
10372 #define UMCCH6_3_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
10373 #define UMCCH6_3_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
10374 #define UMCCH6_3_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10375 #define UMCCH6_3_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10376 //UMCCH6_3_PerfMonCtl6
10377 #define UMCCH6_3_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
10378 #define UMCCH6_3_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
10379 #define UMCCH6_3_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
10380 #define UMCCH6_3_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
10381 #define UMCCH6_3_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
10382 #define UMCCH6_3_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
10383 #define UMCCH6_3_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
10384 #define UMCCH6_3_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
10385 #define UMCCH6_3_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
10386 #define UMCCH6_3_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
10387 #define UMCCH6_3_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
10388 #define UMCCH6_3_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
10389 #define UMCCH6_3_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
10390 #define UMCCH6_3_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
10391 #define UMCCH6_3_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
10392 #define UMCCH6_3_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
10393 //UMCCH6_3_PerfMonCtr6_Lo
10394 #define UMCCH6_3_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
10395 #define UMCCH6_3_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
10396 //UMCCH6_3_PerfMonCtr6_Hi
10397 #define UMCCH6_3_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
10398 #define UMCCH6_3_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
10399 #define UMCCH6_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
10400 #define UMCCH6_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
10401 #define UMCCH6_3_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
10402 #define UMCCH6_3_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
10403 #define UMCCH6_3_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10404 #define UMCCH6_3_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10405 //UMCCH6_3_PerfMonCtl7
10406 #define UMCCH6_3_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
10407 #define UMCCH6_3_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
10408 #define UMCCH6_3_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
10409 #define UMCCH6_3_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
10410 #define UMCCH6_3_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
10411 #define UMCCH6_3_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
10412 #define UMCCH6_3_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
10413 #define UMCCH6_3_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
10414 #define UMCCH6_3_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
10415 #define UMCCH6_3_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
10416 #define UMCCH6_3_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
10417 #define UMCCH6_3_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
10418 #define UMCCH6_3_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
10419 #define UMCCH6_3_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
10420 #define UMCCH6_3_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
10421 #define UMCCH6_3_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
10422 //UMCCH6_3_PerfMonCtr7_Lo
10423 #define UMCCH6_3_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
10424 #define UMCCH6_3_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
10425 //UMCCH6_3_PerfMonCtr7_Hi
10426 #define UMCCH6_3_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
10427 #define UMCCH6_3_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
10428 #define UMCCH6_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
10429 #define UMCCH6_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
10430 #define UMCCH6_3_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
10431 #define UMCCH6_3_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
10432 #define UMCCH6_3_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10433 #define UMCCH6_3_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10434 //UMCCH6_3_PerfMonCtl8
10435 #define UMCCH6_3_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
10436 #define UMCCH6_3_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
10437 #define UMCCH6_3_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
10438 #define UMCCH6_3_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
10439 #define UMCCH6_3_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
10440 #define UMCCH6_3_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
10441 #define UMCCH6_3_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
10442 #define UMCCH6_3_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
10443 #define UMCCH6_3_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
10444 #define UMCCH6_3_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
10445 #define UMCCH6_3_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
10446 #define UMCCH6_3_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
10447 #define UMCCH6_3_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
10448 #define UMCCH6_3_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
10449 #define UMCCH6_3_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
10450 #define UMCCH6_3_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
10451 //UMCCH6_3_PerfMonCtr8_Lo
10452 #define UMCCH6_3_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
10453 #define UMCCH6_3_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
10454 //UMCCH6_3_PerfMonCtr8_Hi
10455 #define UMCCH6_3_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
10456 #define UMCCH6_3_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
10457 #define UMCCH6_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
10458 #define UMCCH6_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
10459 #define UMCCH6_3_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
10460 #define UMCCH6_3_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
10461 #define UMCCH6_3_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10462 #define UMCCH6_3_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10463 
10464 
10465 // addressBlock: umc_w_phy_umc3_umcch7_umcchdec
10466 //UMCCH7_3_BaseAddrCS0
10467 #define UMCCH7_3_BaseAddrCS0__CSEnable__SHIFT                                                                 0x0
10468 #define UMCCH7_3_BaseAddrCS0__BaseAddr__SHIFT                                                                 0x1
10469 #define UMCCH7_3_BaseAddrCS0__CSEnable_MASK                                                                   0x00000001L
10470 #define UMCCH7_3_BaseAddrCS0__BaseAddr_MASK                                                                   0xFFFFFFFEL
10471 //UMCCH7_3_AddrMaskCS01
10472 #define UMCCH7_3_AddrMaskCS01__AddrMask__SHIFT                                                                0x1
10473 #define UMCCH7_3_AddrMaskCS01__AddrMask_MASK                                                                  0xFFFFFFFEL
10474 //UMCCH7_3_AddrSelCS01
10475 #define UMCCH7_3_AddrSelCS01__BankBit0__SHIFT                                                                 0x0
10476 #define UMCCH7_3_AddrSelCS01__BankBit1__SHIFT                                                                 0x4
10477 #define UMCCH7_3_AddrSelCS01__BankBit2__SHIFT                                                                 0x8
10478 #define UMCCH7_3_AddrSelCS01__BankBit3__SHIFT                                                                 0xc
10479 #define UMCCH7_3_AddrSelCS01__BankBit4__SHIFT                                                                 0x10
10480 #define UMCCH7_3_AddrSelCS01__RowLo__SHIFT                                                                    0x18
10481 #define UMCCH7_3_AddrSelCS01__RowHi__SHIFT                                                                    0x1c
10482 #define UMCCH7_3_AddrSelCS01__BankBit0_MASK                                                                   0x0000000FL
10483 #define UMCCH7_3_AddrSelCS01__BankBit1_MASK                                                                   0x000000F0L
10484 #define UMCCH7_3_AddrSelCS01__BankBit2_MASK                                                                   0x00000F00L
10485 #define UMCCH7_3_AddrSelCS01__BankBit3_MASK                                                                   0x0000F000L
10486 #define UMCCH7_3_AddrSelCS01__BankBit4_MASK                                                                   0x001F0000L
10487 #define UMCCH7_3_AddrSelCS01__RowLo_MASK                                                                      0x0F000000L
10488 #define UMCCH7_3_AddrSelCS01__RowHi_MASK                                                                      0xF0000000L
10489 //UMCCH7_3_AddrHashBank0
10490 #define UMCCH7_3_AddrHashBank0__XorEnable__SHIFT                                                              0x0
10491 #define UMCCH7_3_AddrHashBank0__ColXor__SHIFT                                                                 0x1
10492 #define UMCCH7_3_AddrHashBank0__RowXor__SHIFT                                                                 0xe
10493 #define UMCCH7_3_AddrHashBank0__XorEnable_MASK                                                                0x00000001L
10494 #define UMCCH7_3_AddrHashBank0__ColXor_MASK                                                                   0x00003FFEL
10495 #define UMCCH7_3_AddrHashBank0__RowXor_MASK                                                                   0xFFFFC000L
10496 //UMCCH7_3_AddrHashBank1
10497 #define UMCCH7_3_AddrHashBank1__XorEnable__SHIFT                                                              0x0
10498 #define UMCCH7_3_AddrHashBank1__ColXor__SHIFT                                                                 0x1
10499 #define UMCCH7_3_AddrHashBank1__RowXor__SHIFT                                                                 0xe
10500 #define UMCCH7_3_AddrHashBank1__XorEnable_MASK                                                                0x00000001L
10501 #define UMCCH7_3_AddrHashBank1__ColXor_MASK                                                                   0x00003FFEL
10502 #define UMCCH7_3_AddrHashBank1__RowXor_MASK                                                                   0xFFFFC000L
10503 //UMCCH7_3_AddrHashBank2
10504 #define UMCCH7_3_AddrHashBank2__XorEnable__SHIFT                                                              0x0
10505 #define UMCCH7_3_AddrHashBank2__ColXor__SHIFT                                                                 0x1
10506 #define UMCCH7_3_AddrHashBank2__RowXor__SHIFT                                                                 0xe
10507 #define UMCCH7_3_AddrHashBank2__XorEnable_MASK                                                                0x00000001L
10508 #define UMCCH7_3_AddrHashBank2__ColXor_MASK                                                                   0x00003FFEL
10509 #define UMCCH7_3_AddrHashBank2__RowXor_MASK                                                                   0xFFFFC000L
10510 //UMCCH7_3_AddrHashBank3
10511 #define UMCCH7_3_AddrHashBank3__XorEnable__SHIFT                                                              0x0
10512 #define UMCCH7_3_AddrHashBank3__ColXor__SHIFT                                                                 0x1
10513 #define UMCCH7_3_AddrHashBank3__RowXor__SHIFT                                                                 0xe
10514 #define UMCCH7_3_AddrHashBank3__XorEnable_MASK                                                                0x00000001L
10515 #define UMCCH7_3_AddrHashBank3__ColXor_MASK                                                                   0x00003FFEL
10516 #define UMCCH7_3_AddrHashBank3__RowXor_MASK                                                                   0xFFFFC000L
10517 //UMCCH7_3_AddrHashBank4
10518 #define UMCCH7_3_AddrHashBank4__XorEnable__SHIFT                                                              0x0
10519 #define UMCCH7_3_AddrHashBank4__ColXor__SHIFT                                                                 0x1
10520 #define UMCCH7_3_AddrHashBank4__RowXor__SHIFT                                                                 0xe
10521 #define UMCCH7_3_AddrHashBank4__XorEnable_MASK                                                                0x00000001L
10522 #define UMCCH7_3_AddrHashBank4__ColXor_MASK                                                                   0x00003FFEL
10523 #define UMCCH7_3_AddrHashBank4__RowXor_MASK                                                                   0xFFFFC000L
10524 //UMCCH7_3_AddrHashBank5
10525 #define UMCCH7_3_AddrHashBank5__XorEnable__SHIFT                                                              0x0
10526 #define UMCCH7_3_AddrHashBank5__ColXor__SHIFT                                                                 0x1
10527 #define UMCCH7_3_AddrHashBank5__RowXor__SHIFT                                                                 0xe
10528 #define UMCCH7_3_AddrHashBank5__XorEnable_MASK                                                                0x00000001L
10529 #define UMCCH7_3_AddrHashBank5__ColXor_MASK                                                                   0x00003FFEL
10530 #define UMCCH7_3_AddrHashBank5__RowXor_MASK                                                                   0xFFFFC000L
10531 //UMCCH7_3_EccErrCntSel
10532 #define UMCCH7_3_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
10533 #define UMCCH7_3_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
10534 #define UMCCH7_3_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
10535 #define UMCCH7_3_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
10536 #define UMCCH7_3_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
10537 #define UMCCH7_3_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
10538 //UMCCH7_3_EccErrCnt
10539 #define UMCCH7_3_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
10540 #define UMCCH7_3_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
10541 //UMCCH7_3_PerfMonCtlClk
10542 #define UMCCH7_3_PerfMonCtlClk__GlblResetMsk__SHIFT                                                           0x0
10543 #define UMCCH7_3_PerfMonCtlClk__ClkGate__SHIFT                                                                0x16
10544 #define UMCCH7_3_PerfMonCtlClk__GlblReset__SHIFT                                                              0x18
10545 #define UMCCH7_3_PerfMonCtlClk__GlblMonEn__SHIFT                                                              0x19
10546 #define UMCCH7_3_PerfMonCtlClk__NumCounters__SHIFT                                                            0x1a
10547 #define UMCCH7_3_PerfMonCtlClk__CtrClkEn__SHIFT                                                               0x1f
10548 #define UMCCH7_3_PerfMonCtlClk__GlblResetMsk_MASK                                                             0x000001FFL
10549 #define UMCCH7_3_PerfMonCtlClk__ClkGate_MASK                                                                  0x00400000L
10550 #define UMCCH7_3_PerfMonCtlClk__GlblReset_MASK                                                                0x01000000L
10551 #define UMCCH7_3_PerfMonCtlClk__GlblMonEn_MASK                                                                0x02000000L
10552 #define UMCCH7_3_PerfMonCtlClk__NumCounters_MASK                                                              0x3C000000L
10553 #define UMCCH7_3_PerfMonCtlClk__CtrClkEn_MASK                                                                 0x80000000L
10554 //UMCCH7_3_PerfMonCtrClk_Lo
10555 #define UMCCH7_3_PerfMonCtrClk_Lo__Data__SHIFT                                                                0x0
10556 #define UMCCH7_3_PerfMonCtrClk_Lo__Data_MASK                                                                  0xFFFFFFFFL
10557 //UMCCH7_3_PerfMonCtrClk_Hi
10558 #define UMCCH7_3_PerfMonCtrClk_Hi__Data__SHIFT                                                                0x0
10559 #define UMCCH7_3_PerfMonCtrClk_Hi__Overflow__SHIFT                                                            0x10
10560 #define UMCCH7_3_PerfMonCtrClk_Hi__Data_MASK                                                                  0x0000FFFFL
10561 #define UMCCH7_3_PerfMonCtrClk_Hi__Overflow_MASK                                                              0x00010000L
10562 //UMCCH7_3_PerfMonCtl1
10563 #define UMCCH7_3_PerfMonCtl1__EventSelect__SHIFT                                                              0x0
10564 #define UMCCH7_3_PerfMonCtl1__RdWrMask__SHIFT                                                                 0x8
10565 #define UMCCH7_3_PerfMonCtl1__PriorityMask__SHIFT                                                             0xa
10566 #define UMCCH7_3_PerfMonCtl1__ReqSizeMask__SHIFT                                                              0xe
10567 #define UMCCH7_3_PerfMonCtl1__BankSel__SHIFT                                                                  0x10
10568 #define UMCCH7_3_PerfMonCtl1__VCSel__SHIFT                                                                    0x18
10569 #define UMCCH7_3_PerfMonCtl1__SubChanMask__SHIFT                                                              0x1d
10570 #define UMCCH7_3_PerfMonCtl1__Enable__SHIFT                                                                   0x1f
10571 #define UMCCH7_3_PerfMonCtl1__EventSelect_MASK                                                                0x000000FFL
10572 #define UMCCH7_3_PerfMonCtl1__RdWrMask_MASK                                                                   0x00000300L
10573 #define UMCCH7_3_PerfMonCtl1__PriorityMask_MASK                                                               0x00003C00L
10574 #define UMCCH7_3_PerfMonCtl1__ReqSizeMask_MASK                                                                0x0000C000L
10575 #define UMCCH7_3_PerfMonCtl1__BankSel_MASK                                                                    0x00FF0000L
10576 #define UMCCH7_3_PerfMonCtl1__VCSel_MASK                                                                      0x1F000000L
10577 #define UMCCH7_3_PerfMonCtl1__SubChanMask_MASK                                                                0x60000000L
10578 #define UMCCH7_3_PerfMonCtl1__Enable_MASK                                                                     0x80000000L
10579 //UMCCH7_3_PerfMonCtr1_Lo
10580 #define UMCCH7_3_PerfMonCtr1_Lo__Data__SHIFT                                                                  0x0
10581 #define UMCCH7_3_PerfMonCtr1_Lo__Data_MASK                                                                    0xFFFFFFFFL
10582 //UMCCH7_3_PerfMonCtr1_Hi
10583 #define UMCCH7_3_PerfMonCtr1_Hi__Data__SHIFT                                                                  0x0
10584 #define UMCCH7_3_PerfMonCtr1_Hi__Overflow__SHIFT                                                              0x10
10585 #define UMCCH7_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT                                                           0x12
10586 #define UMCCH7_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT                                                             0x14
10587 #define UMCCH7_3_PerfMonCtr1_Hi__Data_MASK                                                                    0x0000FFFFL
10588 #define UMCCH7_3_PerfMonCtr1_Hi__Overflow_MASK                                                                0x00010000L
10589 #define UMCCH7_3_PerfMonCtr1_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10590 #define UMCCH7_3_PerfMonCtr1_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10591 //UMCCH7_3_PerfMonCtl2
10592 #define UMCCH7_3_PerfMonCtl2__EventSelect__SHIFT                                                              0x0
10593 #define UMCCH7_3_PerfMonCtl2__RdWrMask__SHIFT                                                                 0x8
10594 #define UMCCH7_3_PerfMonCtl2__PriorityMask__SHIFT                                                             0xa
10595 #define UMCCH7_3_PerfMonCtl2__ReqSizeMask__SHIFT                                                              0xe
10596 #define UMCCH7_3_PerfMonCtl2__BankSel__SHIFT                                                                  0x10
10597 #define UMCCH7_3_PerfMonCtl2__VCSel__SHIFT                                                                    0x18
10598 #define UMCCH7_3_PerfMonCtl2__SubChanMask__SHIFT                                                              0x1d
10599 #define UMCCH7_3_PerfMonCtl2__Enable__SHIFT                                                                   0x1f
10600 #define UMCCH7_3_PerfMonCtl2__EventSelect_MASK                                                                0x000000FFL
10601 #define UMCCH7_3_PerfMonCtl2__RdWrMask_MASK                                                                   0x00000300L
10602 #define UMCCH7_3_PerfMonCtl2__PriorityMask_MASK                                                               0x00003C00L
10603 #define UMCCH7_3_PerfMonCtl2__ReqSizeMask_MASK                                                                0x0000C000L
10604 #define UMCCH7_3_PerfMonCtl2__BankSel_MASK                                                                    0x00FF0000L
10605 #define UMCCH7_3_PerfMonCtl2__VCSel_MASK                                                                      0x1F000000L
10606 #define UMCCH7_3_PerfMonCtl2__SubChanMask_MASK                                                                0x60000000L
10607 #define UMCCH7_3_PerfMonCtl2__Enable_MASK                                                                     0x80000000L
10608 //UMCCH7_3_PerfMonCtr2_Lo
10609 #define UMCCH7_3_PerfMonCtr2_Lo__Data__SHIFT                                                                  0x0
10610 #define UMCCH7_3_PerfMonCtr2_Lo__Data_MASK                                                                    0xFFFFFFFFL
10611 //UMCCH7_3_PerfMonCtr2_Hi
10612 #define UMCCH7_3_PerfMonCtr2_Hi__Data__SHIFT                                                                  0x0
10613 #define UMCCH7_3_PerfMonCtr2_Hi__Overflow__SHIFT                                                              0x10
10614 #define UMCCH7_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT                                                           0x12
10615 #define UMCCH7_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT                                                             0x14
10616 #define UMCCH7_3_PerfMonCtr2_Hi__Data_MASK                                                                    0x0000FFFFL
10617 #define UMCCH7_3_PerfMonCtr2_Hi__Overflow_MASK                                                                0x00010000L
10618 #define UMCCH7_3_PerfMonCtr2_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10619 #define UMCCH7_3_PerfMonCtr2_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10620 //UMCCH7_3_PerfMonCtl3
10621 #define UMCCH7_3_PerfMonCtl3__EventSelect__SHIFT                                                              0x0
10622 #define UMCCH7_3_PerfMonCtl3__RdWrMask__SHIFT                                                                 0x8
10623 #define UMCCH7_3_PerfMonCtl3__PriorityMask__SHIFT                                                             0xa
10624 #define UMCCH7_3_PerfMonCtl3__ReqSizeMask__SHIFT                                                              0xe
10625 #define UMCCH7_3_PerfMonCtl3__BankSel__SHIFT                                                                  0x10
10626 #define UMCCH7_3_PerfMonCtl3__VCSel__SHIFT                                                                    0x18
10627 #define UMCCH7_3_PerfMonCtl3__SubChanMask__SHIFT                                                              0x1d
10628 #define UMCCH7_3_PerfMonCtl3__Enable__SHIFT                                                                   0x1f
10629 #define UMCCH7_3_PerfMonCtl3__EventSelect_MASK                                                                0x000000FFL
10630 #define UMCCH7_3_PerfMonCtl3__RdWrMask_MASK                                                                   0x00000300L
10631 #define UMCCH7_3_PerfMonCtl3__PriorityMask_MASK                                                               0x00003C00L
10632 #define UMCCH7_3_PerfMonCtl3__ReqSizeMask_MASK                                                                0x0000C000L
10633 #define UMCCH7_3_PerfMonCtl3__BankSel_MASK                                                                    0x00FF0000L
10634 #define UMCCH7_3_PerfMonCtl3__VCSel_MASK                                                                      0x1F000000L
10635 #define UMCCH7_3_PerfMonCtl3__SubChanMask_MASK                                                                0x60000000L
10636 #define UMCCH7_3_PerfMonCtl3__Enable_MASK                                                                     0x80000000L
10637 //UMCCH7_3_PerfMonCtr3_Lo
10638 #define UMCCH7_3_PerfMonCtr3_Lo__Data__SHIFT                                                                  0x0
10639 #define UMCCH7_3_PerfMonCtr3_Lo__Data_MASK                                                                    0xFFFFFFFFL
10640 //UMCCH7_3_PerfMonCtr3_Hi
10641 #define UMCCH7_3_PerfMonCtr3_Hi__Data__SHIFT                                                                  0x0
10642 #define UMCCH7_3_PerfMonCtr3_Hi__Overflow__SHIFT                                                              0x10
10643 #define UMCCH7_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT                                                           0x12
10644 #define UMCCH7_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT                                                             0x14
10645 #define UMCCH7_3_PerfMonCtr3_Hi__Data_MASK                                                                    0x0000FFFFL
10646 #define UMCCH7_3_PerfMonCtr3_Hi__Overflow_MASK                                                                0x00010000L
10647 #define UMCCH7_3_PerfMonCtr3_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10648 #define UMCCH7_3_PerfMonCtr3_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10649 //UMCCH7_3_PerfMonCtl4
10650 #define UMCCH7_3_PerfMonCtl4__EventSelect__SHIFT                                                              0x0
10651 #define UMCCH7_3_PerfMonCtl4__RdWrMask__SHIFT                                                                 0x8
10652 #define UMCCH7_3_PerfMonCtl4__PriorityMask__SHIFT                                                             0xa
10653 #define UMCCH7_3_PerfMonCtl4__ReqSizeMask__SHIFT                                                              0xe
10654 #define UMCCH7_3_PerfMonCtl4__BankSel__SHIFT                                                                  0x10
10655 #define UMCCH7_3_PerfMonCtl4__VCSel__SHIFT                                                                    0x18
10656 #define UMCCH7_3_PerfMonCtl4__SubChanMask__SHIFT                                                              0x1d
10657 #define UMCCH7_3_PerfMonCtl4__Enable__SHIFT                                                                   0x1f
10658 #define UMCCH7_3_PerfMonCtl4__EventSelect_MASK                                                                0x000000FFL
10659 #define UMCCH7_3_PerfMonCtl4__RdWrMask_MASK                                                                   0x00000300L
10660 #define UMCCH7_3_PerfMonCtl4__PriorityMask_MASK                                                               0x00003C00L
10661 #define UMCCH7_3_PerfMonCtl4__ReqSizeMask_MASK                                                                0x0000C000L
10662 #define UMCCH7_3_PerfMonCtl4__BankSel_MASK                                                                    0x00FF0000L
10663 #define UMCCH7_3_PerfMonCtl4__VCSel_MASK                                                                      0x1F000000L
10664 #define UMCCH7_3_PerfMonCtl4__SubChanMask_MASK                                                                0x60000000L
10665 #define UMCCH7_3_PerfMonCtl4__Enable_MASK                                                                     0x80000000L
10666 //UMCCH7_3_PerfMonCtr4_Lo
10667 #define UMCCH7_3_PerfMonCtr4_Lo__Data__SHIFT                                                                  0x0
10668 #define UMCCH7_3_PerfMonCtr4_Lo__Data_MASK                                                                    0xFFFFFFFFL
10669 //UMCCH7_3_PerfMonCtr4_Hi
10670 #define UMCCH7_3_PerfMonCtr4_Hi__Data__SHIFT                                                                  0x0
10671 #define UMCCH7_3_PerfMonCtr4_Hi__Overflow__SHIFT                                                              0x10
10672 #define UMCCH7_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT                                                           0x12
10673 #define UMCCH7_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT                                                             0x14
10674 #define UMCCH7_3_PerfMonCtr4_Hi__Data_MASK                                                                    0x0000FFFFL
10675 #define UMCCH7_3_PerfMonCtr4_Hi__Overflow_MASK                                                                0x00010000L
10676 #define UMCCH7_3_PerfMonCtr4_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10677 #define UMCCH7_3_PerfMonCtr4_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10678 //UMCCH7_3_PerfMonCtl5
10679 #define UMCCH7_3_PerfMonCtl5__EventSelect__SHIFT                                                              0x0
10680 #define UMCCH7_3_PerfMonCtl5__RdWrMask__SHIFT                                                                 0x8
10681 #define UMCCH7_3_PerfMonCtl5__PriorityMask__SHIFT                                                             0xa
10682 #define UMCCH7_3_PerfMonCtl5__ReqSizeMask__SHIFT                                                              0xe
10683 #define UMCCH7_3_PerfMonCtl5__BankSel__SHIFT                                                                  0x10
10684 #define UMCCH7_3_PerfMonCtl5__VCSel__SHIFT                                                                    0x18
10685 #define UMCCH7_3_PerfMonCtl5__SubChanMask__SHIFT                                                              0x1d
10686 #define UMCCH7_3_PerfMonCtl5__Enable__SHIFT                                                                   0x1f
10687 #define UMCCH7_3_PerfMonCtl5__EventSelect_MASK                                                                0x000000FFL
10688 #define UMCCH7_3_PerfMonCtl5__RdWrMask_MASK                                                                   0x00000300L
10689 #define UMCCH7_3_PerfMonCtl5__PriorityMask_MASK                                                               0x00003C00L
10690 #define UMCCH7_3_PerfMonCtl5__ReqSizeMask_MASK                                                                0x0000C000L
10691 #define UMCCH7_3_PerfMonCtl5__BankSel_MASK                                                                    0x00FF0000L
10692 #define UMCCH7_3_PerfMonCtl5__VCSel_MASK                                                                      0x1F000000L
10693 #define UMCCH7_3_PerfMonCtl5__SubChanMask_MASK                                                                0x60000000L
10694 #define UMCCH7_3_PerfMonCtl5__Enable_MASK                                                                     0x80000000L
10695 //UMCCH7_3_PerfMonCtr5_Lo
10696 #define UMCCH7_3_PerfMonCtr5_Lo__Data__SHIFT                                                                  0x0
10697 #define UMCCH7_3_PerfMonCtr5_Lo__Data_MASK                                                                    0xFFFFFFFFL
10698 //UMCCH7_3_PerfMonCtr5_Hi
10699 #define UMCCH7_3_PerfMonCtr5_Hi__Data__SHIFT                                                                  0x0
10700 #define UMCCH7_3_PerfMonCtr5_Hi__Overflow__SHIFT                                                              0x10
10701 #define UMCCH7_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT                                                           0x12
10702 #define UMCCH7_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT                                                             0x14
10703 #define UMCCH7_3_PerfMonCtr5_Hi__Data_MASK                                                                    0x0000FFFFL
10704 #define UMCCH7_3_PerfMonCtr5_Hi__Overflow_MASK                                                                0x00010000L
10705 #define UMCCH7_3_PerfMonCtr5_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10706 #define UMCCH7_3_PerfMonCtr5_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10707 //UMCCH7_3_PerfMonCtl6
10708 #define UMCCH7_3_PerfMonCtl6__EventSelect__SHIFT                                                              0x0
10709 #define UMCCH7_3_PerfMonCtl6__RdWrMask__SHIFT                                                                 0x8
10710 #define UMCCH7_3_PerfMonCtl6__PriorityMask__SHIFT                                                             0xa
10711 #define UMCCH7_3_PerfMonCtl6__ReqSizeMask__SHIFT                                                              0xe
10712 #define UMCCH7_3_PerfMonCtl6__BankSel__SHIFT                                                                  0x10
10713 #define UMCCH7_3_PerfMonCtl6__VCSel__SHIFT                                                                    0x18
10714 #define UMCCH7_3_PerfMonCtl6__SubChanMask__SHIFT                                                              0x1d
10715 #define UMCCH7_3_PerfMonCtl6__Enable__SHIFT                                                                   0x1f
10716 #define UMCCH7_3_PerfMonCtl6__EventSelect_MASK                                                                0x000000FFL
10717 #define UMCCH7_3_PerfMonCtl6__RdWrMask_MASK                                                                   0x00000300L
10718 #define UMCCH7_3_PerfMonCtl6__PriorityMask_MASK                                                               0x00003C00L
10719 #define UMCCH7_3_PerfMonCtl6__ReqSizeMask_MASK                                                                0x0000C000L
10720 #define UMCCH7_3_PerfMonCtl6__BankSel_MASK                                                                    0x00FF0000L
10721 #define UMCCH7_3_PerfMonCtl6__VCSel_MASK                                                                      0x1F000000L
10722 #define UMCCH7_3_PerfMonCtl6__SubChanMask_MASK                                                                0x60000000L
10723 #define UMCCH7_3_PerfMonCtl6__Enable_MASK                                                                     0x80000000L
10724 //UMCCH7_3_PerfMonCtr6_Lo
10725 #define UMCCH7_3_PerfMonCtr6_Lo__Data__SHIFT                                                                  0x0
10726 #define UMCCH7_3_PerfMonCtr6_Lo__Data_MASK                                                                    0xFFFFFFFFL
10727 //UMCCH7_3_PerfMonCtr6_Hi
10728 #define UMCCH7_3_PerfMonCtr6_Hi__Data__SHIFT                                                                  0x0
10729 #define UMCCH7_3_PerfMonCtr6_Hi__Overflow__SHIFT                                                              0x10
10730 #define UMCCH7_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT                                                           0x12
10731 #define UMCCH7_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT                                                             0x14
10732 #define UMCCH7_3_PerfMonCtr6_Hi__Data_MASK                                                                    0x0000FFFFL
10733 #define UMCCH7_3_PerfMonCtr6_Hi__Overflow_MASK                                                                0x00010000L
10734 #define UMCCH7_3_PerfMonCtr6_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10735 #define UMCCH7_3_PerfMonCtr6_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10736 //UMCCH7_3_PerfMonCtl7
10737 #define UMCCH7_3_PerfMonCtl7__EventSelect__SHIFT                                                              0x0
10738 #define UMCCH7_3_PerfMonCtl7__RdWrMask__SHIFT                                                                 0x8
10739 #define UMCCH7_3_PerfMonCtl7__PriorityMask__SHIFT                                                             0xa
10740 #define UMCCH7_3_PerfMonCtl7__ReqSizeMask__SHIFT                                                              0xe
10741 #define UMCCH7_3_PerfMonCtl7__BankSel__SHIFT                                                                  0x10
10742 #define UMCCH7_3_PerfMonCtl7__VCSel__SHIFT                                                                    0x18
10743 #define UMCCH7_3_PerfMonCtl7__SubChanMask__SHIFT                                                              0x1d
10744 #define UMCCH7_3_PerfMonCtl7__Enable__SHIFT                                                                   0x1f
10745 #define UMCCH7_3_PerfMonCtl7__EventSelect_MASK                                                                0x000000FFL
10746 #define UMCCH7_3_PerfMonCtl7__RdWrMask_MASK                                                                   0x00000300L
10747 #define UMCCH7_3_PerfMonCtl7__PriorityMask_MASK                                                               0x00003C00L
10748 #define UMCCH7_3_PerfMonCtl7__ReqSizeMask_MASK                                                                0x0000C000L
10749 #define UMCCH7_3_PerfMonCtl7__BankSel_MASK                                                                    0x00FF0000L
10750 #define UMCCH7_3_PerfMonCtl7__VCSel_MASK                                                                      0x1F000000L
10751 #define UMCCH7_3_PerfMonCtl7__SubChanMask_MASK                                                                0x60000000L
10752 #define UMCCH7_3_PerfMonCtl7__Enable_MASK                                                                     0x80000000L
10753 //UMCCH7_3_PerfMonCtr7_Lo
10754 #define UMCCH7_3_PerfMonCtr7_Lo__Data__SHIFT                                                                  0x0
10755 #define UMCCH7_3_PerfMonCtr7_Lo__Data_MASK                                                                    0xFFFFFFFFL
10756 //UMCCH7_3_PerfMonCtr7_Hi
10757 #define UMCCH7_3_PerfMonCtr7_Hi__Data__SHIFT                                                                  0x0
10758 #define UMCCH7_3_PerfMonCtr7_Hi__Overflow__SHIFT                                                              0x10
10759 #define UMCCH7_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT                                                           0x12
10760 #define UMCCH7_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT                                                             0x14
10761 #define UMCCH7_3_PerfMonCtr7_Hi__Data_MASK                                                                    0x0000FFFFL
10762 #define UMCCH7_3_PerfMonCtr7_Hi__Overflow_MASK                                                                0x00010000L
10763 #define UMCCH7_3_PerfMonCtr7_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10764 #define UMCCH7_3_PerfMonCtr7_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10765 //UMCCH7_3_PerfMonCtl8
10766 #define UMCCH7_3_PerfMonCtl8__EventSelect__SHIFT                                                              0x0
10767 #define UMCCH7_3_PerfMonCtl8__RdWrMask__SHIFT                                                                 0x8
10768 #define UMCCH7_3_PerfMonCtl8__PriorityMask__SHIFT                                                             0xa
10769 #define UMCCH7_3_PerfMonCtl8__ReqSizeMask__SHIFT                                                              0xe
10770 #define UMCCH7_3_PerfMonCtl8__BankSel__SHIFT                                                                  0x10
10771 #define UMCCH7_3_PerfMonCtl8__VCSel__SHIFT                                                                    0x18
10772 #define UMCCH7_3_PerfMonCtl8__SubChanMask__SHIFT                                                              0x1d
10773 #define UMCCH7_3_PerfMonCtl8__Enable__SHIFT                                                                   0x1f
10774 #define UMCCH7_3_PerfMonCtl8__EventSelect_MASK                                                                0x000000FFL
10775 #define UMCCH7_3_PerfMonCtl8__RdWrMask_MASK                                                                   0x00000300L
10776 #define UMCCH7_3_PerfMonCtl8__PriorityMask_MASK                                                               0x00003C00L
10777 #define UMCCH7_3_PerfMonCtl8__ReqSizeMask_MASK                                                                0x0000C000L
10778 #define UMCCH7_3_PerfMonCtl8__BankSel_MASK                                                                    0x00FF0000L
10779 #define UMCCH7_3_PerfMonCtl8__VCSel_MASK                                                                      0x1F000000L
10780 #define UMCCH7_3_PerfMonCtl8__SubChanMask_MASK                                                                0x60000000L
10781 #define UMCCH7_3_PerfMonCtl8__Enable_MASK                                                                     0x80000000L
10782 //UMCCH7_3_PerfMonCtr8_Lo
10783 #define UMCCH7_3_PerfMonCtr8_Lo__Data__SHIFT                                                                  0x0
10784 #define UMCCH7_3_PerfMonCtr8_Lo__Data_MASK                                                                    0xFFFFFFFFL
10785 //UMCCH7_3_PerfMonCtr8_Hi
10786 #define UMCCH7_3_PerfMonCtr8_Hi__Data__SHIFT                                                                  0x0
10787 #define UMCCH7_3_PerfMonCtr8_Hi__Overflow__SHIFT                                                              0x10
10788 #define UMCCH7_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT                                                           0x12
10789 #define UMCCH7_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT                                                             0x14
10790 #define UMCCH7_3_PerfMonCtr8_Hi__Data_MASK                                                                    0x0000FFFFL
10791 #define UMCCH7_3_PerfMonCtr8_Hi__Overflow_MASK                                                                0x00010000L
10792 #define UMCCH7_3_PerfMonCtr8_Hi__ThreshCntEn_MASK                                                             0x000C0000L
10793 #define UMCCH7_3_PerfMonCtr8_Hi__ThreshCnt_MASK                                                               0xFFF00000L
10794 
10795 
10796 #endif
10797