Searched refs:UMC (Results 1 – 12 of 12) sorted by relevance
103 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()106 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()111 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()114 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()181 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT); in umc_v6_1_query_correctable_error_count()183 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT); in umc_v6_1_query_correctable_error_count()185 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT); in umc_v6_1_query_correctable_error_count()189 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); in umc_v6_1_query_correctable_error_count()191 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); in umc_v6_1_query_correctable_error_count()193 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_1_query_correctable_error_count()[all …]
74 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_IPIDT0); in umc_v6_7_query_error_status_helper()81 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_SYNDT0); in umc_v6_7_query_error_status_helper()88 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_MISC0T0); in umc_v6_7_query_error_status_helper()274 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel); in umc_v6_7_query_correctable_error_count()276 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt); in umc_v6_7_query_correctable_error_count()278 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_query_correctable_error_count()316 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v6_7_query_correctable_error_count()345 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_querry_uncorrectable_error_count()371 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()374 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()[all …]
187 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_clear_error_count_per_channel()189 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_clear_error_count_per_channel()245 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_query_correctable_error_count()247 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_query_correctable_error_count()249 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_correctable_error_count()288 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_querry_uncorrectable_error_count()336 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_error_address()338 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v8_7_query_error_address()397 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_err_cnt_init_per_channel()399 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_err_cnt_init_per_channel()
88 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); in umc_v8_10_clear_error_count_per_channel()112 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_correctable_error_count()130 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_uncorrectable_error_count()256 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_error_address()273 mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v8_10_query_error_address()304 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel); in umc_v8_10_err_cnt_init_per_channel()306 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); in umc_v8_10_err_cnt_init_per_channel()
58 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); in umc_v12_0_reset_error_count_per_channel()126 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v12_0_query_error_count_per_type()341 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v12_0_query_error_address()359 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v12_0_query_error_address()403 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel); in umc_v12_0_err_cnt_init_per_channel()405 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); in umc_v12_0_err_cnt_init_per_channel()
46 ACA_BANK_HWID(UMC, 0x96, 0x00),
199 and each GPU data fabric contains four Unified Memory Controllers (UMC).200 Each UMC contains eight channels. Each UMC channel controls one 128-bit204 While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC210 GPU UMC -> EDAC CSROW211 GPU UMC channel -> EDAC CHANNEL218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.221 - CPU UMCs use 1 channel, In this case UMC = EDAC channel. This follows the223 - CPU UMCs use up to 4 chip selects, So UMC chip select = EDAC CSROW.224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.[all …]
15 UMC 486SX-S and the NexGen Nx586.23 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.58 AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5S.65 486DX/DX2/DX4 and UMC U5D.487 bool "Support UMC processors" if PROCESSOR_SELECT490 This enables detection, tunings and quirks for UMC processors493 UMC CPU. Disabling this option on other types of CPUs494 makes the kernel a tiny bit smaller. Disabling it on a UMC
2221 UMC = 0x02, enumerator
4324 return UMC; in be_convert_mc_type()5760 case UMC: in mc_name()
2724 MCA_BANK_IPID(UMC, 0x96, 0x0),
1031 0x80000022, 0, ebx, 21:16, n_pmc_umc , Number of available UMC performan…