Searched refs:TxINT_ENAB (Results 1 – 10 of 10) sorted by relevance
459 zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB); in zs_stop_rx()787 zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB; in zs_startup()1160 if (txint & TxINT_ENAB) { in zs_console_write()1161 zport->regs[1] = txint & ~TxINT_ENAB; in zs_console_write()1180 if (txint & TxINT_ENAB) { in zs_console_write()1181 zport->regs[1] |= TxINT_ENAB; in zs_console_write()
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
178 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in __load_zsregs()724 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in __ip22zilog_startup()785 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in ip22zilog_shutdown()1136 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in ip22zilog_prepare()
197 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in __load_zsregs()790 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in __sunzilog_startup()851 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in sunzilog_shutdown()1344 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in sunzilog_init_hw()1360 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in sunzilog_init_hw()
151 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
125 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in pmz_load_zsregs()199 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; in pmz_interrupt_control()203 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in pmz_interrupt_control()1881 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); in pmz_console_write()
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
879 or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */ in init_channel()917 or(scc, R1, TxINT_ENAB); /* t_maxkeyup may have reset these */ in scc_key_trx()1253 cl(scc, R1, TxINT_ENAB); /* force an ABORT, but don't */ in t_maxkeyup()