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Searched refs:TRANSCONF (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Ddisplay.c70 if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled()
86 if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE) in pipe_is_enabled()
194 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &= in emulate_monitor_status_change()
255 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
256 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; in emulate_monitor_status_change()
516 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
Dhandlers.c2274 MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL, in init_generic_mmio_info()
2276 MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL, in init_generic_mmio_info()
2278 MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL, in init_generic_mmio_info()
2280 MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL, in init_generic_mmio_info()
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_pch_display.c274 pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)); in ilk_enable_pch_transcoder()
417 u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5; in ilk_pch_enable()
562 TRANSCONF(dev_priv, cpu_transcoder)); in lpt_enable_pch_transcoder()
Dintel_crt.c729 TRANSCONF(dev_priv, cpu_transcoder)); in intel_crt_load_detect()
731 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_crt_load_detect()
734 TRANSCONF(dev_priv, cpu_transcoder)); in intel_crt_load_detect()
743 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_crt_load_detect()
Dintel_display.c312 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_wait_for_pipe_off()
335 TRANSCONF(dev_priv, cpu_transcoder)); in assert_transcoder()
459 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in intel_enable_transcoder()
474 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_enable_transcoder()
476 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in intel_enable_transcoder()
505 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in intel_disable_transcoder()
525 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); in intel_disable_transcoder()
2829 TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; in intel_pipe_is_interlaced()
2832 TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; in intel_pipe_is_interlaced()
2984 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); in i9xx_set_pipeconf()
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Dintel_fdi.c1040 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_pll_enable()
1096 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_disable()
1122 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_disable()
Dicl_dsi.c1020 intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0, in gen11_dsi_enable_transcoder()
1024 if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans), in gen11_dsi_enable_transcoder()
1287 intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), in gen11_dsi_disable_transcoder()
1291 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans), in gen11_dsi_disable_transcoder()
1726 tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans)); in gen11_dsi_get_hw_state()
Dintel_display_power_well.c1051 if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1053 if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1067 return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1068 intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; in i830_pipes_power_well_enabled()
Dintel_drrs.c88 intel_de_rmw(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_drrs_set_refresh_rate_pipeconf()
Dvlv_dsi.c976 TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
/linux-6.12.1/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c133 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
134 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B)); in iterate_generic_mmio()
135 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C)); in iterate_generic_mmio()
136 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP)); in iterate_generic_mmio()
Di915_reg.h1698 #define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) macro