Searched refs:TILE_SPLIT (Results 1 – 16 of 16) sorted by relevance
81 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v6_0_tiling_mode_table_init()415 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v6_0_tiling_mode_table_init()423 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()435 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()442 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v6_0_tiling_mode_table_init()450 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()458 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | in gfx_v6_0_tiling_mode_table_init()470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()478 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()[all …]
70 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro2090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()2098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v8_0_tiling_mode_table_init()2102 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v8_0_tiling_mode_table_init()2106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2262 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()[all …]
1018 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1022 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v7_0_tiling_mode_table_init()1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v7_0_tiling_mode_table_init()1030 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v7_0_tiling_mode_table_init()1035 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1042 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1043 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1057 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1073 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1093 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()[all …]
191 # define TILE_SPLIT(x) ((x) << 11) macro
1022 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1195 # define TILE_SPLIT(x) ((x) << 11) macro
1962 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1931 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1992 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2042 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2508 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in si_tiling_mode_table_init()2526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2535 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2544 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2553 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2562 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2571 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2580 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()[all …]
2360 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2364 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2368 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2372 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); in cik_tiling_mode_table_init()2376 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2383 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2387 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2503 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2507 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2511 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()[all …]
1198 # define TILE_SPLIT(x) ((x) << 11) macro
1240 # define TILE_SPLIT(x) ((x) << 11) macro
189 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
1730 typedef enum TILE_SPLIT { enum1738 } TILE_SPLIT; typedef