Home
last modified time | relevance | path

Searched refs:TEGRA20_CLK_PLL_A_OUT0 (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dtegra20-car.h136 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra20.c434 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
689 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
1031 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
1032 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1033 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra20-plutux.dts58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-tec.dts67 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-medcom-wide.dts93 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-trimslice.dts493 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-ventana.dts720 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-paz00.dts730 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-harmony.dts759 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-colibri.dtsi774 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-seaboard.dts918 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20.dtsi404 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
Dtegra20-asus-tf101.dts1203 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-acer-a500-picasso.dts1435 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,