Searched refs:TEGRA186_SID_NVENC (Results 1 – 3 of 3) sorted by relevance
15 #define TEGRA186_SID_NVENC 0x07 macro
212 .sid = TEGRA186_SID_NVENC,242 .sid = TEGRA186_SID_NVENC,
1740 iommus = <&smmu TEGRA186_SID_NVENC>;