Searched refs:TEGRA186_CLK_PLL_A_OUT0 (Results 1 – 2 of 2) sorted by relevance
153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;355 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;367 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;[all …]
712 #define TEGRA186_CLK_PLL_A_OUT0 246 macro