Searched refs:TEGRA186_CLK_PLLP_OUT0 (Results 1 – 2 of 2) sorted by relevance
748 #define TEGRA186_CLK_PLLP_OUT0 269 macro
138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;873 <&bpmp TEGRA186_CLK_PLLP_OUT0>;874 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;978 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,