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Searched refs:SZ_4K (Results 1 – 25 of 336) sorted by relevance

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/linux-6.12.1/fs/btrfs/tests/
Dextent-map-tests.c101 em->len = SZ_4K; in test_case_1()
103 em->disk_num_bytes = SZ_4K; in test_case_1()
104 em->ram_bytes = SZ_4K; in test_case_1()
199 em->start = SZ_4K; in test_case_2()
200 em->len = SZ_4K; in test_case_2()
201 em->disk_bytenr = SZ_4K; in test_case_2()
202 em->disk_num_bytes = SZ_4K; in test_case_2()
203 em->ram_bytes = SZ_4K; in test_case_2()
259 u64 len = SZ_4K; in __test_case_3()
270 em->start = SZ_4K; in __test_case_3()
[all …]
/linux-6.12.1/drivers/gpu/drm/etnaviv/
Detnaviv_iommu_v2.c56 dma_free_wc(context->global->dev, SZ_4K, in etnaviv_iommuv2_free()
61 dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu, in etnaviv_iommuv2_free()
76 dma_alloc_wc(v2_context->base.global->dev, SZ_4K, in etnaviv_iommuv2_ensure_stlb()
84 SZ_4K / sizeof(u32)); in etnaviv_iommuv2_ensure_stlb()
100 if (size != SZ_4K) in etnaviv_iommuv2_map()
127 if (size != SZ_4K) in etnaviv_iommuv2_unmap()
135 return SZ_4K; in etnaviv_iommuv2_unmap()
141 size_t dump_size = SZ_4K; in etnaviv_iommuv2_dump_size()
146 dump_size += SZ_4K; in etnaviv_iommuv2_dump_size()
156 memcpy(buf, v2_context->mtlb_cpu, SZ_4K); in etnaviv_iommuv2_dump()
[all …]
Detnaviv_iommu.c52 unsigned int index = (iova - GPU_MEM_START) / SZ_4K; in etnaviv_iommuv1_map()
54 if (size != SZ_4K) in etnaviv_iommuv1_map()
66 unsigned int index = (iova - GPU_MEM_START) / SZ_4K; in etnaviv_iommuv1_unmap()
68 if (size != SZ_4K) in etnaviv_iommuv1_unmap()
73 return SZ_4K; in etnaviv_iommuv1_unmap()
165 drm_mm_init(&context->mm, GPU_MEM_START, PT_ENTRIES * SZ_4K); in etnaviv_iommuv1_context_alloc()
Detnaviv_mmu.c20 size_t pgsize = SZ_4K; in etnaviv_context_unmap()
44 size_t pgsize = SZ_4K; in etnaviv_context_map()
515 global->bad_page_cpu = dma_alloc_wc(dev, SZ_4K, &global->bad_page_dma, in etnaviv_iommu_global_init()
520 memset32(global->bad_page_cpu, 0xdead55aa, SZ_4K / sizeof(u32)); in etnaviv_iommu_global_init()
544 dma_free_wc(dev, SZ_4K, global->bad_page_cpu, global->bad_page_dma); in etnaviv_iommu_global_init()
567 dma_free_wc(global->dev, SZ_4K, in etnaviv_iommu_global_fini()
/linux-6.12.1/arch/arm64/kernel/
Dvmlinux.lds.S89 . = ALIGN(SZ_4K); \
325 . += SZ_4K; /* stack for the early C runtime */
360 ASSERT(__idmap_text_end - (__idmap_text_start & ~(SZ_4K - 1)) <= SZ_4K,
363 ASSERT(__hibernate_exit_text_end - __hibernate_exit_text_start <= SZ_4K,
390 ASSERT(__relocate_new_kernel_end - __relocate_new_kernel_start <= SZ_4K,
392 ASSERT(KEXEC_CONTROL_PAGE_SIZE >= SZ_4K, "KEXEC_CONTROL_PAGE_SIZE is broken")
Dmodule-plts.c19 add = aarch64_insn_gen_add_sub_imm(reg, reg, dst % SZ_4K, in __get_adrp_add_pair()
55 p = ALIGN_DOWN((u64)a, SZ_4K); in plt_entries_equal()
56 q = ALIGN_DOWN((u64)b, SZ_4K); in plt_entries_equal()
229 if (min_align > SZ_4K) in count_plts()
243 ret += DIV_ROUND_UP(ret, (SZ_4K / sizeof(struct plt_entry))); in count_plts()
/linux-6.12.1/arch/arm/mach-s3c/
Ddevs.c84 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
114 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
146 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
176 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
207 [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
242 [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
299 DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K),
Ds3c64xx.c102 .length = SZ_4K,
107 .length = SZ_4K,
112 .length = SZ_4K,
132 .length = SZ_4K,
137 .length = SZ_4K,
142 .length = SZ_4K,
/linux-6.12.1/arch/arm/mach-tegra/
Diomap.h23 #define TEGRA_ARM_INT_DIST_SIZE SZ_4K
41 #define TEGRA_CLK_RESET_SIZE SZ_4K
50 #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
53 #define TEGRA_APB_MISC_SIZE SZ_4K
/linux-6.12.1/arch/powerpc/include/asm/nohash/32/
Dpte-8xx.h154 return SZ_4K; in __pte_leaf_size()
178 return PAGE_SIZE / SZ_4K; in number_of_cells_per_pte()
180 return SZ_4M / SZ_4K; in number_of_cells_per_pte()
182 return SZ_16K / SZ_4K; in number_of_cells_per_pte()
184 return SZ_512K / SZ_4K; in number_of_cells_per_pte()
198 for (i = 0; i < num; i += PAGE_SIZE / SZ_4K, new += PAGE_SIZE) { in __pte_update()
/linux-6.12.1/drivers/mtd/nand/raw/
Dnand_ids.c34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
66 SZ_4K, SZ_1K, SZ_256K, 0, 5, 256, NAND_ECC_INFO(8, SZ_512)},
/linux-6.12.1/arch/arm64/crypto/
Dcrct10dif-ce-glue.c43 if (chunk > SZ_4K + CRC_T10DIF_PMULL_CHUNK_SIZE) in crct10dif_update_pmull_p8()
44 chunk = SZ_4K; in crct10dif_update_pmull_p8()
68 if (chunk > SZ_4K + CRC_T10DIF_PMULL_CHUNK_SIZE) in crct10dif_update_pmull_p64()
69 chunk = SZ_4K; in crct10dif_update_pmull_p64()
/linux-6.12.1/drivers/gpu/drm/tests/
Ddrm_buddy_test.c36 ps = max(SZ_4K, ps); in drm_test_buddy_alloc_range_bias()
265 const unsigned long ps = SZ_4K; in drm_test_buddy_alloc_clear()
275 mm_size = SZ_4K << max_order; in drm_test_buddy_alloc_clear()
368 size = SZ_4K << order; in drm_test_buddy_alloc_clear()
392 mm_size = 12 * SZ_4K; in drm_test_buddy_alloc_clear()
405 const unsigned long ps = SZ_4K, mm_size = 16 * 3 * SZ_4K; in drm_test_buddy_alloc_contiguous()
508 mm_size = SZ_4K << max_order; in drm_test_buddy_alloc_pathological()
509 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), in drm_test_buddy_alloc_pathological()
587 mm_size = SZ_4K << max_order; in drm_test_buddy_alloc_pessimistic()
588 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), in drm_test_buddy_alloc_pessimistic()
[all …]
/linux-6.12.1/arch/arm/mach-versatile/
Dintegrator_cp.c41 .length = SZ_4K,
46 .length = SZ_4K,
51 .length = SZ_4K,
/linux-6.12.1/drivers/cxl/core/
Dregs.c482 if (!request_mem_region(rcrb, SZ_4K, dev_name(dev))) in cxl_rcrb_to_aer()
485 addr = ioremap(rcrb, SZ_4K); in cxl_rcrb_to_aer()
504 release_mem_region(rcrb, SZ_4K); in cxl_rcrb_to_aer()
520 rcrb += SZ_4K; in __rcrb_to_component()
528 if (!request_mem_region(rcrb, SZ_4K, "CXL RCRB")) in __rcrb_to_component()
530 addr = ioremap(rcrb, SZ_4K); in __rcrb_to_component()
533 release_mem_region(rcrb, SZ_4K); in __rcrb_to_component()
542 release_mem_region(rcrb, SZ_4K); in __rcrb_to_component()
/linux-6.12.1/drivers/iommu/
Domap-iommu.h215 ((bytes) >= SZ_4K) ? SZ_4K : 0)
221 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
227 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
/linux-6.12.1/drivers/misc/keba/
Dcp500.c63 .startup = { 0x0000, SZ_4K },
64 .i2c = { 0x4000, SZ_4K },
69 .startup = { 0x0000, SZ_4K },
70 .i2c = { 0x5000, SZ_4K },
75 .startup = { 0x0000, SZ_4K },
76 .i2c = { 0x5000, SZ_4K },
/linux-6.12.1/drivers/gpu/drm/meson/
Dmeson_rdma.c29 dma_alloc_coherent(priv->dev, SZ_4K, in meson_rdma_init()
55 dma_free_coherent(priv->dev, SZ_4K, in meson_rdma_free()
94 if (priv->rdma.offset >= (SZ_4K / RDMA_DESC_SIZE)) { in meson_rdma_writel()
/linux-6.12.1/rust/kernel/
Dsizes.rs12 pub const SZ_4K: usize = bindings::SZ_4K as usize; constant
/linux-6.12.1/arch/arm/mach-davinci/
Dpm.c133 pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); in davinci_pm_init()
137 pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); in davinci_pm_init()
143 pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); in davinci_pm_init()
/linux-6.12.1/arch/arm/mach-nomadik/
Dcpu-8815.c64 .length = SZ_4K,
76 void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K); in cpu8815_restart()
/linux-6.12.1/arch/x86/crypto/
Dblake2s-glue.c32 BUILD_BUG_ON(SZ_4K / BLAKE2S_BLOCK_SIZE < 8); in blake2s_compress()
41 SZ_4K / BLAKE2S_BLOCK_SIZE); in blake2s_compress()
/linux-6.12.1/drivers/acpi/arm64/
Dgtdt.c215 timer_mem->size = SZ_4K; in gtdt_parse_timer_block()
265 frame->size = SZ_4K; in gtdt_parse_timer_block()
339 DEFINE_RES_MEM(wd->control_frame_address, SZ_4K), in gtdt_import_sbsa_gwdt()
340 DEFINE_RES_MEM(wd->refresh_frame_address, SZ_4K), in gtdt_import_sbsa_gwdt()
/linux-6.12.1/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_io.h21 #define HINIC_DB_PAGE_SIZE SZ_4K
23 #define HINIC_HW_WQ_PAGE_SIZE SZ_4K
/linux-6.12.1/sound/soc/intel/avs/
Dicl.c69 u8 rsvd[SZ_4K];
71 u8 slot_array[AVS_ICL_MEMWND2_SLOTS_COUNT][SZ_4K];
95 return offsetof(struct avs_icl_memwnd2, slot_array) + i * SZ_4K; in avs_icl_slot_offset()

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