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Searched refs:SWD_CLK_DIV_CTRL_SEL (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/arch/arm/mach-omap1/
Dclock.c549 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_enable_generic()
570 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_enable_generic()
594 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_disable_generic()
615 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_disable_generic()
Dclock.h175 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 macro
Dclock_data.c536 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),