Home
last modified time | relevance | path

Searched refs:SW1 (Results 1 – 25 of 33) sorted by relevance

12

/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr9a07g044c2-smarc.dts11 * DIP-Switch SW1 setting on SoM
13 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
14 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
15 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
16 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
17 * Please change below macros according to SW1 setting
40 * - Set DIP-Switch SW1-4 to Off position.
Dr9a07g043u11-smarc.dts11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
22 * - Set DIP-Switch SW1-3 to On position.
Drzg2l-smarc-som.dtsi12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
17 * SW1[2] should be at position 3/ON.
262 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
265 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
266 * SW1[2] should be at position 3/ON to enable uSD card CN3
Drzg2lc-smarc-som.dtsi180 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
183 * SW1[2] should be at OFF position to enable 64 GB eMMC
184 * SW1[2] should be at position ON to enable uSD card CN3
Drzg2l-smarc.dtsi164 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
Drzg2lc-smarc.dtsi181 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
/linux-6.12.1/arch/riscv/boot/dts/renesas/
Dr9a07g043f01-smarc.dts11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a7779-marzen.dts66 label = "SW1-1";
73 label = "SW1-2";
89 label = "SW1-3";
95 label = "SW1-4";
Dr8a7742-iwg21d-q7-dbcm-ca.dts238 * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
270 /* Set SW1 switch on the SOM to 'ON' */
Dr7s72100-rskrza1.dts84 label = "SW1";
Dsh73a0-kzm9g.dts143 label = "SW1";
/linux-6.12.1/Documentation/hid/
Dhid-alps.rst114 1 0 0 SW6 SW5 SW4 SW3 SW2 SW1
148 SW1-SW6:
164 Byte1 1 1 1 0 1 SW3 SW2 SW1
173 SW1-SW3:
/linux-6.12.1/Documentation/devicetree/bindings/regulator/
Dpv88060.txt11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
84 SW1 {
/linux-6.12.1/Documentation/networking/
Darcnet-hardware.rst803 < | SW1 | | SW2 | |
829 SW1 1-6: I/O Base Address Select
889 The first six switches in switch group SW1 are used to select one
932 Switches seven through ten of switch group SW1 are used to select the
1063 SW1: DIP-Switches for Station Address
1085 The station address is binary-coded with SW1.
1341 | | 90C65 || SW1 | ____|
1419 The last three switches in switch block SW1 are used to select one
1442 Switches 1-5 of switch block SW1 select the Memory Base address.
1554 < | PROM | | SW1 | A | 2 | ID3
[all …]
/linux-6.12.1/drivers/regulator/
Dpcap-regulator.c131 VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
228 VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
Dcpcap-regulator.c330 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
406 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
Dpv88060-regulator.c217 PV88060_SW(PV88060, SW1, 5000000),
Dltc3676.c225 LTC3676_LINEAR_REG(SW1, sw1, BUCK1, DVB1A),
Dltc3589.c254 LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
Dmc13892-regulator.c267 MC13892_SW_DEFINE(SW1, sw1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
/linux-6.12.1/include/linux/mfd/
Dezx-pcap.h130 #define SW1 17 macro
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx53-qsrb.dts35 regulator-name = "SW1";
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dat91-kizbox3-hs.dts72 label = "SW1";
/linux-6.12.1/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt86 sw1 : regulator SW1 (register 24, bit 0)
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-odroid-n2.dtsi291 * The SW1 slide should also be set to the correct position.

12