/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/ |
D | dcn35_hubbub.h | 33 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 34 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 35 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 37 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 38 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ 39 SR(DCHUBBUB_ARB_SAT_LEVEL),\ 40 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ 41 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 42 SR(DCHUBBUB_SOFT_RESET),\ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
D | dce_hwseq.h | 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 129 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 130 SR(DCFEV_CLOCK_CONTROL), \ 139 SR(BLNDV_CONTROL),\ 180 SR(DCHUB_FB_LOCATION),\ 181 SR(DCHUB_AGP_BASE),\ 182 SR(DCHUB_AGP_BOT),\ 183 SR(DCHUB_AGP_TOP) 195 SR(REFCLK_CNTL), \ 196 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_dmcu.h | 33 SR(DMCU_CTRL), \ 34 SR(DMCU_STATUS), \ 35 SR(DMCU_RAM_ACCESS_CTRL), \ 36 SR(DMCU_IRAM_WR_CTRL), \ 37 SR(DMCU_IRAM_WR_DATA), \ 38 SR(MASTER_COMM_DATA_REG1), \ 39 SR(MASTER_COMM_DATA_REG2), \ 40 SR(MASTER_COMM_DATA_REG3), \ 41 SR(MASTER_COMM_CMD_REG), \ 42 SR(MASTER_COMM_CNTL_REG), \ [all …]
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D | dce_abm.h | 33 SR(MASTER_COMM_CNTL_REG), \ 34 SR(MASTER_COMM_CMD_REG), \ 35 SR(MASTER_COMM_DATA_REG1) 39 SR(DC_ABM1_HG_SAMPLE_RATE), \ 40 SR(DC_ABM1_LS_SAMPLE_RATE), \ 41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 42 SR(DC_ABM1_HG_MISC_CTRL), \ 43 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 45 SR(BL1_PWM_TARGET_ABM_LEVEL), \ [all …]
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D | dce_panel_cntl.h | 39 SR(BL_PWM_CNTL), \ 40 SR(BL_PWM_CNTL2), \ 41 SR(BL_PWM_PERIOD_CNTL), \ 42 SR(BL_PWM_GRP1_REG_LOCK), \ 43 SR(BIOS_SCRATCH_2) 53 SR(BL_PWM_CNTL), \ 54 SR(BL_PWM_CNTL2), \ 55 SR(BL_PWM_PERIOD_CNTL), \ 56 SR(BL_PWM_GRP1_REG_LOCK), \
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D | dce_link_encoder.h | 48 SR(DMCU_RAM_ACCESS_CTRL), \ 49 SR(DMCU_IRAM_RD_CTRL), \ 50 SR(DMCU_IRAM_RD_DATA), \ 51 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 77 SR(DCI_MEM_PWR_STATUS) 82 SR(DMCU_RAM_ACCESS_CTRL), \ 83 SR(DMCU_IRAM_RD_CTRL), \ 84 SR(DMCU_IRAM_RD_DATA), \ 85 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 115 SR(DCI_MEM_PWR_STATUS) [all …]
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D | dce_audio.h | 33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\ 34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\ 35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\ 36 SR(DCCG_AUDIO_DTO_SOURCE),\ 37 SR(DCCG_AUDIO_DTO0_MODULE),\ 38 SR(DCCG_AUDIO_DTO0_PHASE),\ 39 SR(DCCG_AUDIO_DTO1_MODULE),\ 40 SR(DCCG_AUDIO_DTO1_PHASE)
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
D | dcn30_dwb.h | 31 SR(DWB_ENABLE_CLK_CTRL),\ 32 SR(DWB_MEM_PWR_CTRL),\ 33 SR(FC_MODE_CTRL),\ 34 SR(FC_FLOW_CTRL),\ 35 SR(FC_WINDOW_START),\ 36 SR(FC_WINDOW_SIZE),\ 37 SR(FC_SOURCE_SIZE),\ 38 SR(DWB_UPDATE_CTRL),\ 39 SR(DWB_CRC_CTRL),\ 40 SR(DWB_CRC_MASK_R_G),\ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/ |
D | dcn31_hubbub.h | 33 SR(DCHVM_CTRL0),\ 34 SR(DCHVM_MEM_CTRL),\ 35 SR(DCHVM_CLK_CTRL),\ 36 SR(DCHVM_RIOMMU_CTRL0),\ 37 SR(DCHVM_RIOMMU_STAT0),\ 38 SR(DCHUBBUB_DET0_CTRL),\ 39 SR(DCHUBBUB_DET1_CTRL),\ 40 SR(DCHUBBUB_DET2_CTRL),\ 41 SR(DCHUBBUB_DET3_CTRL),\ 42 SR(DCHUBBUB_COMPBUF_CTRL),\ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
D | dcn35_resource.h | 162 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 163 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 164 SR(DIO_MEM_PWR_CTRL), \ 165 SR(ODM_MEM_PWR_CTRL3), \ 166 SR(MMHUBBUB_MEM_PWR_CNTL), \ 167 SR(DCCG_GATE_DISABLE_CNTL), \ 168 SR(DCCG_GATE_DISABLE_CNTL2), \ 169 SR(DCCG_GATE_DISABLE_CNTL4), \ 170 SR(DCCG_GATE_DISABLE_CNTL5), \ 171 SR(DCFCLK_CNTL),\ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
D | dcn35_pg_cntl.h | 33 SR(DOMAIN0_PG_CONFIG), \ 34 SR(DOMAIN1_PG_CONFIG), \ 35 SR(DOMAIN2_PG_CONFIG), \ 36 SR(DOMAIN3_PG_CONFIG), \ 37 SR(DOMAIN16_PG_CONFIG), \ 38 SR(DOMAIN17_PG_CONFIG), \ 39 SR(DOMAIN18_PG_CONFIG), \ 40 SR(DOMAIN19_PG_CONFIG), \ 41 SR(DOMAIN22_PG_CONFIG), \ 42 SR(DOMAIN23_PG_CONFIG), \ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
D | dcn401_resource.h | 544 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A), \ 545 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B), \ 546 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL), \ 547 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), \ 548 SR(DCHUBBUB_ARB_SAT_LEVEL), \ 549 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), \ 550 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 551 SR(DCHUBBUB_TEST_DEBUG_INDEX), \ 552 SR(DCHUBBUB_TEST_DEBUG_DATA), \ 553 SR(DCHUBBUB_SOFT_RESET), \ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/ |
D | dcn21_hubbub.h | 31 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ 32 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ 33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ 34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ 35 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ 36 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ 37 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ 38 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ 39 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ 40 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
D | dcn314_dccg.h | 37 SR(DPPCLK_DTO_CTRL),\ 43 SR(PHYASYMCLK_CLOCK_CNTL),\ 44 SR(PHYBSYMCLK_CLOCK_CNTL),\ 45 SR(PHYCSYMCLK_CLOCK_CNTL),\ 46 SR(PHYDSYMCLK_CLOCK_CNTL),\ 47 SR(PHYESYMCLK_CLOCK_CNTL),\ 48 SR(DPSTREAMCLK_CNTL),\ 49 SR(HDMISTREAMCLK_CNTL),\ 50 SR(SYMCLK32_SE_CNTL),\ 51 SR(SYMCLK32_LE_CNTL),\ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/ |
D | dcn10_hubbub.h | 36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 37 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ 38 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 39 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ 40 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ 42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 43 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ 44 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 45 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/ |
D | dcn20_hubbub.h | 37 SR(DCHUBBUB_CRC_CTRL), \ 38 SR(DCN_VM_FB_LOCATION_BASE),\ 39 SR(DCN_VM_FB_LOCATION_TOP),\ 40 SR(DCN_VM_FB_OFFSET),\ 41 SR(DCN_VM_AGP_BOT),\ 42 SR(DCN_VM_AGP_TOP),\ 43 SR(DCN_VM_AGP_BASE),\ 44 SR(DCN_VM_FAULT_ADDR_MSB), \ 45 SR(DCN_VM_FAULT_ADDR_LSB), \ 46 SR(DCN_VM_FAULT_CNTL), \ [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
D | dcn31_dccg.h | 32 SR(DPPCLK_DTO_CTRL),\ 38 SR(PHYASYMCLK_CLOCK_CNTL),\ 39 SR(PHYBSYMCLK_CLOCK_CNTL),\ 40 SR(PHYCSYMCLK_CLOCK_CNTL),\ 41 SR(PHYDSYMCLK_CLOCK_CNTL),\ 42 SR(PHYESYMCLK_CLOCK_CNTL),\ 43 SR(DPSTREAMCLK_CNTL),\ 44 SR(HDMISTREAMCLK_CNTL),\ 45 SR(SYMCLK32_SE_CNTL),\ 46 SR(SYMCLK32_LE_CNTL),\ [all …]
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/linux-6.12.1/Documentation/translations/zh_CN/PCI/ |
D | pci-iov-howto.rst | 28 什么是SR-IOV 31 单根I/O虚拟化(SR-IOV)是一种PCI Express扩展功能,它使一个物理设备显示为多个 42 我怎样才能启用SR-IOV功能 45 有多种方法可用于SR-IOV的启用。在第一种方法中,设备驱动(PF驱动)将通过SR-IOV 46 核心提供的API控制功能的启用和禁用。如果硬件具有SR-IOV能力,加载其PF驱动器将启 63 SR-IOV API 66 用来开启SR-IOV功能: 79 用来关闭SR-IOV功能: 90 要想通过主机上的兼容驱动启用自动探测VF,在启用SR-IOV功能之前运行下面的命令。这 97 要禁止主机上的兼容驱动自动探测VF,请在启用SR-IOV功能之前运行以下命令。更新这个 [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/ |
D | dcn30_hubbub.h | 40 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ 41 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ 42 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ 43 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ 44 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ 45 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ 46 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ 47 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ 48 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ 49 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ [all …]
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/linux-6.12.1/Documentation/networking/ |
D | seg6-sysctl.rst | 12 Accept or drop SR-enabled IPv6 packets on this interface. 20 Define HMAC policy for ingress SR-enabled packets on this interface. 23 * 0 - Accept SR packets without HMAC, validate SR packets with HMAC 24 * 1 - Drop SR packets without HMAC, validate SR packets with HMAC 30 IPv6 header in case of SR T.encaps
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
D | dcn32_resource.h | 785 SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), SR(MPC_OUT_CSC_COEF_FORMAT) 1184 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A), \ 1185 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B), \ 1186 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C), \ 1187 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D), \ 1188 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL), \ 1189 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), SR(DCHUBBUB_ARB_SAT_LEVEL), \ 1190 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 1191 SR(DCHUBBUB_TEST_DEBUG_INDEX), \ 1192 SR(DCHUBBUB_TEST_DEBUG_DATA), \ [all …]
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/linux-6.12.1/Documentation/PCI/ |
D | pci-iov-howto.rst | 15 What is SR-IOV 18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended 34 How can I enable SR-IOV capability 37 Multiple methods are available for SR-IOV enablement. 39 enabling and disabling of the capability via API provided by SR-IOV core. 40 If the hardware has SR-IOV capability, loading its PF driver would 63 SR-IOV API 66 To enable SR-IOV capability: 79 To disable SR-IOV capability: 91 command below before enabling SR-IOV capabilities. This is the [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
D | dcn316_resource.c | 148 #define SR(reg_name)\ macro 673 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 674 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 675 SR(DIO_MEM_PWR_CTRL), \ 676 SR(ODM_MEM_PWR_CTRL3), \ 677 SR(DMU_MEM_PWR_CNTL), \ 678 SR(MMHUBBUB_MEM_PWR_CNTL), \ 679 SR(DCCG_GATE_DISABLE_CNTL), \ 680 SR(DCCG_GATE_DISABLE_CNTL2), \ 681 SR(DCFCLK_CNTL),\ [all …]
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/linux-6.12.1/drivers/macintosh/ |
D | via-cuda.c | 50 #define SR (10*RS) /* Shift register */ macro 343 (void)in_8(&via[SR]); in sync_egret() 358 (void)in_8(&via[SR]); in sync_egret() 386 (void)in_8(&via[SR]); /* clear any left-over data */ in cuda_init_via() 395 (void)in_8(&via[SR]); in cuda_init_via() 406 (void)in_8(&via[SR]); in cuda_init_via() 415 (void)in_8(&via[SR]); in cuda_init_via() 543 out_8(&via[SR], current_req->data[data_index++]); in cuda_start() 596 (void)in_8(&via[SR]); in cuda_interrupt() 606 (void)in_8(&via[SR]); in cuda_interrupt() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
D | dcn314_resource.c | 145 #define SR(reg_name)\ macro 686 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 687 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 688 SR(DIO_MEM_PWR_CTRL), \ 689 SR(ODM_MEM_PWR_CTRL3), \ 690 SR(DMU_MEM_PWR_CNTL), \ 691 SR(MMHUBBUB_MEM_PWR_CNTL), \ 692 SR(DCCG_GATE_DISABLE_CNTL), \ 693 SR(DCCG_GATE_DISABLE_CNTL2), \ 694 SR(DCFCLK_CNTL),\ [all …]
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