1 /* 2 * GFX_7_2 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef GFX_7_2_ENUM_H 25 #define GFX_7_2_ENUM_H 26 27 typedef enum SurfaceNumber { 28 NUMBER_UNORM = 0x0, 29 NUMBER_SNORM = 0x1, 30 NUMBER_USCALED = 0x2, 31 NUMBER_SSCALED = 0x3, 32 NUMBER_UINT = 0x4, 33 NUMBER_SINT = 0x5, 34 NUMBER_SRGB = 0x6, 35 NUMBER_FLOAT = 0x7, 36 } SurfaceNumber; 37 typedef enum SurfaceSwap { 38 SWAP_STD = 0x0, 39 SWAP_ALT = 0x1, 40 SWAP_STD_REV = 0x2, 41 SWAP_ALT_REV = 0x3, 42 } SurfaceSwap; 43 typedef enum CBMode { 44 CB_DISABLE = 0x0, 45 CB_NORMAL = 0x1, 46 CB_ELIMINATE_FAST_CLEAR = 0x2, 47 CB_RESOLVE = 0x3, 48 CB_DECOMPRESS = 0x4, 49 CB_FMASK_DECOMPRESS = 0x5, 50 } CBMode; 51 typedef enum RoundMode { 52 ROUND_BY_HALF = 0x0, 53 ROUND_TRUNCATE = 0x1, 54 } RoundMode; 55 typedef enum SourceFormat { 56 EXPORT_4C_32BPC = 0x0, 57 EXPORT_4C_16BPC = 0x1, 58 EXPORT_2C_32BPC_GR = 0x2, 59 EXPORT_2C_32BPC_AR = 0x3, 60 } SourceFormat; 61 typedef enum BlendOp { 62 BLEND_ZERO = 0x0, 63 BLEND_ONE = 0x1, 64 BLEND_SRC_COLOR = 0x2, 65 BLEND_ONE_MINUS_SRC_COLOR = 0x3, 66 BLEND_SRC_ALPHA = 0x4, 67 BLEND_ONE_MINUS_SRC_ALPHA = 0x5, 68 BLEND_DST_ALPHA = 0x6, 69 BLEND_ONE_MINUS_DST_ALPHA = 0x7, 70 BLEND_DST_COLOR = 0x8, 71 BLEND_ONE_MINUS_DST_COLOR = 0x9, 72 BLEND_SRC_ALPHA_SATURATE = 0xa, 73 BLEND_BOTH_SRC_ALPHA = 0xb, 74 BLEND_BOTH_INV_SRC_ALPHA = 0xc, 75 BLEND_CONSTANT_COLOR = 0xd, 76 BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe, 77 BLEND_SRC1_COLOR = 0xf, 78 BLEND_INV_SRC1_COLOR = 0x10, 79 BLEND_SRC1_ALPHA = 0x11, 80 BLEND_INV_SRC1_ALPHA = 0x12, 81 BLEND_CONSTANT_ALPHA = 0x13, 82 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, 83 } BlendOp; 84 typedef enum CombFunc { 85 COMB_DST_PLUS_SRC = 0x0, 86 COMB_SRC_MINUS_DST = 0x1, 87 COMB_MIN_DST_SRC = 0x2, 88 COMB_MAX_DST_SRC = 0x3, 89 COMB_DST_MINUS_SRC = 0x4, 90 } CombFunc; 91 typedef enum BlendOpt { 92 FORCE_OPT_AUTO = 0x0, 93 FORCE_OPT_DISABLE = 0x1, 94 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2, 95 FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3, 96 FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4, 97 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5, 98 FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6, 99 FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7, 100 } BlendOpt; 101 typedef enum CmaskCode { 102 CMASK_CLR00_F0 = 0x0, 103 CMASK_CLR00_F1 = 0x1, 104 CMASK_CLR00_F2 = 0x2, 105 CMASK_CLR00_FX = 0x3, 106 CMASK_CLR01_F0 = 0x4, 107 CMASK_CLR01_F1 = 0x5, 108 CMASK_CLR01_F2 = 0x6, 109 CMASK_CLR01_FX = 0x7, 110 CMASK_CLR10_F0 = 0x8, 111 CMASK_CLR10_F1 = 0x9, 112 CMASK_CLR10_F2 = 0xa, 113 CMASK_CLR10_FX = 0xb, 114 CMASK_CLR11_F0 = 0xc, 115 CMASK_CLR11_F1 = 0xd, 116 CMASK_CLR11_F2 = 0xe, 117 CMASK_CLR11_FX = 0xf, 118 } CmaskCode; 119 typedef enum CBPerfSel { 120 CB_PERF_SEL_NONE = 0x0, 121 CB_PERF_SEL_BUSY = 0x1, 122 CB_PERF_SEL_CORE_SCLK_VLD = 0x2, 123 CB_PERF_SEL_REG_SCLK0_VLD = 0x3, 124 CB_PERF_SEL_REG_SCLK1_VLD = 0x4, 125 CB_PERF_SEL_DRAWN_QUAD = 0x5, 126 CB_PERF_SEL_DRAWN_PIXEL = 0x6, 127 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7, 128 CB_PERF_SEL_DRAWN_TILE = 0x8, 129 CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9, 130 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, 131 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb, 132 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc, 133 CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd, 134 CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe, 135 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf, 136 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10, 137 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11, 138 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12, 139 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13, 140 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14, 141 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15, 142 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16, 143 CB_PERF_SEL_LQUAD_NO_TILE = 0x17, 144 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18, 145 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19, 146 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a, 147 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b, 148 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c, 149 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, 150 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e, 151 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f, 152 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20, 153 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21, 154 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22, 155 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23, 156 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24, 157 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25, 158 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26, 159 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27, 160 CB_PERF_SEL_FOP_IN_VALID_READY = 0x28, 161 CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29, 162 CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a, 163 CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b, 164 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c, 165 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d, 166 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e, 167 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f, 168 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30, 169 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31, 170 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32, 171 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33, 172 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34, 173 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35, 174 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36, 175 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37, 176 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38, 177 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39, 178 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a, 179 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b, 180 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c, 181 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d, 182 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e, 183 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f, 184 CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40, 185 CB_PERF_SEL_CM_CACHE_HIT = 0x41, 186 CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42, 187 CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43, 188 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44, 189 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45, 190 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46, 191 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47, 192 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48, 193 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49, 194 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a, 195 CB_PERF_SEL_CM_CACHE_STALL = 0x4b, 196 CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c, 197 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d, 198 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e, 199 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f, 200 CB_PERF_SEL_FC_CACHE_HIT = 0x50, 201 CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51, 202 CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52, 203 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53, 204 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54, 205 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55, 206 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56, 207 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57, 208 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58, 209 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59, 210 CB_PERF_SEL_FC_CACHE_STALL = 0x5a, 211 CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b, 212 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c, 213 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d, 214 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e, 215 CB_PERF_SEL_CC_CACHE_HIT = 0x5f, 216 CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60, 217 CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61, 218 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62, 219 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63, 220 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64, 221 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65, 222 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66, 223 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67, 224 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68, 225 CB_PERF_SEL_CC_CACHE_STALL = 0x69, 226 CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a, 227 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b, 228 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c, 229 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d, 230 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e, 231 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x6f, 232 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x70, 233 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x71, 234 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x72, 235 CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x73, 236 CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x74, 237 CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x75, 238 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x76, 239 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77, 240 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78, 241 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x79, 242 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7a, 243 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7b, 244 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7c, 245 CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7d, 246 CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7e, 247 CB_PERF_SEL_CC_MC_READ_REQUEST = 0x7f, 248 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x80, 249 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x81, 250 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x82, 251 CB_PERF_SEL_CM_TQ_FULL = 0x83, 252 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x84, 253 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x85, 254 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x86, 255 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x87, 256 CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x88, 257 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x89, 258 CB_PERF_SEL_CC_SF_FULL = 0x8a, 259 CB_PERF_SEL_CC_RB_FULL = 0x8b, 260 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8c, 261 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8d, 262 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8e, 263 CB_PERF_SEL_EVENT = 0x8f, 264 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x90, 265 CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x91, 266 CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x92, 267 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x93, 268 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x94, 269 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x95, 270 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x96, 271 CB_PERF_SEL_CC_SURFACE_SYNC = 0x97, 272 CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x98, 273 CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x99, 274 CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9a, 275 CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9b, 276 CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9c, 277 CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9d, 278 CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9e, 279 CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x9f, 280 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa0, 281 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa1, 282 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa2, 283 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa3, 284 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa4, 285 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa5, 286 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa6, 287 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa7, 288 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa8, 289 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xa9, 290 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xaa, 291 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xab, 292 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xac, 293 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xad, 294 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xae, 295 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xaf, 296 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb0, 297 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb1, 298 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb2, 299 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb3, 300 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb4, 301 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb5, 302 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb6, 303 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb7, 304 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb8, 305 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xb9, 306 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xba, 307 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbb, 308 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbc, 309 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbd, 310 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbe, 311 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xbf, 312 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc0, 313 CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc1, 314 CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc2, 315 CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc3, 316 CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc4, 317 CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc5, 318 CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc6, 319 CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc7, 320 CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc8, 321 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xc9, 322 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xca, 323 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcb, 324 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcc, 325 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xcd, 326 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xce, 327 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xcf, 328 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd0, 329 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd1, 330 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd2, 331 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd3, 332 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd4, 333 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd5, 334 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd6, 335 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd7, 336 CB_PERF_SEL_DRAWN_BUSY = 0xd8, 337 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xd9, 338 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xda, 339 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdb, 340 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdc, 341 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xdd, 342 CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xde, 343 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xdf, 344 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe0, 345 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe1, 346 } CBPerfSel; 347 typedef enum CBPerfOpFilterSel { 348 CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0, 349 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1, 350 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2, 351 CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3, 352 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4, 353 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5, 354 } CBPerfOpFilterSel; 355 typedef enum CBPerfClearFilterSel { 356 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0, 357 CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1, 358 } CBPerfClearFilterSel; 359 typedef enum CP_RING_ID { 360 RINGID0 = 0x0, 361 RINGID1 = 0x1, 362 RINGID2 = 0x2, 363 RINGID3 = 0x3, 364 } CP_RING_ID; 365 typedef enum CP_PIPE_ID { 366 PIPE_ID0 = 0x0, 367 PIPE_ID1 = 0x1, 368 PIPE_ID2 = 0x2, 369 PIPE_ID3 = 0x3, 370 } CP_PIPE_ID; 371 typedef enum CP_ME_ID { 372 ME_ID0 = 0x0, 373 ME_ID1 = 0x1, 374 ME_ID2 = 0x2, 375 ME_ID3 = 0x3, 376 } CP_ME_ID; 377 typedef enum SPM_PERFMON_STATE { 378 STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0, 379 STRM_PERFMON_STATE_START_COUNTING = 0x1, 380 STRM_PERFMON_STATE_STOP_COUNTING = 0x2, 381 STRM_PERFMON_STATE_RESERVED_3 = 0x3, 382 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, 383 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, 384 } SPM_PERFMON_STATE; 385 typedef enum CP_PERFMON_STATE { 386 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0, 387 CP_PERFMON_STATE_START_COUNTING = 0x1, 388 CP_PERFMON_STATE_STOP_COUNTING = 0x2, 389 CP_PERFMON_STATE_RESERVED_3 = 0x3, 390 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, 391 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, 392 } CP_PERFMON_STATE; 393 typedef enum CP_PERFMON_ENABLE_MODE { 394 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0, 395 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1, 396 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2, 397 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3, 398 } CP_PERFMON_ENABLE_MODE; 399 typedef enum CPG_PERFCOUNT_SEL { 400 CPG_PERF_SEL_ALWAYS_COUNT = 0x0, 401 CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1, 402 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2, 403 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3, 404 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4, 405 CPG_PERF_SEL_ME_PARSER_BUSY = 0x5, 406 CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6, 407 CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7, 408 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8, 409 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9, 410 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, 411 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb, 412 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc, 413 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd, 414 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe, 415 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf, 416 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10, 417 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11, 418 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12, 419 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13, 420 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14, 421 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15, 422 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16, 423 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17, 424 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18, 425 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19, 426 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a, 427 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b, 428 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c, 429 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, 430 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e, 431 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f, 432 CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20, 433 CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21, 434 CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22, 435 CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23, 436 CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24, 437 CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25, 438 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26, 439 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27, 440 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28, 441 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29, 442 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a, 443 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b, 444 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c, 445 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d, 446 } CPG_PERFCOUNT_SEL; 447 typedef enum CPF_PERFCOUNT_SEL { 448 CPF_PERF_SEL_ALWAYS_COUNT = 0x0, 449 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1, 450 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2, 451 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3, 452 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4, 453 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5, 454 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6, 455 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7, 456 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8, 457 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9, 458 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, 459 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb, 460 CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc, 461 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd, 462 CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe, 463 CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf, 464 CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10, 465 } CPF_PERFCOUNT_SEL; 466 typedef enum CPC_PERFCOUNT_SEL { 467 CPC_PERF_SEL_ALWAYS_COUNT = 0x0, 468 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1, 469 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2, 470 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3, 471 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4, 472 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5, 473 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6, 474 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7, 475 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8, 476 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9, 477 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, 478 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb, 479 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc, 480 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd, 481 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe, 482 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf, 483 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10, 484 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11, 485 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12, 486 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13, 487 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14, 488 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15, 489 } CPC_PERFCOUNT_SEL; 490 typedef enum CP_ALPHA_TAG_RAM_SEL { 491 CPG_TAG_RAM = 0x0, 492 CPC_TAG_RAM = 0x1, 493 CPF_TAG_RAM = 0x2, 494 RSV_TAG_RAM = 0x3, 495 } CP_ALPHA_TAG_RAM_SEL; 496 #define SEM_ECC_ERROR 0x0 497 #define SEM_RESERVED 0x1 498 #define SEM_FAILED 0x2 499 #define SEM_PASSED 0x3 500 #define IQ_QUEUE_SLEEP 0x0 501 #define IQ_OFFLOAD_RETRY 0x1 502 #define IQ_SCH_WAVE_MSG 0x2 503 #define IQ_SEM_REARM 0x3 504 #define IQ_DEQUEUE_RETRY 0x4 505 #define IQ_INTR_TYPE_PQ 0x0 506 #define IQ_INTR_TYPE_IB 0x1 507 #define IQ_INTR_TYPE_MQD 0x2 508 #define VMID_SZ 0x4 509 #define CONFIG_SPACE_START 0x2000 510 #define CONFIG_SPACE_END 0x9fff 511 #define CONFIG_SPACE1_START 0x2000 512 #define CONFIG_SPACE1_END 0x2bff 513 #define CONFIG_SPACE2_START 0x3000 514 #define CONFIG_SPACE2_END 0x9fff 515 #define UCONFIG_SPACE_START 0xc000 516 #define UCONFIG_SPACE_END 0xffff 517 #define PERSISTENT_SPACE_START 0x2c00 518 #define PERSISTENT_SPACE_END 0x2fff 519 #define CONTEXT_SPACE_START 0xa000 520 #define CONTEXT_SPACE_END 0xbfff 521 typedef enum ForceControl { 522 FORCE_OFF = 0x0, 523 FORCE_ENABLE = 0x1, 524 FORCE_DISABLE = 0x2, 525 FORCE_RESERVED = 0x3, 526 } ForceControl; 527 typedef enum ZSamplePosition { 528 Z_SAMPLE_CENTER = 0x0, 529 Z_SAMPLE_CENTROID = 0x1, 530 } ZSamplePosition; 531 typedef enum ZOrder { 532 LATE_Z = 0x0, 533 EARLY_Z_THEN_LATE_Z = 0x1, 534 RE_Z = 0x2, 535 EARLY_Z_THEN_RE_Z = 0x3, 536 } ZOrder; 537 typedef enum ZpassControl { 538 ZPASS_DISABLE = 0x0, 539 ZPASS_SAMPLES = 0x1, 540 ZPASS_PIXELS = 0x2, 541 } ZpassControl; 542 typedef enum ZModeForce { 543 NO_FORCE = 0x0, 544 FORCE_EARLY_Z = 0x1, 545 FORCE_LATE_Z = 0x2, 546 FORCE_RE_Z = 0x3, 547 } ZModeForce; 548 typedef enum ZLimitSumm { 549 FORCE_SUMM_OFF = 0x0, 550 FORCE_SUMM_MINZ = 0x1, 551 FORCE_SUMM_MAXZ = 0x2, 552 FORCE_SUMM_BOTH = 0x3, 553 } ZLimitSumm; 554 typedef enum CompareFrag { 555 FRAG_NEVER = 0x0, 556 FRAG_LESS = 0x1, 557 FRAG_EQUAL = 0x2, 558 FRAG_LEQUAL = 0x3, 559 FRAG_GREATER = 0x4, 560 FRAG_NOTEQUAL = 0x5, 561 FRAG_GEQUAL = 0x6, 562 FRAG_ALWAYS = 0x7, 563 } CompareFrag; 564 typedef enum StencilOp { 565 STENCIL_KEEP = 0x0, 566 STENCIL_ZERO = 0x1, 567 STENCIL_ONES = 0x2, 568 STENCIL_REPLACE_TEST = 0x3, 569 STENCIL_REPLACE_OP = 0x4, 570 STENCIL_ADD_CLAMP = 0x5, 571 STENCIL_SUB_CLAMP = 0x6, 572 STENCIL_INVERT = 0x7, 573 STENCIL_ADD_WRAP = 0x8, 574 STENCIL_SUB_WRAP = 0x9, 575 STENCIL_AND = 0xa, 576 STENCIL_OR = 0xb, 577 STENCIL_XOR = 0xc, 578 STENCIL_NAND = 0xd, 579 STENCIL_NOR = 0xe, 580 STENCIL_XNOR = 0xf, 581 } StencilOp; 582 typedef enum ConservativeZExport { 583 EXPORT_ANY_Z = 0x0, 584 EXPORT_LESS_THAN_Z = 0x1, 585 EXPORT_GREATER_THAN_Z = 0x2, 586 EXPORT_RESERVED = 0x3, 587 } ConservativeZExport; 588 typedef enum DbPSLControl { 589 PSLC_AUTO = 0x0, 590 PSLC_ON_HANG_ONLY = 0x1, 591 PSLC_ASAP = 0x2, 592 PSLC_COUNTDOWN = 0x3, 593 } DbPSLControl; 594 typedef enum PerfCounter_Vals { 595 DB_PERF_SEL_SC_DB_tile_sends = 0x0, 596 DB_PERF_SEL_SC_DB_tile_busy = 0x1, 597 DB_PERF_SEL_SC_DB_tile_stalls = 0x2, 598 DB_PERF_SEL_SC_DB_tile_events = 0x3, 599 DB_PERF_SEL_SC_DB_tile_tiles = 0x4, 600 DB_PERF_SEL_SC_DB_tile_covered = 0x5, 601 DB_PERF_SEL_hiz_tc_read_starved = 0x6, 602 DB_PERF_SEL_hiz_tc_write_stall = 0x7, 603 DB_PERF_SEL_hiz_qtiles_culled = 0x8, 604 DB_PERF_SEL_his_qtiles_culled = 0x9, 605 DB_PERF_SEL_DB_SC_tile_sends = 0xa, 606 DB_PERF_SEL_DB_SC_tile_busy = 0xb, 607 DB_PERF_SEL_DB_SC_tile_stalls = 0xc, 608 DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd, 609 DB_PERF_SEL_DB_SC_tile_tiles = 0xe, 610 DB_PERF_SEL_DB_SC_tile_culled = 0xf, 611 DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10, 612 DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11, 613 DB_PERF_SEL_DB_SC_tile_no_ops = 0x12, 614 DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13, 615 DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14, 616 DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15, 617 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16, 618 DB_PERF_SEL_SC_DB_quad_sends = 0x17, 619 DB_PERF_SEL_SC_DB_quad_busy = 0x18, 620 DB_PERF_SEL_SC_DB_quad_squads = 0x19, 621 DB_PERF_SEL_SC_DB_quad_tiles = 0x1a, 622 DB_PERF_SEL_SC_DB_quad_pixels = 0x1b, 623 DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c, 624 DB_PERF_SEL_DB_SC_quad_sends = 0x1d, 625 DB_PERF_SEL_DB_SC_quad_busy = 0x1e, 626 DB_PERF_SEL_DB_SC_quad_stalls = 0x1f, 627 DB_PERF_SEL_DB_SC_quad_tiles = 0x20, 628 DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21, 629 DB_PERF_SEL_DB_CB_tile_sends = 0x22, 630 DB_PERF_SEL_DB_CB_tile_busy = 0x23, 631 DB_PERF_SEL_DB_CB_tile_stalls = 0x24, 632 DB_PERF_SEL_SX_DB_quad_sends = 0x25, 633 DB_PERF_SEL_SX_DB_quad_busy = 0x26, 634 DB_PERF_SEL_SX_DB_quad_stalls = 0x27, 635 DB_PERF_SEL_SX_DB_quad_quads = 0x28, 636 DB_PERF_SEL_SX_DB_quad_pixels = 0x29, 637 DB_PERF_SEL_SX_DB_quad_exports = 0x2a, 638 DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b, 639 DB_PERF_SEL_DB_CB_lquad_sends = 0x2c, 640 DB_PERF_SEL_DB_CB_lquad_busy = 0x2d, 641 DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e, 642 DB_PERF_SEL_DB_CB_lquad_quads = 0x2f, 643 DB_PERF_SEL_tile_rd_sends = 0x30, 644 DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31, 645 DB_PERF_SEL_quad_rd_sends = 0x32, 646 DB_PERF_SEL_quad_rd_busy = 0x33, 647 DB_PERF_SEL_quad_rd_mi_stall = 0x34, 648 DB_PERF_SEL_quad_rd_rw_collision = 0x35, 649 DB_PERF_SEL_quad_rd_tag_stall = 0x36, 650 DB_PERF_SEL_quad_rd_32byte_reqs = 0x37, 651 DB_PERF_SEL_quad_rd_panic = 0x38, 652 DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39, 653 DB_PERF_SEL_quad_rdret_sends = 0x3a, 654 DB_PERF_SEL_quad_rdret_busy = 0x3b, 655 DB_PERF_SEL_tile_wr_sends = 0x3c, 656 DB_PERF_SEL_tile_wr_acks = 0x3d, 657 DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e, 658 DB_PERF_SEL_quad_wr_sends = 0x3f, 659 DB_PERF_SEL_quad_wr_busy = 0x40, 660 DB_PERF_SEL_quad_wr_mi_stall = 0x41, 661 DB_PERF_SEL_quad_wr_coherency_stall = 0x42, 662 DB_PERF_SEL_quad_wr_acks = 0x43, 663 DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44, 664 DB_PERF_SEL_Tile_Cache_misses = 0x45, 665 DB_PERF_SEL_Tile_Cache_hits = 0x46, 666 DB_PERF_SEL_Tile_Cache_flushes = 0x47, 667 DB_PERF_SEL_Tile_Cache_surface_stall = 0x48, 668 DB_PERF_SEL_Tile_Cache_starves = 0x49, 669 DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a, 670 DB_PERF_SEL_tcp_dispatcher_reads = 0x4b, 671 DB_PERF_SEL_tcp_prefetcher_reads = 0x4c, 672 DB_PERF_SEL_tcp_preloader_reads = 0x4d, 673 DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e, 674 DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f, 675 DB_PERF_SEL_tcp_preloader_flushes = 0x50, 676 DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51, 677 DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52, 678 DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53, 679 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54, 680 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55, 681 DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56, 682 DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57, 683 DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58, 684 DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59, 685 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a, 686 DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b, 687 DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c, 688 DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d, 689 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e, 690 DB_PERF_SEL_Stencil_Cache_misses = 0x5f, 691 DB_PERF_SEL_Stencil_Cache_hits = 0x60, 692 DB_PERF_SEL_Stencil_Cache_flushes = 0x61, 693 DB_PERF_SEL_Stencil_Cache_starves = 0x62, 694 DB_PERF_SEL_Stencil_Cache_frees = 0x63, 695 DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64, 696 DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65, 697 DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66, 698 DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67, 699 DB_PERF_SEL_Z_Cache_pmask_misses = 0x68, 700 DB_PERF_SEL_Z_Cache_pmask_hits = 0x69, 701 DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a, 702 DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b, 703 DB_PERF_SEL_Z_Cache_frees = 0x6c, 704 DB_PERF_SEL_Plane_Cache_misses = 0x6d, 705 DB_PERF_SEL_Plane_Cache_hits = 0x6e, 706 DB_PERF_SEL_Plane_Cache_flushes = 0x6f, 707 DB_PERF_SEL_Plane_Cache_starves = 0x70, 708 DB_PERF_SEL_Plane_Cache_frees = 0x71, 709 DB_PERF_SEL_flush_expanded_stencil = 0x72, 710 DB_PERF_SEL_flush_compressed_stencil = 0x73, 711 DB_PERF_SEL_flush_single_stencil = 0x74, 712 DB_PERF_SEL_planes_flushed = 0x75, 713 DB_PERF_SEL_flush_1plane = 0x76, 714 DB_PERF_SEL_flush_2plane = 0x77, 715 DB_PERF_SEL_flush_3plane = 0x78, 716 DB_PERF_SEL_flush_4plane = 0x79, 717 DB_PERF_SEL_flush_5plane = 0x7a, 718 DB_PERF_SEL_flush_6plane = 0x7b, 719 DB_PERF_SEL_flush_7plane = 0x7c, 720 DB_PERF_SEL_flush_8plane = 0x7d, 721 DB_PERF_SEL_flush_9plane = 0x7e, 722 DB_PERF_SEL_flush_10plane = 0x7f, 723 DB_PERF_SEL_flush_11plane = 0x80, 724 DB_PERF_SEL_flush_12plane = 0x81, 725 DB_PERF_SEL_flush_13plane = 0x82, 726 DB_PERF_SEL_flush_14plane = 0x83, 727 DB_PERF_SEL_flush_15plane = 0x84, 728 DB_PERF_SEL_flush_16plane = 0x85, 729 DB_PERF_SEL_flush_expanded_z = 0x86, 730 DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87, 731 DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88, 732 DB_PERF_SEL_dk_tile_sends = 0x89, 733 DB_PERF_SEL_dk_tile_busy = 0x8a, 734 DB_PERF_SEL_dk_tile_quad_starves = 0x8b, 735 DB_PERF_SEL_dk_tile_stalls = 0x8c, 736 DB_PERF_SEL_dk_squad_sends = 0x8d, 737 DB_PERF_SEL_dk_squad_busy = 0x8e, 738 DB_PERF_SEL_dk_squad_stalls = 0x8f, 739 DB_PERF_SEL_Op_Pipe_Busy = 0x90, 740 DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91, 741 DB_PERF_SEL_qc_busy = 0x92, 742 DB_PERF_SEL_qc_xfc = 0x93, 743 DB_PERF_SEL_qc_conflicts = 0x94, 744 DB_PERF_SEL_qc_full_stall = 0x95, 745 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96, 746 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97, 747 DB_PERF_SEL_tsc_insert_summarize_stall = 0x98, 748 DB_PERF_SEL_tl_busy = 0x99, 749 DB_PERF_SEL_tl_dtc_read_starved = 0x9a, 750 DB_PERF_SEL_tl_z_fetch_stall = 0x9b, 751 DB_PERF_SEL_tl_stencil_stall = 0x9c, 752 DB_PERF_SEL_tl_z_decompress_stall = 0x9d, 753 DB_PERF_SEL_tl_stencil_locked_stall = 0x9e, 754 DB_PERF_SEL_tl_events = 0x9f, 755 DB_PERF_SEL_tl_summarize_squads = 0xa0, 756 DB_PERF_SEL_tl_flush_expand_squads = 0xa1, 757 DB_PERF_SEL_tl_expand_squads = 0xa2, 758 DB_PERF_SEL_tl_preZ_squads = 0xa3, 759 DB_PERF_SEL_tl_postZ_squads = 0xa4, 760 DB_PERF_SEL_tl_preZ_noop_squads = 0xa5, 761 DB_PERF_SEL_tl_postZ_noop_squads = 0xa6, 762 DB_PERF_SEL_tl_tile_ops = 0xa7, 763 DB_PERF_SEL_tl_in_xfc = 0xa8, 764 DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9, 765 DB_PERF_SEL_tl_in_fast_z_stall = 0xaa, 766 DB_PERF_SEL_tl_out_xfc = 0xab, 767 DB_PERF_SEL_tl_out_squads = 0xac, 768 DB_PERF_SEL_zf_plane_multicycle = 0xad, 769 DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae, 770 DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf, 771 DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0, 772 DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1, 773 DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2, 774 DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3, 775 DB_PERF_SEL_ts_tc_update_stall = 0xb4, 776 DB_PERF_SEL_sc_kick_start = 0xb5, 777 DB_PERF_SEL_sc_kick_end = 0xb6, 778 DB_PERF_SEL_clock_reg_active = 0xb7, 779 DB_PERF_SEL_clock_main_active = 0xb8, 780 DB_PERF_SEL_clock_mem_export_active = 0xb9, 781 DB_PERF_SEL_esr_ps_out_busy = 0xba, 782 DB_PERF_SEL_esr_ps_lqf_busy = 0xbb, 783 DB_PERF_SEL_esr_ps_lqf_stall = 0xbc, 784 DB_PERF_SEL_etr_out_send = 0xbd, 785 DB_PERF_SEL_etr_out_busy = 0xbe, 786 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf, 787 DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0, 788 DB_PERF_SEL_etr_out_esr_stall = 0xc1, 789 DB_PERF_SEL_esr_ps_sqq_busy = 0xc2, 790 DB_PERF_SEL_esr_ps_sqq_stall = 0xc3, 791 DB_PERF_SEL_esr_eot_fwd_busy = 0xc4, 792 DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5, 793 DB_PERF_SEL_esr_eot_fwd_forward = 0xc6, 794 DB_PERF_SEL_esr_sqq_zi_busy = 0xc7, 795 DB_PERF_SEL_esr_sqq_zi_stall = 0xc8, 796 DB_PERF_SEL_postzl_sq_pt_busy = 0xc9, 797 DB_PERF_SEL_postzl_sq_pt_stall = 0xca, 798 DB_PERF_SEL_postzl_se_busy = 0xcb, 799 DB_PERF_SEL_postzl_se_stall = 0xcc, 800 DB_PERF_SEL_postzl_partial_launch = 0xcd, 801 DB_PERF_SEL_postzl_full_launch = 0xce, 802 DB_PERF_SEL_postzl_partial_waiting = 0xcf, 803 DB_PERF_SEL_postzl_tile_mem_stall = 0xd0, 804 DB_PERF_SEL_postzl_tile_init_stall = 0xd1, 805 DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2, 806 DB_PERF_SEL_prezl_tile_init_stall = 0xd3, 807 DB_PERF_SEL_dtt_sm_clash_stall = 0xd4, 808 DB_PERF_SEL_dtt_sm_slot_stall = 0xd5, 809 DB_PERF_SEL_dtt_sm_miss_stall = 0xd6, 810 DB_PERF_SEL_mi_rdreq_busy = 0xd7, 811 DB_PERF_SEL_mi_rdreq_stall = 0xd8, 812 DB_PERF_SEL_mi_wrreq_busy = 0xd9, 813 DB_PERF_SEL_mi_wrreq_stall = 0xda, 814 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb, 815 DB_PERF_SEL_dkg_tile_rate_tile = 0xdc, 816 DB_PERF_SEL_prezl_src_in_sends = 0xdd, 817 DB_PERF_SEL_prezl_src_in_stall = 0xde, 818 DB_PERF_SEL_prezl_src_in_squads = 0xdf, 819 DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0, 820 DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1, 821 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2, 822 DB_PERF_SEL_prezl_src_out_stall = 0xe3, 823 DB_PERF_SEL_postzl_src_in_sends = 0xe4, 824 DB_PERF_SEL_postzl_src_in_stall = 0xe5, 825 DB_PERF_SEL_postzl_src_in_squads = 0xe6, 826 DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7, 827 DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8, 828 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9, 829 DB_PERF_SEL_postzl_src_out_stall = 0xea, 830 DB_PERF_SEL_esr_ps_src_in_sends = 0xeb, 831 DB_PERF_SEL_esr_ps_src_in_stall = 0xec, 832 DB_PERF_SEL_esr_ps_src_in_squads = 0xed, 833 DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee, 834 DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef, 835 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0, 836 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1, 837 DB_PERF_SEL_esr_ps_src_out_stall = 0xf2, 838 DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3, 839 DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4, 840 DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5, 841 DB_PERF_SEL_flush_compressed = 0xf6, 842 DB_PERF_SEL_flush_plane_le4 = 0xf7, 843 DB_PERF_SEL_tiles_z_fully_summarized = 0xf8, 844 DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9, 845 DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa, 846 DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb, 847 DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc, 848 DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd, 849 DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe, 850 DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff, 851 DB_PERF_SEL_di_dt_stall = 0x100, 852 } PerfCounter_Vals; 853 typedef enum RingCounterControl { 854 COUNTER_RING_SPLIT = 0x0, 855 COUNTER_RING_0 = 0x1, 856 COUNTER_RING_1 = 0x2, 857 } RingCounterControl; 858 typedef enum PixelPipeCounterId { 859 PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0, 860 PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1, 861 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2, 862 PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3, 863 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4, 864 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5, 865 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6, 866 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7, 867 } PixelPipeCounterId; 868 typedef enum PixelPipeStride { 869 PIXEL_PIPE_STRIDE_32_BITS = 0x0, 870 PIXEL_PIPE_STRIDE_64_BITS = 0x1, 871 PIXEL_PIPE_STRIDE_128_BITS = 0x2, 872 PIXEL_PIPE_STRIDE_256_BITS = 0x3, 873 } PixelPipeStride; 874 typedef enum GB_EDC_DED_MODE { 875 GB_EDC_DED_MODE_LOG = 0x0, 876 GB_EDC_DED_MODE_HALT = 0x1, 877 GB_EDC_DED_MODE_INT_HALT = 0x2, 878 } GB_EDC_DED_MODE; 879 #define GB_TILING_CONFIG_TABLE_SIZE 0x20 880 #define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10 881 typedef enum GRBM_PERF_SEL { 882 GRBM_PERF_SEL_COUNT = 0x0, 883 GRBM_PERF_SEL_USER_DEFINED = 0x1, 884 GRBM_PERF_SEL_GUI_ACTIVE = 0x2, 885 GRBM_PERF_SEL_CP_BUSY = 0x3, 886 GRBM_PERF_SEL_CP_COHER_BUSY = 0x4, 887 GRBM_PERF_SEL_CP_DMA_BUSY = 0x5, 888 GRBM_PERF_SEL_CB_BUSY = 0x6, 889 GRBM_PERF_SEL_DB_BUSY = 0x7, 890 GRBM_PERF_SEL_PA_BUSY = 0x8, 891 GRBM_PERF_SEL_SC_BUSY = 0x9, 892 GRBM_PERF_SEL_RESERVED_6 = 0xa, 893 GRBM_PERF_SEL_SPI_BUSY = 0xb, 894 GRBM_PERF_SEL_SX_BUSY = 0xc, 895 GRBM_PERF_SEL_TA_BUSY = 0xd, 896 GRBM_PERF_SEL_CB_CLEAN = 0xe, 897 GRBM_PERF_SEL_DB_CLEAN = 0xf, 898 GRBM_PERF_SEL_RESERVED_5 = 0x10, 899 GRBM_PERF_SEL_VGT_BUSY = 0x11, 900 GRBM_PERF_SEL_RESERVED_4 = 0x12, 901 GRBM_PERF_SEL_RESERVED_3 = 0x13, 902 GRBM_PERF_SEL_RESERVED_2 = 0x14, 903 GRBM_PERF_SEL_RESERVED_1 = 0x15, 904 GRBM_PERF_SEL_RESERVED_0 = 0x16, 905 GRBM_PERF_SEL_IA_BUSY = 0x17, 906 GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18, 907 GRBM_PERF_SEL_GDS_BUSY = 0x19, 908 GRBM_PERF_SEL_BCI_BUSY = 0x1a, 909 GRBM_PERF_SEL_RLC_BUSY = 0x1b, 910 GRBM_PERF_SEL_TC_BUSY = 0x1c, 911 GRBM_PERF_SEL_CPG_BUSY = 0x1d, 912 GRBM_PERF_SEL_CPC_BUSY = 0x1e, 913 GRBM_PERF_SEL_CPF_BUSY = 0x1f, 914 GRBM_PERF_SEL_WD_BUSY = 0x20, 915 GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21, 916 } GRBM_PERF_SEL; 917 typedef enum GRBM_SE0_PERF_SEL { 918 GRBM_SE0_PERF_SEL_COUNT = 0x0, 919 GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1, 920 GRBM_SE0_PERF_SEL_CB_BUSY = 0x2, 921 GRBM_SE0_PERF_SEL_DB_BUSY = 0x3, 922 GRBM_SE0_PERF_SEL_SC_BUSY = 0x4, 923 GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5, 924 GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6, 925 GRBM_SE0_PERF_SEL_SX_BUSY = 0x7, 926 GRBM_SE0_PERF_SEL_TA_BUSY = 0x8, 927 GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9, 928 GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, 929 GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb, 930 GRBM_SE0_PERF_SEL_PA_BUSY = 0xc, 931 GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd, 932 GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe, 933 } GRBM_SE0_PERF_SEL; 934 typedef enum GRBM_SE1_PERF_SEL { 935 GRBM_SE1_PERF_SEL_COUNT = 0x0, 936 GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1, 937 GRBM_SE1_PERF_SEL_CB_BUSY = 0x2, 938 GRBM_SE1_PERF_SEL_DB_BUSY = 0x3, 939 GRBM_SE1_PERF_SEL_SC_BUSY = 0x4, 940 GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5, 941 GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6, 942 GRBM_SE1_PERF_SEL_SX_BUSY = 0x7, 943 GRBM_SE1_PERF_SEL_TA_BUSY = 0x8, 944 GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9, 945 GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa, 946 GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb, 947 GRBM_SE1_PERF_SEL_PA_BUSY = 0xc, 948 GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd, 949 GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe, 950 } GRBM_SE1_PERF_SEL; 951 typedef enum GRBM_SE2_PERF_SEL { 952 GRBM_SE2_PERF_SEL_COUNT = 0x0, 953 GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1, 954 GRBM_SE2_PERF_SEL_CB_BUSY = 0x2, 955 GRBM_SE2_PERF_SEL_DB_BUSY = 0x3, 956 GRBM_SE2_PERF_SEL_SC_BUSY = 0x4, 957 GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5, 958 GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6, 959 GRBM_SE2_PERF_SEL_SX_BUSY = 0x7, 960 GRBM_SE2_PERF_SEL_TA_BUSY = 0x8, 961 GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9, 962 GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa, 963 GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb, 964 GRBM_SE2_PERF_SEL_PA_BUSY = 0xc, 965 GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd, 966 GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe, 967 } GRBM_SE2_PERF_SEL; 968 typedef enum GRBM_SE3_PERF_SEL { 969 GRBM_SE3_PERF_SEL_COUNT = 0x0, 970 GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1, 971 GRBM_SE3_PERF_SEL_CB_BUSY = 0x2, 972 GRBM_SE3_PERF_SEL_DB_BUSY = 0x3, 973 GRBM_SE3_PERF_SEL_SC_BUSY = 0x4, 974 GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5, 975 GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6, 976 GRBM_SE3_PERF_SEL_SX_BUSY = 0x7, 977 GRBM_SE3_PERF_SEL_TA_BUSY = 0x8, 978 GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9, 979 GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa, 980 GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb, 981 GRBM_SE3_PERF_SEL_PA_BUSY = 0xc, 982 GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd, 983 GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe, 984 } GRBM_SE3_PERF_SEL; 985 typedef enum SU_PERFCNT_SEL { 986 PERF_PAPC_PASX_REQ = 0x0, 987 PERF_PAPC_PASX_DISABLE_PIPE = 0x1, 988 PERF_PAPC_PASX_FIRST_VECTOR = 0x2, 989 PERF_PAPC_PASX_SECOND_VECTOR = 0x3, 990 PERF_PAPC_PASX_FIRST_DEAD = 0x4, 991 PERF_PAPC_PASX_SECOND_DEAD = 0x5, 992 PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6, 993 PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7, 994 PERF_PAPC_PA_INPUT_PRIM = 0x8, 995 PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9, 996 PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa, 997 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb, 998 PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc, 999 PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd, 1000 PERF_PAPC_CLPR_CULL_PRIM = 0xe, 1001 PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf, 1002 PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10, 1003 PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11, 1004 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12, 1005 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13, 1006 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14, 1007 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15, 1008 PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16, 1009 PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17, 1010 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18, 1011 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19, 1012 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a, 1013 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b, 1014 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c, 1015 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, 1016 PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e, 1017 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f, 1018 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20, 1019 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21, 1020 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22, 1021 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23, 1022 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24, 1023 PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25, 1024 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26, 1025 PERF_PAPC_CLSM_NULL_PRIM = 0x27, 1026 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28, 1027 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29, 1028 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a, 1029 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b, 1030 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c, 1031 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d, 1032 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e, 1033 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f, 1034 PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30, 1035 PERF_PAPC_SU_INPUT_PRIM = 0x31, 1036 PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32, 1037 PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33, 1038 PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34, 1039 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35, 1040 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36, 1041 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37, 1042 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38, 1043 PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39, 1044 PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a, 1045 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b, 1046 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c, 1047 PERF_PAPC_SU_OUTPUT_PRIM = 0x3d, 1048 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e, 1049 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f, 1050 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40, 1051 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41, 1052 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42, 1053 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43, 1054 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44, 1055 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45, 1056 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46, 1057 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47, 1058 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48, 1059 PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49, 1060 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a, 1061 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b, 1062 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c, 1063 PERF_PAPC_PASX_REQ_IDLE = 0x4d, 1064 PERF_PAPC_PASX_REQ_BUSY = 0x4e, 1065 PERF_PAPC_PASX_REQ_STALLED = 0x4f, 1066 PERF_PAPC_PASX_REC_IDLE = 0x50, 1067 PERF_PAPC_PASX_REC_BUSY = 0x51, 1068 PERF_PAPC_PASX_REC_STARVED_SX = 0x52, 1069 PERF_PAPC_PASX_REC_STALLED = 0x53, 1070 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54, 1071 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55, 1072 PERF_PAPC_CCGSM_IDLE = 0x56, 1073 PERF_PAPC_CCGSM_BUSY = 0x57, 1074 PERF_PAPC_CCGSM_STALLED = 0x58, 1075 PERF_PAPC_CLPRIM_IDLE = 0x59, 1076 PERF_PAPC_CLPRIM_BUSY = 0x5a, 1077 PERF_PAPC_CLPRIM_STALLED = 0x5b, 1078 PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c, 1079 PERF_PAPC_CLIPSM_IDLE = 0x5d, 1080 PERF_PAPC_CLIPSM_BUSY = 0x5e, 1081 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f, 1082 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60, 1083 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61, 1084 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62, 1085 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63, 1086 PERF_PAPC_CLIPGA_IDLE = 0x64, 1087 PERF_PAPC_CLIPGA_BUSY = 0x65, 1088 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66, 1089 PERF_PAPC_CLIPGA_STALLED = 0x67, 1090 PERF_PAPC_CLIP_IDLE = 0x68, 1091 PERF_PAPC_CLIP_BUSY = 0x69, 1092 PERF_PAPC_SU_IDLE = 0x6a, 1093 PERF_PAPC_SU_BUSY = 0x6b, 1094 PERF_PAPC_SU_STARVED_CLIP = 0x6c, 1095 PERF_PAPC_SU_STALLED_SC = 0x6d, 1096 PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e, 1097 PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f, 1098 PERF_PAPC_PA_REG_SCLK_VLD = 0x70, 1099 PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71, 1100 PERF_PAPC_PASX_SE0_REQ = 0x72, 1101 PERF_PAPC_PASX_SE1_REQ = 0x73, 1102 PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74, 1103 PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75, 1104 PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76, 1105 PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77, 1106 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78, 1107 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79, 1108 PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a, 1109 PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b, 1110 PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c, 1111 PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d, 1112 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e, 1113 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f, 1114 PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80, 1115 PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81, 1116 PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82, 1117 PERF_PAPC_SU_SE0_STALLED_SC = 0x83, 1118 PERF_PAPC_SU_SE1_STALLED_SC = 0x84, 1119 PERF_PAPC_SU_SE01_STALLED_SC = 0x85, 1120 PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86, 1121 PERF_PAPC_SU_CULLED_PRIM = 0x87, 1122 PERF_PAPC_SU_OUTPUT_EOPG = 0x88, 1123 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89, 1124 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a, 1125 PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b, 1126 PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c, 1127 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d, 1128 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e, 1129 PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f, 1130 PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90, 1131 PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91, 1132 PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92, 1133 PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93, 1134 PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94, 1135 PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95, 1136 PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96, 1137 PERF_PAPC_SU_SE2_STALLED_SC = 0x97, 1138 PERF_PAPC_SU_SE3_STALLED_SC = 0x98, 1139 } SU_PERFCNT_SEL; 1140 typedef enum SC_PERFCNT_SEL { 1141 SC_SRPS_WINDOW_VALID = 0x0, 1142 SC_PSSW_WINDOW_VALID = 0x1, 1143 SC_TPQZ_WINDOW_VALID = 0x2, 1144 SC_QZQP_WINDOW_VALID = 0x3, 1145 SC_TRPK_WINDOW_VALID = 0x4, 1146 SC_SRPS_WINDOW_VALID_BUSY = 0x5, 1147 SC_PSSW_WINDOW_VALID_BUSY = 0x6, 1148 SC_TPQZ_WINDOW_VALID_BUSY = 0x7, 1149 SC_QZQP_WINDOW_VALID_BUSY = 0x8, 1150 SC_TRPK_WINDOW_VALID_BUSY = 0x9, 1151 SC_STARVED_BY_PA = 0xa, 1152 SC_STALLED_BY_PRIMFIFO = 0xb, 1153 SC_STALLED_BY_DB_TILE = 0xc, 1154 SC_STARVED_BY_DB_TILE = 0xd, 1155 SC_STALLED_BY_TILEORDERFIFO = 0xe, 1156 SC_STALLED_BY_TILEFIFO = 0xf, 1157 SC_STALLED_BY_DB_QUAD = 0x10, 1158 SC_STARVED_BY_DB_QUAD = 0x11, 1159 SC_STALLED_BY_QUADFIFO = 0x12, 1160 SC_STALLED_BY_BCI = 0x13, 1161 SC_STALLED_BY_SPI = 0x14, 1162 SC_SCISSOR_DISCARD = 0x15, 1163 SC_BB_DISCARD = 0x16, 1164 SC_SUPERTILE_COUNT = 0x17, 1165 SC_SUPERTILE_PER_PRIM_H0 = 0x18, 1166 SC_SUPERTILE_PER_PRIM_H1 = 0x19, 1167 SC_SUPERTILE_PER_PRIM_H2 = 0x1a, 1168 SC_SUPERTILE_PER_PRIM_H3 = 0x1b, 1169 SC_SUPERTILE_PER_PRIM_H4 = 0x1c, 1170 SC_SUPERTILE_PER_PRIM_H5 = 0x1d, 1171 SC_SUPERTILE_PER_PRIM_H6 = 0x1e, 1172 SC_SUPERTILE_PER_PRIM_H7 = 0x1f, 1173 SC_SUPERTILE_PER_PRIM_H8 = 0x20, 1174 SC_SUPERTILE_PER_PRIM_H9 = 0x21, 1175 SC_SUPERTILE_PER_PRIM_H10 = 0x22, 1176 SC_SUPERTILE_PER_PRIM_H11 = 0x23, 1177 SC_SUPERTILE_PER_PRIM_H12 = 0x24, 1178 SC_SUPERTILE_PER_PRIM_H13 = 0x25, 1179 SC_SUPERTILE_PER_PRIM_H14 = 0x26, 1180 SC_SUPERTILE_PER_PRIM_H15 = 0x27, 1181 SC_SUPERTILE_PER_PRIM_H16 = 0x28, 1182 SC_TILE_PER_PRIM_H0 = 0x29, 1183 SC_TILE_PER_PRIM_H1 = 0x2a, 1184 SC_TILE_PER_PRIM_H2 = 0x2b, 1185 SC_TILE_PER_PRIM_H3 = 0x2c, 1186 SC_TILE_PER_PRIM_H4 = 0x2d, 1187 SC_TILE_PER_PRIM_H5 = 0x2e, 1188 SC_TILE_PER_PRIM_H6 = 0x2f, 1189 SC_TILE_PER_PRIM_H7 = 0x30, 1190 SC_TILE_PER_PRIM_H8 = 0x31, 1191 SC_TILE_PER_PRIM_H9 = 0x32, 1192 SC_TILE_PER_PRIM_H10 = 0x33, 1193 SC_TILE_PER_PRIM_H11 = 0x34, 1194 SC_TILE_PER_PRIM_H12 = 0x35, 1195 SC_TILE_PER_PRIM_H13 = 0x36, 1196 SC_TILE_PER_PRIM_H14 = 0x37, 1197 SC_TILE_PER_PRIM_H15 = 0x38, 1198 SC_TILE_PER_PRIM_H16 = 0x39, 1199 SC_TILE_PER_SUPERTILE_H0 = 0x3a, 1200 SC_TILE_PER_SUPERTILE_H1 = 0x3b, 1201 SC_TILE_PER_SUPERTILE_H2 = 0x3c, 1202 SC_TILE_PER_SUPERTILE_H3 = 0x3d, 1203 SC_TILE_PER_SUPERTILE_H4 = 0x3e, 1204 SC_TILE_PER_SUPERTILE_H5 = 0x3f, 1205 SC_TILE_PER_SUPERTILE_H6 = 0x40, 1206 SC_TILE_PER_SUPERTILE_H7 = 0x41, 1207 SC_TILE_PER_SUPERTILE_H8 = 0x42, 1208 SC_TILE_PER_SUPERTILE_H9 = 0x43, 1209 SC_TILE_PER_SUPERTILE_H10 = 0x44, 1210 SC_TILE_PER_SUPERTILE_H11 = 0x45, 1211 SC_TILE_PER_SUPERTILE_H12 = 0x46, 1212 SC_TILE_PER_SUPERTILE_H13 = 0x47, 1213 SC_TILE_PER_SUPERTILE_H14 = 0x48, 1214 SC_TILE_PER_SUPERTILE_H15 = 0x49, 1215 SC_TILE_PER_SUPERTILE_H16 = 0x4a, 1216 SC_TILE_PICKED_H1 = 0x4b, 1217 SC_TILE_PICKED_H2 = 0x4c, 1218 SC_TILE_PICKED_H3 = 0x4d, 1219 SC_TILE_PICKED_H4 = 0x4e, 1220 SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f, 1221 SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50, 1222 SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51, 1223 SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52, 1224 SC_QZ0_TILE_COUNT = 0x53, 1225 SC_QZ1_TILE_COUNT = 0x54, 1226 SC_QZ2_TILE_COUNT = 0x55, 1227 SC_QZ3_TILE_COUNT = 0x56, 1228 SC_QZ0_TILE_COVERED_COUNT = 0x57, 1229 SC_QZ1_TILE_COVERED_COUNT = 0x58, 1230 SC_QZ2_TILE_COVERED_COUNT = 0x59, 1231 SC_QZ3_TILE_COVERED_COUNT = 0x5a, 1232 SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b, 1233 SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c, 1234 SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d, 1235 SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e, 1236 SC_QZ0_QUAD_PER_TILE_H0 = 0x5f, 1237 SC_QZ0_QUAD_PER_TILE_H1 = 0x60, 1238 SC_QZ0_QUAD_PER_TILE_H2 = 0x61, 1239 SC_QZ0_QUAD_PER_TILE_H3 = 0x62, 1240 SC_QZ0_QUAD_PER_TILE_H4 = 0x63, 1241 SC_QZ0_QUAD_PER_TILE_H5 = 0x64, 1242 SC_QZ0_QUAD_PER_TILE_H6 = 0x65, 1243 SC_QZ0_QUAD_PER_TILE_H7 = 0x66, 1244 SC_QZ0_QUAD_PER_TILE_H8 = 0x67, 1245 SC_QZ0_QUAD_PER_TILE_H9 = 0x68, 1246 SC_QZ0_QUAD_PER_TILE_H10 = 0x69, 1247 SC_QZ0_QUAD_PER_TILE_H11 = 0x6a, 1248 SC_QZ0_QUAD_PER_TILE_H12 = 0x6b, 1249 SC_QZ0_QUAD_PER_TILE_H13 = 0x6c, 1250 SC_QZ0_QUAD_PER_TILE_H14 = 0x6d, 1251 SC_QZ0_QUAD_PER_TILE_H15 = 0x6e, 1252 SC_QZ0_QUAD_PER_TILE_H16 = 0x6f, 1253 SC_QZ1_QUAD_PER_TILE_H0 = 0x70, 1254 SC_QZ1_QUAD_PER_TILE_H1 = 0x71, 1255 SC_QZ1_QUAD_PER_TILE_H2 = 0x72, 1256 SC_QZ1_QUAD_PER_TILE_H3 = 0x73, 1257 SC_QZ1_QUAD_PER_TILE_H4 = 0x74, 1258 SC_QZ1_QUAD_PER_TILE_H5 = 0x75, 1259 SC_QZ1_QUAD_PER_TILE_H6 = 0x76, 1260 SC_QZ1_QUAD_PER_TILE_H7 = 0x77, 1261 SC_QZ1_QUAD_PER_TILE_H8 = 0x78, 1262 SC_QZ1_QUAD_PER_TILE_H9 = 0x79, 1263 SC_QZ1_QUAD_PER_TILE_H10 = 0x7a, 1264 SC_QZ1_QUAD_PER_TILE_H11 = 0x7b, 1265 SC_QZ1_QUAD_PER_TILE_H12 = 0x7c, 1266 SC_QZ1_QUAD_PER_TILE_H13 = 0x7d, 1267 SC_QZ1_QUAD_PER_TILE_H14 = 0x7e, 1268 SC_QZ1_QUAD_PER_TILE_H15 = 0x7f, 1269 SC_QZ1_QUAD_PER_TILE_H16 = 0x80, 1270 SC_QZ2_QUAD_PER_TILE_H0 = 0x81, 1271 SC_QZ2_QUAD_PER_TILE_H1 = 0x82, 1272 SC_QZ2_QUAD_PER_TILE_H2 = 0x83, 1273 SC_QZ2_QUAD_PER_TILE_H3 = 0x84, 1274 SC_QZ2_QUAD_PER_TILE_H4 = 0x85, 1275 SC_QZ2_QUAD_PER_TILE_H5 = 0x86, 1276 SC_QZ2_QUAD_PER_TILE_H6 = 0x87, 1277 SC_QZ2_QUAD_PER_TILE_H7 = 0x88, 1278 SC_QZ2_QUAD_PER_TILE_H8 = 0x89, 1279 SC_QZ2_QUAD_PER_TILE_H9 = 0x8a, 1280 SC_QZ2_QUAD_PER_TILE_H10 = 0x8b, 1281 SC_QZ2_QUAD_PER_TILE_H11 = 0x8c, 1282 SC_QZ2_QUAD_PER_TILE_H12 = 0x8d, 1283 SC_QZ2_QUAD_PER_TILE_H13 = 0x8e, 1284 SC_QZ2_QUAD_PER_TILE_H14 = 0x8f, 1285 SC_QZ2_QUAD_PER_TILE_H15 = 0x90, 1286 SC_QZ2_QUAD_PER_TILE_H16 = 0x91, 1287 SC_QZ3_QUAD_PER_TILE_H0 = 0x92, 1288 SC_QZ3_QUAD_PER_TILE_H1 = 0x93, 1289 SC_QZ3_QUAD_PER_TILE_H2 = 0x94, 1290 SC_QZ3_QUAD_PER_TILE_H3 = 0x95, 1291 SC_QZ3_QUAD_PER_TILE_H4 = 0x96, 1292 SC_QZ3_QUAD_PER_TILE_H5 = 0x97, 1293 SC_QZ3_QUAD_PER_TILE_H6 = 0x98, 1294 SC_QZ3_QUAD_PER_TILE_H7 = 0x99, 1295 SC_QZ3_QUAD_PER_TILE_H8 = 0x9a, 1296 SC_QZ3_QUAD_PER_TILE_H9 = 0x9b, 1297 SC_QZ3_QUAD_PER_TILE_H10 = 0x9c, 1298 SC_QZ3_QUAD_PER_TILE_H11 = 0x9d, 1299 SC_QZ3_QUAD_PER_TILE_H12 = 0x9e, 1300 SC_QZ3_QUAD_PER_TILE_H13 = 0x9f, 1301 SC_QZ3_QUAD_PER_TILE_H14 = 0xa0, 1302 SC_QZ3_QUAD_PER_TILE_H15 = 0xa1, 1303 SC_QZ3_QUAD_PER_TILE_H16 = 0xa2, 1304 SC_QZ0_QUAD_COUNT = 0xa3, 1305 SC_QZ1_QUAD_COUNT = 0xa4, 1306 SC_QZ2_QUAD_COUNT = 0xa5, 1307 SC_QZ3_QUAD_COUNT = 0xa6, 1308 SC_P0_HIZ_TILE_COUNT = 0xa7, 1309 SC_P1_HIZ_TILE_COUNT = 0xa8, 1310 SC_P2_HIZ_TILE_COUNT = 0xa9, 1311 SC_P3_HIZ_TILE_COUNT = 0xaa, 1312 SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab, 1313 SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac, 1314 SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad, 1315 SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae, 1316 SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf, 1317 SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0, 1318 SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1, 1319 SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2, 1320 SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3, 1321 SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4, 1322 SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5, 1323 SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6, 1324 SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7, 1325 SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8, 1326 SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9, 1327 SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba, 1328 SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb, 1329 SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc, 1330 SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd, 1331 SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe, 1332 SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf, 1333 SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0, 1334 SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1, 1335 SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2, 1336 SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3, 1337 SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4, 1338 SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5, 1339 SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6, 1340 SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7, 1341 SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8, 1342 SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9, 1343 SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca, 1344 SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb, 1345 SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc, 1346 SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd, 1347 SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce, 1348 SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf, 1349 SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0, 1350 SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1, 1351 SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2, 1352 SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3, 1353 SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4, 1354 SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5, 1355 SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6, 1356 SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7, 1357 SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8, 1358 SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9, 1359 SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda, 1360 SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb, 1361 SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc, 1362 SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd, 1363 SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde, 1364 SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf, 1365 SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0, 1366 SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1, 1367 SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2, 1368 SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3, 1369 SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4, 1370 SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5, 1371 SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6, 1372 SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7, 1373 SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8, 1374 SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9, 1375 SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea, 1376 SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb, 1377 SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec, 1378 SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed, 1379 SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee, 1380 SC_P0_HIZ_QUAD_COUNT = 0xef, 1381 SC_P1_HIZ_QUAD_COUNT = 0xf0, 1382 SC_P2_HIZ_QUAD_COUNT = 0xf1, 1383 SC_P3_HIZ_QUAD_COUNT = 0xf2, 1384 SC_P0_DETAIL_QUAD_COUNT = 0xf3, 1385 SC_P1_DETAIL_QUAD_COUNT = 0xf4, 1386 SC_P2_DETAIL_QUAD_COUNT = 0xf5, 1387 SC_P3_DETAIL_QUAD_COUNT = 0xf6, 1388 SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7, 1389 SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8, 1390 SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9, 1391 SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa, 1392 SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb, 1393 SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc, 1394 SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd, 1395 SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe, 1396 SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff, 1397 SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100, 1398 SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101, 1399 SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102, 1400 SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103, 1401 SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104, 1402 SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105, 1403 SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106, 1404 SC_EARLYZ_QUAD_COUNT = 0x107, 1405 SC_EARLYZ_QUAD_WITH_1_PIX = 0x108, 1406 SC_EARLYZ_QUAD_WITH_2_PIX = 0x109, 1407 SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a, 1408 SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b, 1409 SC_PKR_QUAD_PER_ROW_H1 = 0x10c, 1410 SC_PKR_QUAD_PER_ROW_H2 = 0x10d, 1411 SC_PKR_QUAD_PER_ROW_H3 = 0x10e, 1412 SC_PKR_QUAD_PER_ROW_H4 = 0x10f, 1413 SC_PKR_END_OF_VECTOR = 0x110, 1414 SC_PKR_CONTROL_XFER = 0x111, 1415 SC_PKR_DBHANG_FORCE_EOV = 0x112, 1416 SC_REG_SCLK_BUSY = 0x113, 1417 SC_GRP0_DYN_SCLK_BUSY = 0x114, 1418 SC_GRP1_DYN_SCLK_BUSY = 0x115, 1419 SC_GRP2_DYN_SCLK_BUSY = 0x116, 1420 SC_GRP3_DYN_SCLK_BUSY = 0x117, 1421 SC_GRP4_DYN_SCLK_BUSY = 0x118, 1422 SC_PA0_SC_DATA_FIFO_RD = 0x119, 1423 SC_PA0_SC_DATA_FIFO_WE = 0x11a, 1424 SC_PA1_SC_DATA_FIFO_RD = 0x11b, 1425 SC_PA1_SC_DATA_FIFO_WE = 0x11c, 1426 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d, 1427 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e, 1428 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f, 1429 SC_PS_ARB_STALLED_FROM_BELOW = 0x120, 1430 SC_PS_ARB_STARVED_FROM_ABOVE = 0x121, 1431 SC_PS_ARB_SC_BUSY = 0x122, 1432 SC_PS_ARB_PA_SC_BUSY = 0x123, 1433 SC_PA2_SC_DATA_FIFO_RD = 0x124, 1434 SC_PA2_SC_DATA_FIFO_WE = 0x125, 1435 SC_PA3_SC_DATA_FIFO_RD = 0x126, 1436 SC_PA3_SC_DATA_FIFO_WE = 0x127, 1437 SC_PA_SC_DEALLOC_0_0_WE = 0x128, 1438 SC_PA_SC_DEALLOC_0_1_WE = 0x129, 1439 SC_PA_SC_DEALLOC_1_0_WE = 0x12a, 1440 SC_PA_SC_DEALLOC_1_1_WE = 0x12b, 1441 SC_PA_SC_DEALLOC_2_0_WE = 0x12c, 1442 SC_PA_SC_DEALLOC_2_1_WE = 0x12d, 1443 SC_PA_SC_DEALLOC_3_0_WE = 0x12e, 1444 SC_PA_SC_DEALLOC_3_1_WE = 0x12f, 1445 SC_PA0_SC_EOP_WE = 0x130, 1446 SC_PA0_SC_EOPG_WE = 0x131, 1447 SC_PA0_SC_EVENT_WE = 0x132, 1448 SC_PA1_SC_EOP_WE = 0x133, 1449 SC_PA1_SC_EOPG_WE = 0x134, 1450 SC_PA1_SC_EVENT_WE = 0x135, 1451 SC_PA2_SC_EOP_WE = 0x136, 1452 SC_PA2_SC_EOPG_WE = 0x137, 1453 SC_PA2_SC_EVENT_WE = 0x138, 1454 SC_PA3_SC_EOP_WE = 0x139, 1455 SC_PA3_SC_EOPG_WE = 0x13a, 1456 SC_PA3_SC_EVENT_WE = 0x13b, 1457 SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c, 1458 SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d, 1459 SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e, 1460 SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f, 1461 SC_PS_ARB_EVENT_SYNC_POP = 0x140, 1462 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141, 1463 SC_PA0_SC_FPOV_WE = 0x142, 1464 SC_PA1_SC_FPOV_WE = 0x143, 1465 SC_PA2_SC_FPOV_WE = 0x144, 1466 SC_PA3_SC_FPOV_WE = 0x145, 1467 SC_PA0_SC_LPOV_WE = 0x146, 1468 SC_PA1_SC_LPOV_WE = 0x147, 1469 SC_PA2_SC_LPOV_WE = 0x148, 1470 SC_PA3_SC_LPOV_WE = 0x149, 1471 SC_SC_SPI_DEALLOC_0_0 = 0x14a, 1472 SC_SC_SPI_DEALLOC_0_1 = 0x14b, 1473 SC_SC_SPI_DEALLOC_0_2 = 0x14c, 1474 SC_SC_SPI_DEALLOC_1_0 = 0x14d, 1475 SC_SC_SPI_DEALLOC_1_1 = 0x14e, 1476 SC_SC_SPI_DEALLOC_1_2 = 0x14f, 1477 SC_SC_SPI_DEALLOC_2_0 = 0x150, 1478 SC_SC_SPI_DEALLOC_2_1 = 0x151, 1479 SC_SC_SPI_DEALLOC_2_2 = 0x152, 1480 SC_SC_SPI_DEALLOC_3_0 = 0x153, 1481 SC_SC_SPI_DEALLOC_3_1 = 0x154, 1482 SC_SC_SPI_DEALLOC_3_2 = 0x155, 1483 SC_SC_SPI_FPOV_0 = 0x156, 1484 SC_SC_SPI_FPOV_1 = 0x157, 1485 SC_SC_SPI_FPOV_2 = 0x158, 1486 SC_SC_SPI_FPOV_3 = 0x159, 1487 SC_SC_SPI_EVENT = 0x15a, 1488 SC_PS_TS_EVENT_FIFO_PUSH = 0x15b, 1489 SC_PS_TS_EVENT_FIFO_POP = 0x15c, 1490 SC_PS_CTX_DONE_FIFO_PUSH = 0x15d, 1491 SC_PS_CTX_DONE_FIFO_POP = 0x15e, 1492 SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f, 1493 SC_EOP_SYNC_WINDOW = 0x160, 1494 SC_PA0_SC_NULL_WE = 0x161, 1495 SC_PA0_SC_NULL_DEALLOC_WE = 0x162, 1496 SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163, 1497 SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164, 1498 SC_PA0_SC_DEALLOC_0_RD = 0x165, 1499 SC_PA0_SC_DEALLOC_1_RD = 0x166, 1500 SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167, 1501 SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168, 1502 SC_PA1_SC_DEALLOC_0_RD = 0x169, 1503 SC_PA1_SC_DEALLOC_1_RD = 0x16a, 1504 SC_PA1_SC_NULL_WE = 0x16b, 1505 SC_PA1_SC_NULL_DEALLOC_WE = 0x16c, 1506 SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d, 1507 SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e, 1508 SC_PA2_SC_DEALLOC_0_RD = 0x16f, 1509 SC_PA2_SC_DEALLOC_1_RD = 0x170, 1510 SC_PA2_SC_NULL_WE = 0x171, 1511 SC_PA2_SC_NULL_DEALLOC_WE = 0x172, 1512 SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173, 1513 SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174, 1514 SC_PA3_SC_DEALLOC_0_RD = 0x175, 1515 SC_PA3_SC_DEALLOC_1_RD = 0x176, 1516 SC_PA3_SC_NULL_WE = 0x177, 1517 SC_PA3_SC_NULL_DEALLOC_WE = 0x178, 1518 SC_PS_PA0_SC_FIFO_EMPTY = 0x179, 1519 SC_PS_PA0_SC_FIFO_FULL = 0x17a, 1520 SC_PA0_PS_DATA_SEND = 0x17b, 1521 SC_PS_PA1_SC_FIFO_EMPTY = 0x17c, 1522 SC_PS_PA1_SC_FIFO_FULL = 0x17d, 1523 SC_PA1_PS_DATA_SEND = 0x17e, 1524 SC_PS_PA2_SC_FIFO_EMPTY = 0x17f, 1525 SC_PS_PA2_SC_FIFO_FULL = 0x180, 1526 SC_PA2_PS_DATA_SEND = 0x181, 1527 SC_PS_PA3_SC_FIFO_EMPTY = 0x182, 1528 SC_PS_PA3_SC_FIFO_FULL = 0x183, 1529 SC_PA3_PS_DATA_SEND = 0x184, 1530 SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185, 1531 SC_BUSY_CNT_NOT_ZERO = 0x186, 1532 SC_BM_BUSY = 0x187, 1533 SC_BACKEND_BUSY = 0x188, 1534 SC_SCF_SCB_INTERFACE_BUSY = 0x189, 1535 SC_SCB_BUSY = 0x18a, 1536 } SC_PERFCNT_SEL; 1537 typedef enum SePairXsel { 1538 RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0, 1539 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1, 1540 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2, 1541 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3, 1542 } SePairXsel; 1543 typedef enum SePairYsel { 1544 RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0, 1545 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1, 1546 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2, 1547 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3, 1548 } SePairYsel; 1549 typedef enum SePairMap { 1550 RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0, 1551 RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1, 1552 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2, 1553 RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3, 1554 } SePairMap; 1555 typedef enum SeXsel { 1556 RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0, 1557 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1, 1558 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2, 1559 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3, 1560 } SeXsel; 1561 typedef enum SeYsel { 1562 RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0, 1563 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1, 1564 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2, 1565 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3, 1566 } SeYsel; 1567 typedef enum SeMap { 1568 RASTER_CONFIG_SE_MAP_0 = 0x0, 1569 RASTER_CONFIG_SE_MAP_1 = 0x1, 1570 RASTER_CONFIG_SE_MAP_2 = 0x2, 1571 RASTER_CONFIG_SE_MAP_3 = 0x3, 1572 } SeMap; 1573 typedef enum ScXsel { 1574 RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0, 1575 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1, 1576 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2, 1577 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3, 1578 } ScXsel; 1579 typedef enum ScYsel { 1580 RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0, 1581 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1, 1582 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2, 1583 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3, 1584 } ScYsel; 1585 typedef enum ScMap { 1586 RASTER_CONFIG_SC_MAP_0 = 0x0, 1587 RASTER_CONFIG_SC_MAP_1 = 0x1, 1588 RASTER_CONFIG_SC_MAP_2 = 0x2, 1589 RASTER_CONFIG_SC_MAP_3 = 0x3, 1590 } ScMap; 1591 typedef enum PkrXsel2 { 1592 RASTER_CONFIG_PKR_XSEL2_0 = 0x0, 1593 RASTER_CONFIG_PKR_XSEL2_1 = 0x1, 1594 RASTER_CONFIG_PKR_XSEL2_2 = 0x2, 1595 RASTER_CONFIG_PKR_XSEL2_3 = 0x3, 1596 } PkrXsel2; 1597 typedef enum PkrXsel { 1598 RASTER_CONFIG_PKR_XSEL_0 = 0x0, 1599 RASTER_CONFIG_PKR_XSEL_1 = 0x1, 1600 RASTER_CONFIG_PKR_XSEL_2 = 0x2, 1601 RASTER_CONFIG_PKR_XSEL_3 = 0x3, 1602 } PkrXsel; 1603 typedef enum PkrYsel { 1604 RASTER_CONFIG_PKR_YSEL_0 = 0x0, 1605 RASTER_CONFIG_PKR_YSEL_1 = 0x1, 1606 RASTER_CONFIG_PKR_YSEL_2 = 0x2, 1607 RASTER_CONFIG_PKR_YSEL_3 = 0x3, 1608 } PkrYsel; 1609 typedef enum PkrMap { 1610 RASTER_CONFIG_PKR_MAP_0 = 0x0, 1611 RASTER_CONFIG_PKR_MAP_1 = 0x1, 1612 RASTER_CONFIG_PKR_MAP_2 = 0x2, 1613 RASTER_CONFIG_PKR_MAP_3 = 0x3, 1614 } PkrMap; 1615 typedef enum RbXsel { 1616 RASTER_CONFIG_RB_XSEL_0 = 0x0, 1617 RASTER_CONFIG_RB_XSEL_1 = 0x1, 1618 } RbXsel; 1619 typedef enum RbYsel { 1620 RASTER_CONFIG_RB_YSEL_0 = 0x0, 1621 RASTER_CONFIG_RB_YSEL_1 = 0x1, 1622 } RbYsel; 1623 typedef enum RbXsel2 { 1624 RASTER_CONFIG_RB_XSEL2_0 = 0x0, 1625 RASTER_CONFIG_RB_XSEL2_1 = 0x1, 1626 RASTER_CONFIG_RB_XSEL2_2 = 0x2, 1627 RASTER_CONFIG_RB_XSEL2_3 = 0x3, 1628 } RbXsel2; 1629 typedef enum RbMap { 1630 RASTER_CONFIG_RB_MAP_0 = 0x0, 1631 RASTER_CONFIG_RB_MAP_1 = 0x1, 1632 RASTER_CONFIG_RB_MAP_2 = 0x2, 1633 RASTER_CONFIG_RB_MAP_3 = 0x3, 1634 } RbMap; 1635 typedef enum CSDATA_TYPE { 1636 CSDATA_TYPE_TG = 0x0, 1637 CSDATA_TYPE_STATE = 0x1, 1638 CSDATA_TYPE_EVENT = 0x2, 1639 CSDATA_TYPE_PRIVATE = 0x3, 1640 } CSDATA_TYPE; 1641 #define CSDATA_TYPE_WIDTH 0x2 1642 #define CSDATA_ADDR_WIDTH 0x7 1643 #define CSDATA_DATA_WIDTH 0x20 1644 typedef enum SPI_SAMPLE_CNTL { 1645 CENTROIDS_ONLY = 0x0, 1646 CENTERS_ONLY = 0x1, 1647 CENTROIDS_AND_CENTERS = 0x2, 1648 UNDEF = 0x3, 1649 } SPI_SAMPLE_CNTL; 1650 typedef enum SPI_FOG_MODE { 1651 SPI_FOG_NONE = 0x0, 1652 SPI_FOG_EXP = 0x1, 1653 SPI_FOG_EXP2 = 0x2, 1654 SPI_FOG_LINEAR = 0x3, 1655 } SPI_FOG_MODE; 1656 typedef enum SPI_PNT_SPRITE_OVERRIDE { 1657 SPI_PNT_SPRITE_SEL_0 = 0x0, 1658 SPI_PNT_SPRITE_SEL_1 = 0x1, 1659 SPI_PNT_SPRITE_SEL_S = 0x2, 1660 SPI_PNT_SPRITE_SEL_T = 0x3, 1661 SPI_PNT_SPRITE_SEL_NONE = 0x4, 1662 } SPI_PNT_SPRITE_OVERRIDE; 1663 typedef enum SPI_PERFCNT_SEL { 1664 SPI_PERF_VS_WINDOW_VALID = 0x0, 1665 SPI_PERF_VS_BUSY = 0x1, 1666 SPI_PERF_VS_FIRST_WAVE = 0x2, 1667 SPI_PERF_VS_LAST_WAVE = 0x3, 1668 SPI_PERF_VS_LSHS_DEALLOC = 0x4, 1669 SPI_PERF_VS_PC_STALL = 0x5, 1670 SPI_PERF_VS_POS0_STALL = 0x6, 1671 SPI_PERF_VS_POS1_STALL = 0x7, 1672 SPI_PERF_VS_CRAWLER_STALL = 0x8, 1673 SPI_PERF_VS_EVENT_WAVE = 0x9, 1674 SPI_PERF_VS_WAVE = 0xa, 1675 SPI_PERF_VS_PERS_UPD_FULL0 = 0xb, 1676 SPI_PERF_VS_PERS_UPD_FULL1 = 0xc, 1677 SPI_PERF_VS_LATE_ALLOC_FULL = 0xd, 1678 SPI_PERF_VS_FIRST_SUBGRP = 0xe, 1679 SPI_PERF_VS_LAST_SUBGRP = 0xf, 1680 SPI_PERF_GS_WINDOW_VALID = 0x10, 1681 SPI_PERF_GS_BUSY = 0x11, 1682 SPI_PERF_GS_CRAWLER_STALL = 0x12, 1683 SPI_PERF_GS_EVENT_WAVE = 0x13, 1684 SPI_PERF_GS_WAVE = 0x14, 1685 SPI_PERF_GS_PERS_UPD_FULL0 = 0x15, 1686 SPI_PERF_GS_PERS_UPD_FULL1 = 0x16, 1687 SPI_PERF_GS_FIRST_SUBGRP = 0x17, 1688 SPI_PERF_GS_LAST_SUBGRP = 0x18, 1689 SPI_PERF_ES_WINDOW_VALID = 0x19, 1690 SPI_PERF_ES_BUSY = 0x1a, 1691 SPI_PERF_ES_CRAWLER_STALL = 0x1b, 1692 SPI_PERF_ES_FIRST_WAVE = 0x1c, 1693 SPI_PERF_ES_LAST_WAVE = 0x1d, 1694 SPI_PERF_ES_LSHS_DEALLOC = 0x1e, 1695 SPI_PERF_ES_EVENT_WAVE = 0x1f, 1696 SPI_PERF_ES_WAVE = 0x20, 1697 SPI_PERF_ES_PERS_UPD_FULL0 = 0x21, 1698 SPI_PERF_ES_PERS_UPD_FULL1 = 0x22, 1699 SPI_PERF_ES_FIRST_SUBGRP = 0x23, 1700 SPI_PERF_ES_LAST_SUBGRP = 0x24, 1701 SPI_PERF_HS_WINDOW_VALID = 0x25, 1702 SPI_PERF_HS_BUSY = 0x26, 1703 SPI_PERF_HS_CRAWLER_STALL = 0x27, 1704 SPI_PERF_HS_FIRST_WAVE = 0x28, 1705 SPI_PERF_HS_LAST_WAVE = 0x29, 1706 SPI_PERF_HS_LSHS_DEALLOC = 0x2a, 1707 SPI_PERF_HS_EVENT_WAVE = 0x2b, 1708 SPI_PERF_HS_WAVE = 0x2c, 1709 SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d, 1710 SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e, 1711 SPI_PERF_LS_WINDOW_VALID = 0x2f, 1712 SPI_PERF_LS_BUSY = 0x30, 1713 SPI_PERF_LS_CRAWLER_STALL = 0x31, 1714 SPI_PERF_LS_FIRST_WAVE = 0x32, 1715 SPI_PERF_LS_LAST_WAVE = 0x33, 1716 SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34, 1717 SPI_PERF_LS_EVENT_WAVE = 0x35, 1718 SPI_PERF_LS_WAVE = 0x36, 1719 SPI_PERF_LS_PERS_UPD_FULL0 = 0x37, 1720 SPI_PERF_LS_PERS_UPD_FULL1 = 0x38, 1721 SPI_PERF_CSG_WINDOW_VALID = 0x39, 1722 SPI_PERF_CSG_BUSY = 0x3a, 1723 SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b, 1724 SPI_PERF_CSG_CRAWLER_STALL = 0x3c, 1725 SPI_PERF_CSG_EVENT_WAVE = 0x3d, 1726 SPI_PERF_CSG_WAVE = 0x3e, 1727 SPI_PERF_CSN_WINDOW_VALID = 0x3f, 1728 SPI_PERF_CSN_BUSY = 0x40, 1729 SPI_PERF_CSN_NUM_THREADGROUPS = 0x41, 1730 SPI_PERF_CSN_CRAWLER_STALL = 0x42, 1731 SPI_PERF_CSN_EVENT_WAVE = 0x43, 1732 SPI_PERF_CSN_WAVE = 0x44, 1733 SPI_PERF_PS_CTL_WINDOW_VALID = 0x45, 1734 SPI_PERF_PS_CTL_BUSY = 0x46, 1735 SPI_PERF_PS_CTL_ACTIVE = 0x47, 1736 SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48, 1737 SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49, 1738 SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a, 1739 SPI_PERF_PS_CTL_WAVE = 0x4b, 1740 SPI_PERF_PS_CTL_OPT_WAVE = 0x4c, 1741 SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d, 1742 SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e, 1743 SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f, 1744 SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50, 1745 SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51, 1746 SPI_PERF_PS_CTL_CNF_BIN2 = 0x52, 1747 SPI_PERF_PS_CTL_CNF_BIN3 = 0x53, 1748 SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54, 1749 SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55, 1750 SPI_PERF_PS_PERS_UPD_FULL0 = 0x56, 1751 SPI_PERF_PS_PERS_UPD_FULL1 = 0x57, 1752 SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58, 1753 SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59, 1754 SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a, 1755 SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b, 1756 SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c, 1757 SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d, 1758 SPI_PERF_LDS0_PC_VALID = 0x5e, 1759 SPI_PERF_LDS1_PC_VALID = 0x5f, 1760 SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60, 1761 SPI_PERF_RA_TASK_REQ_BIN3 = 0x61, 1762 SPI_PERF_RA_WR_CTL_FULL = 0x62, 1763 SPI_PERF_RA_REQ_NO_ALLOC = 0x63, 1764 SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64, 1765 SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65, 1766 SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66, 1767 SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67, 1768 SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68, 1769 SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69, 1770 SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a, 1771 SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b, 1772 SPI_PERF_RA_RES_STALL_PS = 0x6c, 1773 SPI_PERF_RA_RES_STALL_VS = 0x6d, 1774 SPI_PERF_RA_RES_STALL_GS = 0x6e, 1775 SPI_PERF_RA_RES_STALL_ES = 0x6f, 1776 SPI_PERF_RA_RES_STALL_HS = 0x70, 1777 SPI_PERF_RA_RES_STALL_LS = 0x71, 1778 SPI_PERF_RA_RES_STALL_CSG = 0x72, 1779 SPI_PERF_RA_RES_STALL_CSN = 0x73, 1780 SPI_PERF_RA_TMP_STALL_PS = 0x74, 1781 SPI_PERF_RA_TMP_STALL_VS = 0x75, 1782 SPI_PERF_RA_TMP_STALL_GS = 0x76, 1783 SPI_PERF_RA_TMP_STALL_ES = 0x77, 1784 SPI_PERF_RA_TMP_STALL_HS = 0x78, 1785 SPI_PERF_RA_TMP_STALL_LS = 0x79, 1786 SPI_PERF_RA_TMP_STALL_CSG = 0x7a, 1787 SPI_PERF_RA_TMP_STALL_CSN = 0x7b, 1788 SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c, 1789 SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d, 1790 SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e, 1791 SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f, 1792 SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80, 1793 SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81, 1794 SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82, 1795 SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83, 1796 SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84, 1797 SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85, 1798 SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86, 1799 SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87, 1800 SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88, 1801 SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89, 1802 SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a, 1803 SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b, 1804 SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c, 1805 SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d, 1806 SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e, 1807 SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f, 1808 SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90, 1809 SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91, 1810 SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92, 1811 SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93, 1812 SPI_PERF_RA_LDS_CU_FULL_PS = 0x94, 1813 SPI_PERF_RA_LDS_CU_FULL_LS = 0x95, 1814 SPI_PERF_RA_LDS_CU_FULL_ES = 0x96, 1815 SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97, 1816 SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98, 1817 SPI_PERF_RA_BAR_CU_FULL_HS = 0x99, 1818 SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a, 1819 SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b, 1820 SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c, 1821 SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d, 1822 SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e, 1823 SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f, 1824 SPI_PERF_RA_WVLIM_STALL_PS = 0xa0, 1825 SPI_PERF_RA_WVLIM_STALL_VS = 0xa1, 1826 SPI_PERF_RA_WVLIM_STALL_GS = 0xa2, 1827 SPI_PERF_RA_WVLIM_STALL_ES = 0xa3, 1828 SPI_PERF_RA_WVLIM_STALL_HS = 0xa4, 1829 SPI_PERF_RA_WVLIM_STALL_LS = 0xa5, 1830 SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6, 1831 SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7, 1832 SPI_PERF_RA_PS_LOCK = 0xa8, 1833 SPI_PERF_RA_VS_LOCK = 0xa9, 1834 SPI_PERF_RA_GS_LOCK = 0xaa, 1835 SPI_PERF_RA_ES_LOCK = 0xab, 1836 SPI_PERF_RA_HS_LOCK = 0xac, 1837 SPI_PERF_RA_LS_LOCK = 0xad, 1838 SPI_PERF_RA_CSG_LOCK = 0xae, 1839 SPI_PERF_RA_CSN_LOCK = 0xaf, 1840 SPI_PERF_RA_RSV_UPD = 0xb0, 1841 SPI_PERF_EXP_ARB_COL_CNT = 0xb1, 1842 SPI_PERF_EXP_ARB_PAR_CNT = 0xb2, 1843 SPI_PERF_EXP_ARB_POS_CNT = 0xb3, 1844 SPI_PERF_EXP_ARB_GDS_CNT = 0xb4, 1845 SPI_PERF_CLKGATE_BUSY_STALL = 0xb5, 1846 SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6, 1847 SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7, 1848 SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8, 1849 SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9, 1850 } SPI_PERFCNT_SEL; 1851 typedef enum SPI_SHADER_FORMAT { 1852 SPI_SHADER_NONE = 0x0, 1853 SPI_SHADER_1COMP = 0x1, 1854 SPI_SHADER_2COMP = 0x2, 1855 SPI_SHADER_4COMPRESS = 0x3, 1856 SPI_SHADER_4COMP = 0x4, 1857 } SPI_SHADER_FORMAT; 1858 typedef enum SPI_SHADER_EX_FORMAT { 1859 SPI_SHADER_ZERO = 0x0, 1860 SPI_SHADER_32_R = 0x1, 1861 SPI_SHADER_32_GR = 0x2, 1862 SPI_SHADER_32_AR = 0x3, 1863 SPI_SHADER_FP16_ABGR = 0x4, 1864 SPI_SHADER_UNORM16_ABGR = 0x5, 1865 SPI_SHADER_SNORM16_ABGR = 0x6, 1866 SPI_SHADER_UINT16_ABGR = 0x7, 1867 SPI_SHADER_SINT16_ABGR = 0x8, 1868 SPI_SHADER_32_ABGR = 0x9, 1869 } SPI_SHADER_EX_FORMAT; 1870 typedef enum CLKGATE_SM_MODE { 1871 ON_SEQ = 0x0, 1872 OFF_SEQ = 0x1, 1873 PROG_SEQ = 0x2, 1874 READ_SEQ = 0x3, 1875 SM_MODE_RESERVED = 0x4, 1876 } CLKGATE_SM_MODE; 1877 typedef enum CLKGATE_BASE_MODE { 1878 MULT_8 = 0x0, 1879 MULT_16 = 0x1, 1880 } CLKGATE_BASE_MODE; 1881 typedef enum SQ_TEX_CLAMP { 1882 SQ_TEX_WRAP = 0x0, 1883 SQ_TEX_MIRROR = 0x1, 1884 SQ_TEX_CLAMP_LAST_TEXEL = 0x2, 1885 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3, 1886 SQ_TEX_CLAMP_HALF_BORDER = 0x4, 1887 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5, 1888 SQ_TEX_CLAMP_BORDER = 0x6, 1889 SQ_TEX_MIRROR_ONCE_BORDER = 0x7, 1890 } SQ_TEX_CLAMP; 1891 typedef enum SQ_TEX_XY_FILTER { 1892 SQ_TEX_XY_FILTER_POINT = 0x0, 1893 SQ_TEX_XY_FILTER_BILINEAR = 0x1, 1894 SQ_TEX_XY_FILTER_ANISO_POINT = 0x2, 1895 SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3, 1896 } SQ_TEX_XY_FILTER; 1897 typedef enum SQ_TEX_Z_FILTER { 1898 SQ_TEX_Z_FILTER_NONE = 0x0, 1899 SQ_TEX_Z_FILTER_POINT = 0x1, 1900 SQ_TEX_Z_FILTER_LINEAR = 0x2, 1901 } SQ_TEX_Z_FILTER; 1902 typedef enum SQ_TEX_MIP_FILTER { 1903 SQ_TEX_MIP_FILTER_NONE = 0x0, 1904 SQ_TEX_MIP_FILTER_POINT = 0x1, 1905 SQ_TEX_MIP_FILTER_LINEAR = 0x2, 1906 } SQ_TEX_MIP_FILTER; 1907 typedef enum SQ_TEX_ANISO_RATIO { 1908 SQ_TEX_ANISO_RATIO_1 = 0x0, 1909 SQ_TEX_ANISO_RATIO_2 = 0x1, 1910 SQ_TEX_ANISO_RATIO_4 = 0x2, 1911 SQ_TEX_ANISO_RATIO_8 = 0x3, 1912 SQ_TEX_ANISO_RATIO_16 = 0x4, 1913 } SQ_TEX_ANISO_RATIO; 1914 typedef enum SQ_TEX_DEPTH_COMPARE { 1915 SQ_TEX_DEPTH_COMPARE_NEVER = 0x0, 1916 SQ_TEX_DEPTH_COMPARE_LESS = 0x1, 1917 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2, 1918 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3, 1919 SQ_TEX_DEPTH_COMPARE_GREATER = 0x4, 1920 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5, 1921 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6, 1922 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7, 1923 } SQ_TEX_DEPTH_COMPARE; 1924 typedef enum SQ_TEX_BORDER_COLOR { 1925 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0, 1926 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1, 1927 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2, 1928 SQ_TEX_BORDER_COLOR_REGISTER = 0x3, 1929 } SQ_TEX_BORDER_COLOR; 1930 typedef enum SQ_RSRC_BUF_TYPE { 1931 SQ_RSRC_BUF = 0x0, 1932 SQ_RSRC_BUF_RSVD_1 = 0x1, 1933 SQ_RSRC_BUF_RSVD_2 = 0x2, 1934 SQ_RSRC_BUF_RSVD_3 = 0x3, 1935 } SQ_RSRC_BUF_TYPE; 1936 typedef enum SQ_RSRC_IMG_TYPE { 1937 SQ_RSRC_IMG_RSVD_0 = 0x0, 1938 SQ_RSRC_IMG_RSVD_1 = 0x1, 1939 SQ_RSRC_IMG_RSVD_2 = 0x2, 1940 SQ_RSRC_IMG_RSVD_3 = 0x3, 1941 SQ_RSRC_IMG_RSVD_4 = 0x4, 1942 SQ_RSRC_IMG_RSVD_5 = 0x5, 1943 SQ_RSRC_IMG_RSVD_6 = 0x6, 1944 SQ_RSRC_IMG_RSVD_7 = 0x7, 1945 SQ_RSRC_IMG_1D = 0x8, 1946 SQ_RSRC_IMG_2D = 0x9, 1947 SQ_RSRC_IMG_3D = 0xa, 1948 SQ_RSRC_IMG_CUBE = 0xb, 1949 SQ_RSRC_IMG_1D_ARRAY = 0xc, 1950 SQ_RSRC_IMG_2D_ARRAY = 0xd, 1951 SQ_RSRC_IMG_2D_MSAA = 0xe, 1952 SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf, 1953 } SQ_RSRC_IMG_TYPE; 1954 typedef enum SQ_RSRC_FLAT_TYPE { 1955 SQ_RSRC_FLAT_RSVD_0 = 0x0, 1956 SQ_RSRC_FLAT = 0x1, 1957 SQ_RSRC_FLAT_RSVD_2 = 0x2, 1958 SQ_RSRC_FLAT_RSVD_3 = 0x3, 1959 } SQ_RSRC_FLAT_TYPE; 1960 typedef enum SQ_IMG_FILTER_TYPE { 1961 SQ_IMG_FILTER_MODE_BLEND = 0x0, 1962 SQ_IMG_FILTER_MODE_MIN = 0x1, 1963 SQ_IMG_FILTER_MODE_MAX = 0x2, 1964 } SQ_IMG_FILTER_TYPE; 1965 typedef enum SQ_SEL_XYZW01 { 1966 SQ_SEL_0 = 0x0, 1967 SQ_SEL_1 = 0x1, 1968 SQ_SEL_RESERVED_0 = 0x2, 1969 SQ_SEL_RESERVED_1 = 0x3, 1970 SQ_SEL_X = 0x4, 1971 SQ_SEL_Y = 0x5, 1972 SQ_SEL_Z = 0x6, 1973 SQ_SEL_W = 0x7, 1974 } SQ_SEL_XYZW01; 1975 typedef enum SQ_WAVE_TYPE { 1976 SQ_WAVE_TYPE_PS = 0x0, 1977 SQ_WAVE_TYPE_VS = 0x1, 1978 SQ_WAVE_TYPE_GS = 0x2, 1979 SQ_WAVE_TYPE_ES = 0x3, 1980 SQ_WAVE_TYPE_HS = 0x4, 1981 SQ_WAVE_TYPE_LS = 0x5, 1982 SQ_WAVE_TYPE_CS = 0x6, 1983 SQ_WAVE_TYPE_PS1 = 0x7, 1984 } SQ_WAVE_TYPE; 1985 typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { 1986 SQ_THREAD_TRACE_TOKEN_MISC = 0x0, 1987 SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1, 1988 SQ_THREAD_TRACE_TOKEN_REG = 0x2, 1989 SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3, 1990 SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4, 1991 SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5, 1992 SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6, 1993 SQ_THREAD_TRACE_TOKEN_EVENT = 0x7, 1994 SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8, 1995 SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9, 1996 SQ_THREAD_TRACE_TOKEN_INST = 0xa, 1997 SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb, 1998 SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc, 1999 SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd, 2000 SQ_THREAD_TRACE_TOKEN_PERF = 0xe, 2001 SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf, 2002 } SQ_THREAD_TRACE_TOKEN_TYPE; 2003 typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { 2004 SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0, 2005 SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1, 2006 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2, 2007 SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3, 2008 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4, 2009 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5, 2010 } SQ_THREAD_TRACE_MISC_TOKEN_TYPE; 2011 typedef enum SQ_THREAD_TRACE_INST_TYPE { 2012 SQ_THREAD_TRACE_INST_TYPE_SMEM = 0x0, 2013 SQ_THREAD_TRACE_INST_TYPE_SALU = 0x1, 2014 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2, 2015 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3, 2016 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4, 2017 SQ_THREAD_TRACE_INST_TYPE_VALU = 0x5, 2018 SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6, 2019 SQ_THREAD_TRACE_INST_TYPE_PC = 0x7, 2020 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8, 2021 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9, 2022 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa, 2023 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb, 2024 SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc, 2025 SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd, 2026 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe, 2027 SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf, 2028 } SQ_THREAD_TRACE_INST_TYPE; 2029 typedef enum SQ_THREAD_TRACE_REG_TYPE { 2030 SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0, 2031 SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1, 2032 SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2, 2033 SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3, 2034 SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4, 2035 SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5, 2036 SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6, 2037 SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7, 2038 } SQ_THREAD_TRACE_REG_TYPE; 2039 typedef enum SQ_THREAD_TRACE_REG_OP { 2040 SQ_THREAD_TRACE_REG_OP_READ = 0x0, 2041 SQ_THREAD_TRACE_REG_OP_WRITE = 0x1, 2042 } SQ_THREAD_TRACE_REG_OP; 2043 typedef enum SQ_THREAD_TRACE_MODE_SEL { 2044 SQ_THREAD_TRACE_MODE_OFF = 0x0, 2045 SQ_THREAD_TRACE_MODE_ON = 0x1, 2046 SQ_THREAD_TRACE_MODE_RANDOM = 0x2, 2047 } SQ_THREAD_TRACE_MODE_SEL; 2048 typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { 2049 SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0, 2050 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1, 2051 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2, 2052 } SQ_THREAD_TRACE_CAPTURE_MODE; 2053 typedef enum SQ_THREAD_TRACE_VM_ID_MASK { 2054 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0, 2055 SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1, 2056 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2, 2057 } SQ_THREAD_TRACE_VM_ID_MASK; 2058 typedef enum SQ_THREAD_TRACE_WAVE_MASK { 2059 SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0, 2060 SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1, 2061 SQ_THREAD_TRACE_WAVE_MASK_1_2 = 0x2, 2062 SQ_THREAD_TRACE_WAVE_MASK_1_4 = 0x3, 2063 SQ_THREAD_TRACE_WAVE_MASK_1_8 = 0x4, 2064 SQ_THREAD_TRACE_WAVE_MASK_1_16 = 0x5, 2065 SQ_THREAD_TRACE_WAVE_MASK_1_32 = 0x6, 2066 SQ_THREAD_TRACE_WAVE_MASK_1_64 = 0x7, 2067 } SQ_THREAD_TRACE_WAVE_MASK; 2068 typedef enum SQ_THREAD_TRACE_ISSUE { 2069 SQ_THREAD_TRACE_ISSUE_NULL = 0x0, 2070 SQ_THREAD_TRACE_ISSUE_STALL = 0x1, 2071 SQ_THREAD_TRACE_ISSUE_INST = 0x2, 2072 SQ_THREAD_TRACE_ISSUE_IMMED = 0x3, 2073 } SQ_THREAD_TRACE_ISSUE; 2074 typedef enum SQ_THREAD_TRACE_ISSUE_MASK { 2075 SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0, 2076 SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1, 2077 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2, 2078 SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3, 2079 } SQ_THREAD_TRACE_ISSUE_MASK; 2080 typedef enum SQ_PERF_SEL { 2081 SQ_PERF_SEL_NONE = 0x0, 2082 SQ_PERF_SEL_ACCUM_PREV = 0x1, 2083 SQ_PERF_SEL_CYCLES = 0x2, 2084 SQ_PERF_SEL_BUSY_CYCLES = 0x3, 2085 SQ_PERF_SEL_WAVES = 0x4, 2086 SQ_PERF_SEL_LEVEL_WAVES = 0x5, 2087 SQ_PERF_SEL_WAVES_EQ_64 = 0x6, 2088 SQ_PERF_SEL_WAVES_LT_64 = 0x7, 2089 SQ_PERF_SEL_WAVES_LT_48 = 0x8, 2090 SQ_PERF_SEL_WAVES_LT_32 = 0x9, 2091 SQ_PERF_SEL_WAVES_LT_16 = 0xa, 2092 SQ_PERF_SEL_WAVES_CU = 0xb, 2093 SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc, 2094 SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd, 2095 SQ_PERF_SEL_ITEMS = 0xe, 2096 SQ_PERF_SEL_QUADS = 0xf, 2097 SQ_PERF_SEL_EVENTS = 0x10, 2098 SQ_PERF_SEL_SURF_SYNCS = 0x11, 2099 SQ_PERF_SEL_TTRACE_REQS = 0x12, 2100 SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13, 2101 SQ_PERF_SEL_TTRACE_STALL = 0x14, 2102 SQ_PERF_SEL_MSG_CNTR = 0x15, 2103 SQ_PERF_SEL_MSG_PERF = 0x16, 2104 SQ_PERF_SEL_MSG_GSCNT = 0x17, 2105 SQ_PERF_SEL_MSG_INTERRUPT = 0x18, 2106 SQ_PERF_SEL_INSTS = 0x19, 2107 SQ_PERF_SEL_INSTS_VALU = 0x1a, 2108 SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b, 2109 SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c, 2110 SQ_PERF_SEL_INSTS_VMEM = 0x1d, 2111 SQ_PERF_SEL_INSTS_SALU = 0x1e, 2112 SQ_PERF_SEL_INSTS_SMEM = 0x1f, 2113 SQ_PERF_SEL_INSTS_FLAT = 0x20, 2114 SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21, 2115 SQ_PERF_SEL_INSTS_LDS = 0x22, 2116 SQ_PERF_SEL_INSTS_GDS = 0x23, 2117 SQ_PERF_SEL_INSTS_EXP = 0x24, 2118 SQ_PERF_SEL_INSTS_EXP_GDS = 0x25, 2119 SQ_PERF_SEL_INSTS_BRANCH = 0x26, 2120 SQ_PERF_SEL_INSTS_SENDMSG = 0x27, 2121 SQ_PERF_SEL_INSTS_VSKIPPED = 0x28, 2122 SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29, 2123 SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a, 2124 SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b, 2125 SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c, 2126 SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d, 2127 SQ_PERF_SEL_WAVE_CYCLES = 0x2e, 2128 SQ_PERF_SEL_WAVE_READY = 0x2f, 2129 SQ_PERF_SEL_WAIT_CNT_VM = 0x30, 2130 SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31, 2131 SQ_PERF_SEL_WAIT_CNT_EXP = 0x32, 2132 SQ_PERF_SEL_WAIT_CNT_ANY = 0x33, 2133 SQ_PERF_SEL_WAIT_BARRIER = 0x34, 2134 SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35, 2135 SQ_PERF_SEL_WAIT_SLEEP = 0x36, 2136 SQ_PERF_SEL_WAIT_OTHER = 0x37, 2137 SQ_PERF_SEL_WAIT_ANY = 0x38, 2138 SQ_PERF_SEL_WAIT_TTRACE = 0x39, 2139 SQ_PERF_SEL_WAIT_IFETCH = 0x3a, 2140 SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b, 2141 SQ_PERF_SEL_WAIT_INST_SCA = 0x3c, 2142 SQ_PERF_SEL_WAIT_INST_LDS = 0x3d, 2143 SQ_PERF_SEL_WAIT_INST_VALU = 0x3e, 2144 SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f, 2145 SQ_PERF_SEL_WAIT_INST_MISC = 0x40, 2146 SQ_PERF_SEL_WAIT_INST_FLAT = 0x41, 2147 SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42, 2148 SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43, 2149 SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44, 2150 SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45, 2151 SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46, 2152 SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47, 2153 SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48, 2154 SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49, 2155 SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a, 2156 SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b, 2157 SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c, 2158 SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d, 2159 SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e, 2160 SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f, 2161 SQ_PERF_SEL_INST_CYCLES_LDS = 0x50, 2162 SQ_PERF_SEL_INST_CYCLES_VALU = 0x51, 2163 SQ_PERF_SEL_INST_CYCLES_EXP = 0x52, 2164 SQ_PERF_SEL_INST_CYCLES_GDS = 0x53, 2165 SQ_PERF_SEL_INST_CYCLES_SCA = 0x54, 2166 SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55, 2167 SQ_PERF_SEL_INST_CYCLES_SALU = 0x56, 2168 SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57, 2169 SQ_PERF_SEL_INST_CYCLES_MISC = 0x58, 2170 SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59, 2171 SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a, 2172 SQ_PERF_SEL_IFETCH = 0x5b, 2173 SQ_PERF_SEL_IFETCH_LEVEL = 0x5c, 2174 SQ_PERF_SEL_CBRANCH_FORK = 0x5d, 2175 SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e, 2176 SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f, 2177 SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60, 2178 SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61, 2179 SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62, 2180 SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63, 2181 SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64, 2182 SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65, 2183 SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66, 2184 SQ_PERF_SEL_VALU_DEP_STALL = 0x67, 2185 SQ_PERF_SEL_VALU_STARVE = 0x68, 2186 SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69, 2187 SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a, 2188 SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b, 2189 SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c, 2190 SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d, 2191 SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e, 2192 SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f, 2193 SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70, 2194 SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71, 2195 SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72, 2196 SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73, 2197 SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74, 2198 SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75, 2199 SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76, 2200 SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77, 2201 SQ_PERF_SEL_SRC_CD_BUSY = 0x78, 2202 SQ_PERF_SEL_PT_POWER_STALL = 0x79, 2203 SQ_PERF_SEL_USER0 = 0x7a, 2204 SQ_PERF_SEL_USER1 = 0x7b, 2205 SQ_PERF_SEL_USER2 = 0x7c, 2206 SQ_PERF_SEL_USER3 = 0x7d, 2207 SQ_PERF_SEL_USER4 = 0x7e, 2208 SQ_PERF_SEL_USER5 = 0x7f, 2209 SQ_PERF_SEL_USER6 = 0x80, 2210 SQ_PERF_SEL_USER7 = 0x81, 2211 SQ_PERF_SEL_USER8 = 0x82, 2212 SQ_PERF_SEL_USER9 = 0x83, 2213 SQ_PERF_SEL_USER10 = 0x84, 2214 SQ_PERF_SEL_USER11 = 0x85, 2215 SQ_PERF_SEL_USER12 = 0x86, 2216 SQ_PERF_SEL_USER13 = 0x87, 2217 SQ_PERF_SEL_USER14 = 0x88, 2218 SQ_PERF_SEL_USER15 = 0x89, 2219 SQ_PERF_SEL_USER_LEVEL0 = 0x8a, 2220 SQ_PERF_SEL_USER_LEVEL1 = 0x8b, 2221 SQ_PERF_SEL_USER_LEVEL2 = 0x8c, 2222 SQ_PERF_SEL_USER_LEVEL3 = 0x8d, 2223 SQ_PERF_SEL_USER_LEVEL4 = 0x8e, 2224 SQ_PERF_SEL_USER_LEVEL5 = 0x8f, 2225 SQ_PERF_SEL_USER_LEVEL6 = 0x90, 2226 SQ_PERF_SEL_USER_LEVEL7 = 0x91, 2227 SQ_PERF_SEL_USER_LEVEL8 = 0x92, 2228 SQ_PERF_SEL_USER_LEVEL9 = 0x93, 2229 SQ_PERF_SEL_USER_LEVEL10 = 0x94, 2230 SQ_PERF_SEL_USER_LEVEL11 = 0x95, 2231 SQ_PERF_SEL_USER_LEVEL12 = 0x96, 2232 SQ_PERF_SEL_USER_LEVEL13 = 0x97, 2233 SQ_PERF_SEL_USER_LEVEL14 = 0x98, 2234 SQ_PERF_SEL_USER_LEVEL15 = 0x99, 2235 SQ_PERF_SEL_POWER_VALU = 0x9a, 2236 SQ_PERF_SEL_POWER_VALU0 = 0x9b, 2237 SQ_PERF_SEL_POWER_VALU1 = 0x9c, 2238 SQ_PERF_SEL_POWER_VALU2 = 0x9d, 2239 SQ_PERF_SEL_POWER_GPR_RD = 0x9e, 2240 SQ_PERF_SEL_POWER_GPR_WR = 0x9f, 2241 SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0, 2242 SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1, 2243 SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2, 2244 SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3, 2245 SQ_PERF_SEL_DUMMY_LAST = 0xa7, 2246 SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8, 2247 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9, 2248 SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa, 2249 SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab, 2250 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac, 2251 SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad, 2252 SQC_PERF_SEL_TC_REQ = 0xae, 2253 SQC_PERF_SEL_TC_INST_REQ = 0xaf, 2254 SQC_PERF_SEL_TC_DATA_REQ = 0xb0, 2255 SQC_PERF_SEL_TC_STALL = 0xb1, 2256 SQC_PERF_SEL_TC_STARVE = 0xb2, 2257 SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb3, 2258 SQC_PERF_SEL_ICACHE_REQ = 0xb4, 2259 SQC_PERF_SEL_ICACHE_HITS = 0xb5, 2260 SQC_PERF_SEL_ICACHE_MISSES = 0xb6, 2261 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb7, 2262 SQC_PERF_SEL_ICACHE_UNCACHED = 0xb8, 2263 SQC_PERF_SEL_ICACHE_VOLATILE = 0xb9, 2264 SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba, 2265 SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb, 2266 SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_INST = 0xbc, 2267 SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_ASYNC = 0xbd, 2268 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbe, 2269 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbf, 2270 SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xc0, 2271 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xc1, 2272 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc2, 2273 SQC_PERF_SEL_ICACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xc3, 2274 SQC_PERF_SEL_ICACHE_CACHE_STALL_UNCACHED_HIT = 0xc4, 2275 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc5, 2276 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc6, 2277 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc7, 2278 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc8, 2279 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc9, 2280 SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xca, 2281 SQC_PERF_SEL_DCACHE_REQ = 0xcb, 2282 SQC_PERF_SEL_DCACHE_HITS = 0xcc, 2283 SQC_PERF_SEL_DCACHE_MISSES = 0xcd, 2284 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xce, 2285 SQC_PERF_SEL_DCACHE_UNCACHED = 0xcf, 2286 SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0, 2287 SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1, 2288 SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2, 2289 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3, 2290 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4, 2291 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd5, 2292 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xd6, 2293 SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xd7, 2294 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xd8, 2295 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xd9, 2296 SQC_PERF_SEL_DCACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xda, 2297 SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT = 0xdb, 2298 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdc, 2299 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xdd, 2300 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xde, 2301 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xdf, 2302 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe0, 2303 SQC_PERF_SEL_DCACHE_REQ_1 = 0xe1, 2304 SQC_PERF_SEL_DCACHE_REQ_2 = 0xe2, 2305 SQC_PERF_SEL_DCACHE_REQ_4 = 0xe3, 2306 SQC_PERF_SEL_DCACHE_REQ_8 = 0xe4, 2307 SQC_PERF_SEL_DCACHE_REQ_16 = 0xe5, 2308 SQC_PERF_SEL_DCACHE_REQ_TIME = 0xe6, 2309 SQC_PERF_SEL_SQ_DCACHE_REQS = 0xe7, 2310 SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xe8, 2311 SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xe9, 2312 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xea, 2313 SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL = 0xeb, 2314 SQC_PERF_SEL_ICACHE_POST_CC_LEVEL = 0xec, 2315 SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL = 0xed, 2316 SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL = 0xee, 2317 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xef, 2318 SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL = 0xf0, 2319 SQC_PERF_SEL_DCACHE_POST_CC_LEVEL = 0xf1, 2320 SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL = 0xf2, 2321 SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL = 0xf3, 2322 SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf4, 2323 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf5, 2324 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf6, 2325 SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED = 0xf7, 2326 SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED = 0xf8, 2327 SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED = 0xf9, 2328 SQC_PERF_SEL_ERR_DCACHE_REQ_16_GPR_ADDR_UNALIGNED= 0xfa, 2329 SQC_PERF_SEL_DUMMY_LAST = 0xfb, 2330 } SQ_PERF_SEL; 2331 typedef enum SQC_DATA_CACHE_POLICIES { 2332 SQC_DATA_CACHE_POLICY_HIT_LRU = 0x0, 2333 SQC_DATA_CACHE_POLICY_MISS_EVICT = 0x1, 2334 } SQC_DATA_CACHE_POLICIES; 2335 typedef enum SQ_CAC_POWER_SEL { 2336 SQ_CAC_POWER_VALU = 0x0, 2337 SQ_CAC_POWER_VALU0 = 0x1, 2338 SQ_CAC_POWER_VALU1 = 0x2, 2339 SQ_CAC_POWER_VALU2 = 0x3, 2340 SQ_CAC_POWER_GPR_RD = 0x4, 2341 SQ_CAC_POWER_GPR_WR = 0x5, 2342 SQ_CAC_POWER_LDS_BUSY = 0x6, 2343 SQ_CAC_POWER_ALU_BUSY = 0x7, 2344 SQ_CAC_POWER_TEX_BUSY = 0x8, 2345 } SQ_CAC_POWER_SEL; 2346 typedef enum SQ_IND_CMD_CMD { 2347 SQ_IND_CMD_CMD_NULL = 0x0, 2348 SQ_IND_CMD_CMD_HALT = 0x1, 2349 SQ_IND_CMD_CMD_RESUME = 0x2, 2350 SQ_IND_CMD_CMD_KILL = 0x3, 2351 SQ_IND_CMD_CMD_DEBUG = 0x4, 2352 SQ_IND_CMD_CMD_TRAP = 0x5, 2353 } SQ_IND_CMD_CMD; 2354 typedef enum SQ_IND_CMD_MODE { 2355 SQ_IND_CMD_MODE_SINGLE = 0x0, 2356 SQ_IND_CMD_MODE_BROADCAST = 0x1, 2357 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2, 2358 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3, 2359 SQ_IND_CMD_MODE_BROADCAST_ME = 0x4, 2360 } SQ_IND_CMD_MODE; 2361 typedef enum SQ_DED_INFO_SOURCE { 2362 SQ_DED_INFO_SOURCE_INVALID = 0x0, 2363 SQ_DED_INFO_SOURCE_INST = 0x1, 2364 SQ_DED_INFO_SOURCE_SGPR = 0x2, 2365 SQ_DED_INFO_SOURCE_VGPR = 0x3, 2366 SQ_DED_INFO_SOURCE_LDS = 0x4, 2367 SQ_DED_INFO_SOURCE_GDS = 0x5, 2368 SQ_DED_INFO_SOURCE_TA = 0x6, 2369 } SQ_DED_INFO_SOURCE; 2370 typedef enum SQ_ROUND_MODE { 2371 SQ_ROUND_NEAREST_EVEN = 0x0, 2372 SQ_ROUND_PLUS_INFINITY = 0x1, 2373 SQ_ROUND_MINUS_INFINITY = 0x2, 2374 SQ_ROUND_TO_ZERO = 0x3, 2375 } SQ_ROUND_MODE; 2376 typedef enum SQ_INTERRUPT_WORD_ENCODING { 2377 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, 2378 SQ_INTERRUPT_WORD_ENCODING_INST = 0x1, 2379 SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2, 2380 } SQ_INTERRUPT_WORD_ENCODING; 2381 typedef enum ENUM_SQ_EXPORT_RAT_INST { 2382 SQ_EXPORT_RAT_INST_NOP = 0x0, 2383 SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1, 2384 SQ_EXPORT_RAT_INST_STORE_RAW = 0x2, 2385 SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3, 2386 SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4, 2387 SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5, 2388 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6, 2389 SQ_EXPORT_RAT_INST_ADD = 0x7, 2390 SQ_EXPORT_RAT_INST_SUB = 0x8, 2391 SQ_EXPORT_RAT_INST_RSUB = 0x9, 2392 SQ_EXPORT_RAT_INST_MIN_INT = 0xa, 2393 SQ_EXPORT_RAT_INST_MIN_UINT = 0xb, 2394 SQ_EXPORT_RAT_INST_MAX_INT = 0xc, 2395 SQ_EXPORT_RAT_INST_MAX_UINT = 0xd, 2396 SQ_EXPORT_RAT_INST_AND = 0xe, 2397 SQ_EXPORT_RAT_INST_OR = 0xf, 2398 SQ_EXPORT_RAT_INST_XOR = 0x10, 2399 SQ_EXPORT_RAT_INST_MSKOR = 0x11, 2400 SQ_EXPORT_RAT_INST_INC_UINT = 0x12, 2401 SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, 2402 SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14, 2403 SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15, 2404 SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16, 2405 SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, 2406 SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, 2407 SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, 2408 SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, 2409 SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, 2410 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, 2411 SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, 2412 SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, 2413 SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, 2414 SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, 2415 SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, 2416 SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, 2417 SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, 2418 SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, 2419 SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, 2420 SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, 2421 SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, 2422 SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, 2423 SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, 2424 } ENUM_SQ_EXPORT_RAT_INST; 2425 typedef enum SQ_IBUF_ST { 2426 SQ_IBUF_IB_IDLE = 0x0, 2427 SQ_IBUF_IB_INI_WAIT_GNT = 0x1, 2428 SQ_IBUF_IB_INI_WAIT_DRET = 0x2, 2429 SQ_IBUF_IB_LE_4DW = 0x3, 2430 SQ_IBUF_IB_WAIT_DRET = 0x4, 2431 SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5, 2432 SQ_IBUF_IB_DRET = 0x6, 2433 SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7, 2434 } SQ_IBUF_ST; 2435 typedef enum SQ_INST_STR_ST { 2436 SQ_INST_STR_IB_WAVE_NORML = 0x0, 2437 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1, 2438 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2, 2439 SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3, 2440 SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4, 2441 SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5, 2442 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6, 2443 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7, 2444 } SQ_INST_STR_ST; 2445 typedef enum SQ_WAVE_IB_ECC_ST { 2446 SQ_WAVE_IB_ECC_CLEAN = 0x0, 2447 SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1, 2448 SQ_WAVE_IB_ECC_ERR_HALT = 0x2, 2449 SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3, 2450 } SQ_WAVE_IB_ECC_ST; 2451 typedef enum SH_MEM_ALIGNMENT_MODE { 2452 SH_MEM_ALIGNMENT_MODE_DWORD = 0x0, 2453 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1, 2454 SH_MEM_ALIGNMENT_MODE_STRICT = 0x2, 2455 SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3, 2456 } SH_MEM_ALIGNMENT_MODE; 2457 #define SQ_WAVE_TYPE_PS0 0x0 2458 #define SQ_THREAD_TRACE_LFSR_PS 0x8016 2459 #define SQ_THREAD_TRACE_LFSR_VS 0x801c 2460 #define SQ_THREAD_TRACE_LFSR_GS 0x801f 2461 #define SQ_THREAD_TRACE_LFSR_ES 0x8029 2462 #define SQ_THREAD_TRACE_LFSR_HS 0x805e 2463 #define SQ_THREAD_TRACE_LFSR_LS 0x806b 2464 #define SQ_THREAD_TRACE_LFSR_CS 0x8097 2465 #define SQIND_GLOBAL_REGS_OFFSET 0x0 2466 #define SQIND_GLOBAL_REGS_SIZE 0x8 2467 #define SQIND_LOCAL_REGS_OFFSET 0x8 2468 #define SQIND_LOCAL_REGS_SIZE 0x8 2469 #define SQIND_WAVE_HWREGS_OFFSET 0x10 2470 #define SQIND_WAVE_HWREGS_SIZE 0x1f0 2471 #define SQIND_WAVE_SGPRS_OFFSET 0x200 2472 #define SQIND_WAVE_SGPRS_SIZE 0x200 2473 #define SQ_GFXDEC_BEGIN 0xa000 2474 #define SQ_GFXDEC_END 0xc000 2475 #define SQ_GFXDEC_STATE_ID_SHIFT 0xa 2476 #define SQDEC_BEGIN 0x2300 2477 #define SQDEC_END 0x23ff 2478 #define SQPERFSDEC_BEGIN 0xd9c0 2479 #define SQPERFSDEC_END 0xda40 2480 #define SQPERFDDEC_BEGIN 0xd1c0 2481 #define SQPERFDDEC_END 0xd240 2482 #define SQGFXUDEC_BEGIN 0xc340 2483 #define SQGFXUDEC_END 0xc380 2484 #define SQPWRDEC_BEGIN 0xf08c 2485 #define SQPWRDEC_END 0xf094 2486 #define SQ_DISPATCHER_GFX_MIN 0x10 2487 #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8 2488 #define SQ_MAX_PGM_SGPRS 0x68 2489 #define SQ_MAX_PGM_VGPRS 0x100 2490 #define SQ_THREAD_TRACE_TIME_UNIT 0x4 2491 #define SQ_INTERRUPT_ID 0xef 2492 #define SQ_EX_MODE_EXCP_VALU_BASE 0x0 2493 #define SQ_EX_MODE_EXCP_VALU_SIZE 0x7 2494 #define SQ_EX_MODE_EXCP_INVALID 0x0 2495 #define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1 2496 #define SQ_EX_MODE_EXCP_DIV0 0x2 2497 #define SQ_EX_MODE_EXCP_OVERFLOW 0x3 2498 #define SQ_EX_MODE_EXCP_UNDERFLOW 0x4 2499 #define SQ_EX_MODE_EXCP_INEXACT 0x5 2500 #define SQ_EX_MODE_EXCP_INT_DIV0 0x6 2501 #define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7 2502 #define SQ_EX_MODE_EXCP_MEM_VIOL 0x8 2503 #define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 2504 #define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 2505 #define INST_ID_HW_TRAP 0xfffffff2 2506 #define INST_ID_KILL_SEQ 0xfffffff3 2507 #define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe 2508 #define SQ_ENC_SOP1_BITS 0xbe800000 2509 #define SQ_ENC_SOP1_MASK 0xff800000 2510 #define SQ_ENC_SOP1_FIELD 0x17d 2511 #define SQ_ENC_SOPC_BITS 0xbf000000 2512 #define SQ_ENC_SOPC_MASK 0xff800000 2513 #define SQ_ENC_SOPC_FIELD 0x17e 2514 #define SQ_ENC_SOPP_BITS 0xbf800000 2515 #define SQ_ENC_SOPP_MASK 0xff800000 2516 #define SQ_ENC_SOPP_FIELD 0x17f 2517 #define SQ_ENC_SOPK_BITS 0xb0000000 2518 #define SQ_ENC_SOPK_MASK 0xf0000000 2519 #define SQ_ENC_SOPK_FIELD 0xb 2520 #define SQ_ENC_SOP2_BITS 0x80000000 2521 #define SQ_ENC_SOP2_MASK 0xc0000000 2522 #define SQ_ENC_SOP2_FIELD 0x2 2523 #define SQ_ENC_SMRD_BITS 0xc0000000 2524 #define SQ_ENC_SMRD_MASK 0xf8000000 2525 #define SQ_ENC_SMRD_FIELD 0x18 2526 #define SQ_ENC_VOP1_BITS 0x7e000000 2527 #define SQ_ENC_VOP1_MASK 0xfe000000 2528 #define SQ_ENC_VOP1_FIELD 0x3f 2529 #define SQ_ENC_VOPC_BITS 0x7c000000 2530 #define SQ_ENC_VOPC_MASK 0xfe000000 2531 #define SQ_ENC_VOPC_FIELD 0x3e 2532 #define SQ_ENC_VOP2_BITS 0x0 2533 #define SQ_ENC_VOP2_MASK 0x80000000 2534 #define SQ_ENC_VOP2_FIELD 0x0 2535 #define SQ_ENC_VINTRP_BITS 0xc8000000 2536 #define SQ_ENC_VINTRP_MASK 0xfc000000 2537 #define SQ_ENC_VINTRP_FIELD 0x32 2538 #define SQ_ENC_VOP3_BITS 0xd0000000 2539 #define SQ_ENC_VOP3_MASK 0xfc000000 2540 #define SQ_ENC_VOP3_FIELD 0x34 2541 #define SQ_ENC_DS_BITS 0xd8000000 2542 #define SQ_ENC_DS_MASK 0xfc000000 2543 #define SQ_ENC_DS_FIELD 0x36 2544 #define SQ_ENC_MUBUF_BITS 0xe0000000 2545 #define SQ_ENC_MUBUF_MASK 0xfc000000 2546 #define SQ_ENC_MUBUF_FIELD 0x38 2547 #define SQ_ENC_MTBUF_BITS 0xe8000000 2548 #define SQ_ENC_MTBUF_MASK 0xfc000000 2549 #define SQ_ENC_MTBUF_FIELD 0x3a 2550 #define SQ_ENC_MIMG_BITS 0xf0000000 2551 #define SQ_ENC_MIMG_MASK 0xfc000000 2552 #define SQ_ENC_MIMG_FIELD 0x3c 2553 #define SQ_ENC_EXP_BITS 0xf8000000 2554 #define SQ_ENC_EXP_MASK 0xfc000000 2555 #define SQ_ENC_EXP_FIELD 0x3e 2556 #define SQ_ENC_FLAT_BITS 0xdc000000 2557 #define SQ_ENC_FLAT_MASK 0xfc000000 2558 #define SQ_ENC_FLAT_FIELD 0x37 2559 #define SQ_WAITCNT_VM_SHIFT 0x0 2560 #define SQ_SENDMSG_STREAMID_SIZE 0x2 2561 #define SQ_V_OPC_COUNT 0x100 2562 #define SQ_HWREG_OFFSET_SIZE 0x5 2563 #define SQ_HWREG_OFFSET_SHIFT 0x6 2564 #define SQ_NUM_ATTR 0x21 2565 #define SQ_NUM_VGPR 0x100 2566 #define SQ_SENDMSG_MSG_SIZE 0x4 2567 #define SQ_NUM_TTMP 0xc 2568 #define SQ_HWREG_ID_SIZE 0x6 2569 #define SQ_SENDMSG_GSOP_SIZE 0x2 2570 #define SQ_NUM_SGPR 0x68 2571 #define SQ_EXP_NUM_MRT 0x8 2572 #define SQ_SENDMSG_SYSTEM_SIZE 0x3 2573 #define SQ_WAITCNT_LGKM_SHIFT 0x8 2574 #define SQ_WAITCNT_EXP_SIZE 0x3 2575 #define SQ_SENDMSG_SYSTEM_SHIFT 0x4 2576 #define SQ_HWREG_SIZE_SHIFT 0xb 2577 #define SQ_EXP_NUM_GDS 0x5 2578 #define SQ_SENDMSG_MSG_SHIFT 0x0 2579 #define SQ_WAITCNT_EXP_SHIFT 0x4 2580 #define SQ_WAITCNT_VM_SIZE 0x4 2581 #define SQ_SENDMSG_GSOP_SHIFT 0x4 2582 #define SQ_SRC_VGPR_BIT 0x100 2583 #define SQ_V_OP2_COUNT 0x40 2584 #define SQ_EXP_NUM_PARAM 0x20 2585 #define SQ_SENDMSG_STREAMID_SHIFT 0x8 2586 #define SQ_V_OP1_COUNT 0x80 2587 #define SQ_WAITCNT_LGKM_SIZE 0x5 2588 #define SQ_EXP_NUM_POS 0x4 2589 #define SQ_HWREG_SIZE_SIZE 0x5 2590 #define SQ_HWREG_ID_SHIFT 0x0 2591 #define SQ_S_MOV_B32 0x3 2592 #define SQ_S_MOV_B64 0x4 2593 #define SQ_S_CMOV_B32 0x5 2594 #define SQ_S_CMOV_B64 0x6 2595 #define SQ_S_NOT_B32 0x7 2596 #define SQ_S_NOT_B64 0x8 2597 #define SQ_S_WQM_B32 0x9 2598 #define SQ_S_WQM_B64 0xa 2599 #define SQ_S_BREV_B32 0xb 2600 #define SQ_S_BREV_B64 0xc 2601 #define SQ_S_BCNT0_I32_B32 0xd 2602 #define SQ_S_BCNT0_I32_B64 0xe 2603 #define SQ_S_BCNT1_I32_B32 0xf 2604 #define SQ_S_BCNT1_I32_B64 0x10 2605 #define SQ_S_FF0_I32_B32 0x11 2606 #define SQ_S_FF0_I32_B64 0x12 2607 #define SQ_S_FF1_I32_B32 0x13 2608 #define SQ_S_FF1_I32_B64 0x14 2609 #define SQ_S_FLBIT_I32_B32 0x15 2610 #define SQ_S_FLBIT_I32_B64 0x16 2611 #define SQ_S_FLBIT_I32 0x17 2612 #define SQ_S_FLBIT_I32_I64 0x18 2613 #define SQ_S_SEXT_I32_I8 0x19 2614 #define SQ_S_SEXT_I32_I16 0x1a 2615 #define SQ_S_BITSET0_B32 0x1b 2616 #define SQ_S_BITSET0_B64 0x1c 2617 #define SQ_S_BITSET1_B32 0x1d 2618 #define SQ_S_BITSET1_B64 0x1e 2619 #define SQ_S_GETPC_B64 0x1f 2620 #define SQ_S_SETPC_B64 0x20 2621 #define SQ_S_SWAPPC_B64 0x21 2622 #define SQ_S_RFE_B64 0x22 2623 #define SQ_S_AND_SAVEEXEC_B64 0x24 2624 #define SQ_S_OR_SAVEEXEC_B64 0x25 2625 #define SQ_S_XOR_SAVEEXEC_B64 0x26 2626 #define SQ_S_ANDN2_SAVEEXEC_B64 0x27 2627 #define SQ_S_ORN2_SAVEEXEC_B64 0x28 2628 #define SQ_S_NAND_SAVEEXEC_B64 0x29 2629 #define SQ_S_NOR_SAVEEXEC_B64 0x2a 2630 #define SQ_S_XNOR_SAVEEXEC_B64 0x2b 2631 #define SQ_S_QUADMASK_B32 0x2c 2632 #define SQ_S_QUADMASK_B64 0x2d 2633 #define SQ_S_MOVRELS_B32 0x2e 2634 #define SQ_S_MOVRELS_B64 0x2f 2635 #define SQ_S_MOVRELD_B32 0x30 2636 #define SQ_S_MOVRELD_B64 0x31 2637 #define SQ_S_CBRANCH_JOIN 0x32 2638 #define SQ_S_MOV_REGRD_B32 0x33 2639 #define SQ_S_ABS_I32 0x34 2640 #define SQ_S_MOV_FED_B32 0x35 2641 #define SQ_ATTR0 0x0 2642 #define SQ_S_MOVK_I32 0x0 2643 #define SQ_S_CMOVK_I32 0x2 2644 #define SQ_S_CMPK_EQ_I32 0x3 2645 #define SQ_S_CMPK_LG_I32 0x4 2646 #define SQ_S_CMPK_GT_I32 0x5 2647 #define SQ_S_CMPK_GE_I32 0x6 2648 #define SQ_S_CMPK_LT_I32 0x7 2649 #define SQ_S_CMPK_LE_I32 0x8 2650 #define SQ_S_CMPK_EQ_U32 0x9 2651 #define SQ_S_CMPK_LG_U32 0xa 2652 #define SQ_S_CMPK_GT_U32 0xb 2653 #define SQ_S_CMPK_GE_U32 0xc 2654 #define SQ_S_CMPK_LT_U32 0xd 2655 #define SQ_S_CMPK_LE_U32 0xe 2656 #define SQ_S_ADDK_I32 0xf 2657 #define SQ_S_MULK_I32 0x10 2658 #define SQ_S_CBRANCH_I_FORK 0x11 2659 #define SQ_S_GETREG_B32 0x12 2660 #define SQ_S_SETREG_B32 0x13 2661 #define SQ_S_GETREG_REGRD_B32 0x14 2662 #define SQ_S_SETREG_IMM32_B32 0x15 2663 #define SQ_TBA_LO 0x6c 2664 #define SQ_TBA_HI 0x6d 2665 #define SQ_TMA_LO 0x6e 2666 #define SQ_TMA_HI 0x6f 2667 #define SQ_TTMP0 0x70 2668 #define SQ_TTMP1 0x71 2669 #define SQ_TTMP2 0x72 2670 #define SQ_TTMP3 0x73 2671 #define SQ_TTMP4 0x74 2672 #define SQ_TTMP5 0x75 2673 #define SQ_TTMP6 0x76 2674 #define SQ_TTMP7 0x77 2675 #define SQ_TTMP8 0x78 2676 #define SQ_TTMP9 0x79 2677 #define SQ_TTMP10 0x7a 2678 #define SQ_TTMP11 0x7b 2679 #define SQ_VGPR0 0x0 2680 #define SQ_EXP 0x0 2681 #define SQ_EXP_MRT0 0x0 2682 #define SQ_EXP_MRTZ 0x8 2683 #define SQ_EXP_NULL 0x9 2684 #define SQ_EXP_POS0 0xc 2685 #define SQ_EXP_PARAM0 0x20 2686 #define SQ_CNT1 0x0 2687 #define SQ_CNT2 0x1 2688 #define SQ_CNT3 0x2 2689 #define SQ_CNT4 0x3 2690 #define SQ_F 0x0 2691 #define SQ_LT 0x1 2692 #define SQ_EQ 0x2 2693 #define SQ_LE 0x3 2694 #define SQ_GT 0x4 2695 #define SQ_LG 0x5 2696 #define SQ_GE 0x6 2697 #define SQ_O 0x7 2698 #define SQ_U 0x8 2699 #define SQ_NGE 0x9 2700 #define SQ_NLG 0xa 2701 #define SQ_NGT 0xb 2702 #define SQ_NLE 0xc 2703 #define SQ_NEQ 0xd 2704 #define SQ_NLT 0xe 2705 #define SQ_TRU 0xf 2706 #define SQ_V_CMP_F_F32 0x0 2707 #define SQ_V_CMP_LT_F32 0x1 2708 #define SQ_V_CMP_EQ_F32 0x2 2709 #define SQ_V_CMP_LE_F32 0x3 2710 #define SQ_V_CMP_GT_F32 0x4 2711 #define SQ_V_CMP_LG_F32 0x5 2712 #define SQ_V_CMP_GE_F32 0x6 2713 #define SQ_V_CMP_O_F32 0x7 2714 #define SQ_V_CMP_U_F32 0x8 2715 #define SQ_V_CMP_NGE_F32 0x9 2716 #define SQ_V_CMP_NLG_F32 0xa 2717 #define SQ_V_CMP_NGT_F32 0xb 2718 #define SQ_V_CMP_NLE_F32 0xc 2719 #define SQ_V_CMP_NEQ_F32 0xd 2720 #define SQ_V_CMP_NLT_F32 0xe 2721 #define SQ_V_CMP_TRU_F32 0xf 2722 #define SQ_V_CMPX_F_F32 0x10 2723 #define SQ_V_CMPX_LT_F32 0x11 2724 #define SQ_V_CMPX_EQ_F32 0x12 2725 #define SQ_V_CMPX_LE_F32 0x13 2726 #define SQ_V_CMPX_GT_F32 0x14 2727 #define SQ_V_CMPX_LG_F32 0x15 2728 #define SQ_V_CMPX_GE_F32 0x16 2729 #define SQ_V_CMPX_O_F32 0x17 2730 #define SQ_V_CMPX_U_F32 0x18 2731 #define SQ_V_CMPX_NGE_F32 0x19 2732 #define SQ_V_CMPX_NLG_F32 0x1a 2733 #define SQ_V_CMPX_NGT_F32 0x1b 2734 #define SQ_V_CMPX_NLE_F32 0x1c 2735 #define SQ_V_CMPX_NEQ_F32 0x1d 2736 #define SQ_V_CMPX_NLT_F32 0x1e 2737 #define SQ_V_CMPX_TRU_F32 0x1f 2738 #define SQ_V_CMP_F_F64 0x20 2739 #define SQ_V_CMP_LT_F64 0x21 2740 #define SQ_V_CMP_EQ_F64 0x22 2741 #define SQ_V_CMP_LE_F64 0x23 2742 #define SQ_V_CMP_GT_F64 0x24 2743 #define SQ_V_CMP_LG_F64 0x25 2744 #define SQ_V_CMP_GE_F64 0x26 2745 #define SQ_V_CMP_O_F64 0x27 2746 #define SQ_V_CMP_U_F64 0x28 2747 #define SQ_V_CMP_NGE_F64 0x29 2748 #define SQ_V_CMP_NLG_F64 0x2a 2749 #define SQ_V_CMP_NGT_F64 0x2b 2750 #define SQ_V_CMP_NLE_F64 0x2c 2751 #define SQ_V_CMP_NEQ_F64 0x2d 2752 #define SQ_V_CMP_NLT_F64 0x2e 2753 #define SQ_V_CMP_TRU_F64 0x2f 2754 #define SQ_V_CMPX_F_F64 0x30 2755 #define SQ_V_CMPX_LT_F64 0x31 2756 #define SQ_V_CMPX_EQ_F64 0x32 2757 #define SQ_V_CMPX_LE_F64 0x33 2758 #define SQ_V_CMPX_GT_F64 0x34 2759 #define SQ_V_CMPX_LG_F64 0x35 2760 #define SQ_V_CMPX_GE_F64 0x36 2761 #define SQ_V_CMPX_O_F64 0x37 2762 #define SQ_V_CMPX_U_F64 0x38 2763 #define SQ_V_CMPX_NGE_F64 0x39 2764 #define SQ_V_CMPX_NLG_F64 0x3a 2765 #define SQ_V_CMPX_NGT_F64 0x3b 2766 #define SQ_V_CMPX_NLE_F64 0x3c 2767 #define SQ_V_CMPX_NEQ_F64 0x3d 2768 #define SQ_V_CMPX_NLT_F64 0x3e 2769 #define SQ_V_CMPX_TRU_F64 0x3f 2770 #define SQ_V_CMPS_F_F32 0x40 2771 #define SQ_V_CMPS_LT_F32 0x41 2772 #define SQ_V_CMPS_EQ_F32 0x42 2773 #define SQ_V_CMPS_LE_F32 0x43 2774 #define SQ_V_CMPS_GT_F32 0x44 2775 #define SQ_V_CMPS_LG_F32 0x45 2776 #define SQ_V_CMPS_GE_F32 0x46 2777 #define SQ_V_CMPS_O_F32 0x47 2778 #define SQ_V_CMPS_U_F32 0x48 2779 #define SQ_V_CMPS_NGE_F32 0x49 2780 #define SQ_V_CMPS_NLG_F32 0x4a 2781 #define SQ_V_CMPS_NGT_F32 0x4b 2782 #define SQ_V_CMPS_NLE_F32 0x4c 2783 #define SQ_V_CMPS_NEQ_F32 0x4d 2784 #define SQ_V_CMPS_NLT_F32 0x4e 2785 #define SQ_V_CMPS_TRU_F32 0x4f 2786 #define SQ_V_CMPSX_F_F32 0x50 2787 #define SQ_V_CMPSX_LT_F32 0x51 2788 #define SQ_V_CMPSX_EQ_F32 0x52 2789 #define SQ_V_CMPSX_LE_F32 0x53 2790 #define SQ_V_CMPSX_GT_F32 0x54 2791 #define SQ_V_CMPSX_LG_F32 0x55 2792 #define SQ_V_CMPSX_GE_F32 0x56 2793 #define SQ_V_CMPSX_O_F32 0x57 2794 #define SQ_V_CMPSX_U_F32 0x58 2795 #define SQ_V_CMPSX_NGE_F32 0x59 2796 #define SQ_V_CMPSX_NLG_F32 0x5a 2797 #define SQ_V_CMPSX_NGT_F32 0x5b 2798 #define SQ_V_CMPSX_NLE_F32 0x5c 2799 #define SQ_V_CMPSX_NEQ_F32 0x5d 2800 #define SQ_V_CMPSX_NLT_F32 0x5e 2801 #define SQ_V_CMPSX_TRU_F32 0x5f 2802 #define SQ_V_CMPS_F_F64 0x60 2803 #define SQ_V_CMPS_LT_F64 0x61 2804 #define SQ_V_CMPS_EQ_F64 0x62 2805 #define SQ_V_CMPS_LE_F64 0x63 2806 #define SQ_V_CMPS_GT_F64 0x64 2807 #define SQ_V_CMPS_LG_F64 0x65 2808 #define SQ_V_CMPS_GE_F64 0x66 2809 #define SQ_V_CMPS_O_F64 0x67 2810 #define SQ_V_CMPS_U_F64 0x68 2811 #define SQ_V_CMPS_NGE_F64 0x69 2812 #define SQ_V_CMPS_NLG_F64 0x6a 2813 #define SQ_V_CMPS_NGT_F64 0x6b 2814 #define SQ_V_CMPS_NLE_F64 0x6c 2815 #define SQ_V_CMPS_NEQ_F64 0x6d 2816 #define SQ_V_CMPS_NLT_F64 0x6e 2817 #define SQ_V_CMPS_TRU_F64 0x6f 2818 #define SQ_V_CMPSX_F_F64 0x70 2819 #define SQ_V_CMPSX_LT_F64 0x71 2820 #define SQ_V_CMPSX_EQ_F64 0x72 2821 #define SQ_V_CMPSX_LE_F64 0x73 2822 #define SQ_V_CMPSX_GT_F64 0x74 2823 #define SQ_V_CMPSX_LG_F64 0x75 2824 #define SQ_V_CMPSX_GE_F64 0x76 2825 #define SQ_V_CMPSX_O_F64 0x77 2826 #define SQ_V_CMPSX_U_F64 0x78 2827 #define SQ_V_CMPSX_NGE_F64 0x79 2828 #define SQ_V_CMPSX_NLG_F64 0x7a 2829 #define SQ_V_CMPSX_NGT_F64 0x7b 2830 #define SQ_V_CMPSX_NLE_F64 0x7c 2831 #define SQ_V_CMPSX_NEQ_F64 0x7d 2832 #define SQ_V_CMPSX_NLT_F64 0x7e 2833 #define SQ_V_CMPSX_TRU_F64 0x7f 2834 #define SQ_V_CMP_F_I32 0x80 2835 #define SQ_V_CMP_LT_I32 0x81 2836 #define SQ_V_CMP_EQ_I32 0x82 2837 #define SQ_V_CMP_LE_I32 0x83 2838 #define SQ_V_CMP_GT_I32 0x84 2839 #define SQ_V_CMP_NE_I32 0x85 2840 #define SQ_V_CMP_GE_I32 0x86 2841 #define SQ_V_CMP_T_I32 0x87 2842 #define SQ_V_CMPX_F_I32 0x90 2843 #define SQ_V_CMPX_LT_I32 0x91 2844 #define SQ_V_CMPX_EQ_I32 0x92 2845 #define SQ_V_CMPX_LE_I32 0x93 2846 #define SQ_V_CMPX_GT_I32 0x94 2847 #define SQ_V_CMPX_NE_I32 0x95 2848 #define SQ_V_CMPX_GE_I32 0x96 2849 #define SQ_V_CMPX_T_I32 0x97 2850 #define SQ_V_CMP_F_I64 0xa0 2851 #define SQ_V_CMP_LT_I64 0xa1 2852 #define SQ_V_CMP_EQ_I64 0xa2 2853 #define SQ_V_CMP_LE_I64 0xa3 2854 #define SQ_V_CMP_GT_I64 0xa4 2855 #define SQ_V_CMP_NE_I64 0xa5 2856 #define SQ_V_CMP_GE_I64 0xa6 2857 #define SQ_V_CMP_T_I64 0xa7 2858 #define SQ_V_CMPX_F_I64 0xb0 2859 #define SQ_V_CMPX_LT_I64 0xb1 2860 #define SQ_V_CMPX_EQ_I64 0xb2 2861 #define SQ_V_CMPX_LE_I64 0xb3 2862 #define SQ_V_CMPX_GT_I64 0xb4 2863 #define SQ_V_CMPX_NE_I64 0xb5 2864 #define SQ_V_CMPX_GE_I64 0xb6 2865 #define SQ_V_CMPX_T_I64 0xb7 2866 #define SQ_V_CMP_F_U32 0xc0 2867 #define SQ_V_CMP_LT_U32 0xc1 2868 #define SQ_V_CMP_EQ_U32 0xc2 2869 #define SQ_V_CMP_LE_U32 0xc3 2870 #define SQ_V_CMP_GT_U32 0xc4 2871 #define SQ_V_CMP_NE_U32 0xc5 2872 #define SQ_V_CMP_GE_U32 0xc6 2873 #define SQ_V_CMP_T_U32 0xc7 2874 #define SQ_V_CMPX_F_U32 0xd0 2875 #define SQ_V_CMPX_LT_U32 0xd1 2876 #define SQ_V_CMPX_EQ_U32 0xd2 2877 #define SQ_V_CMPX_LE_U32 0xd3 2878 #define SQ_V_CMPX_GT_U32 0xd4 2879 #define SQ_V_CMPX_NE_U32 0xd5 2880 #define SQ_V_CMPX_GE_U32 0xd6 2881 #define SQ_V_CMPX_T_U32 0xd7 2882 #define SQ_V_CMP_F_U64 0xe0 2883 #define SQ_V_CMP_LT_U64 0xe1 2884 #define SQ_V_CMP_EQ_U64 0xe2 2885 #define SQ_V_CMP_LE_U64 0xe3 2886 #define SQ_V_CMP_GT_U64 0xe4 2887 #define SQ_V_CMP_NE_U64 0xe5 2888 #define SQ_V_CMP_GE_U64 0xe6 2889 #define SQ_V_CMP_T_U64 0xe7 2890 #define SQ_V_CMPX_F_U64 0xf0 2891 #define SQ_V_CMPX_LT_U64 0xf1 2892 #define SQ_V_CMPX_EQ_U64 0xf2 2893 #define SQ_V_CMPX_LE_U64 0xf3 2894 #define SQ_V_CMPX_GT_U64 0xf4 2895 #define SQ_V_CMPX_NE_U64 0xf5 2896 #define SQ_V_CMPX_GE_U64 0xf6 2897 #define SQ_V_CMPX_T_U64 0xf7 2898 #define SQ_V_CMP_CLASS_F32 0x88 2899 #define SQ_V_CMPX_CLASS_F32 0x98 2900 #define SQ_V_CMP_CLASS_F64 0xa8 2901 #define SQ_V_CMPX_CLASS_F64 0xb8 2902 #define SQ_SGPR0 0x0 2903 #define SQ_F 0x0 2904 #define SQ_LT 0x1 2905 #define SQ_EQ 0x2 2906 #define SQ_LE 0x3 2907 #define SQ_GT 0x4 2908 #define SQ_NE 0x5 2909 #define SQ_GE 0x6 2910 #define SQ_T 0x7 2911 #define SQ_SRC_64_INT 0xc0 2912 #define SQ_SRC_M_1_INT 0xc1 2913 #define SQ_SRC_M_2_INT 0xc2 2914 #define SQ_SRC_M_3_INT 0xc3 2915 #define SQ_SRC_M_4_INT 0xc4 2916 #define SQ_SRC_M_5_INT 0xc5 2917 #define SQ_SRC_M_6_INT 0xc6 2918 #define SQ_SRC_M_7_INT 0xc7 2919 #define SQ_SRC_M_8_INT 0xc8 2920 #define SQ_SRC_M_9_INT 0xc9 2921 #define SQ_SRC_M_10_INT 0xca 2922 #define SQ_SRC_M_11_INT 0xcb 2923 #define SQ_SRC_M_12_INT 0xcc 2924 #define SQ_SRC_M_13_INT 0xcd 2925 #define SQ_SRC_M_14_INT 0xce 2926 #define SQ_SRC_M_15_INT 0xcf 2927 #define SQ_SRC_M_16_INT 0xd0 2928 #define SQ_SRC_0_5 0xf0 2929 #define SQ_SRC_M_0_5 0xf1 2930 #define SQ_SRC_1 0xf2 2931 #define SQ_SRC_M_1 0xf3 2932 #define SQ_SRC_2 0xf4 2933 #define SQ_SRC_M_2 0xf5 2934 #define SQ_SRC_4 0xf6 2935 #define SQ_SRC_M_4 0xf7 2936 #define SQ_SRC_0 0x80 2937 #define SQ_SRC_1_INT 0x81 2938 #define SQ_SRC_2_INT 0x82 2939 #define SQ_SRC_3_INT 0x83 2940 #define SQ_SRC_4_INT 0x84 2941 #define SQ_SRC_5_INT 0x85 2942 #define SQ_SRC_6_INT 0x86 2943 #define SQ_SRC_7_INT 0x87 2944 #define SQ_SRC_8_INT 0x88 2945 #define SQ_SRC_9_INT 0x89 2946 #define SQ_SRC_10_INT 0x8a 2947 #define SQ_SRC_11_INT 0x8b 2948 #define SQ_SRC_12_INT 0x8c 2949 #define SQ_SRC_13_INT 0x8d 2950 #define SQ_SRC_14_INT 0x8e 2951 #define SQ_SRC_15_INT 0x8f 2952 #define SQ_SRC_16_INT 0x90 2953 #define SQ_SRC_17_INT 0x91 2954 #define SQ_SRC_18_INT 0x92 2955 #define SQ_SRC_19_INT 0x93 2956 #define SQ_SRC_20_INT 0x94 2957 #define SQ_SRC_21_INT 0x95 2958 #define SQ_SRC_22_INT 0x96 2959 #define SQ_SRC_23_INT 0x97 2960 #define SQ_SRC_24_INT 0x98 2961 #define SQ_SRC_25_INT 0x99 2962 #define SQ_SRC_26_INT 0x9a 2963 #define SQ_SRC_27_INT 0x9b 2964 #define SQ_SRC_28_INT 0x9c 2965 #define SQ_SRC_29_INT 0x9d 2966 #define SQ_SRC_30_INT 0x9e 2967 #define SQ_SRC_31_INT 0x9f 2968 #define SQ_SRC_32_INT 0xa0 2969 #define SQ_SRC_33_INT 0xa1 2970 #define SQ_SRC_34_INT 0xa2 2971 #define SQ_SRC_35_INT 0xa3 2972 #define SQ_SRC_36_INT 0xa4 2973 #define SQ_SRC_37_INT 0xa5 2974 #define SQ_SRC_38_INT 0xa6 2975 #define SQ_SRC_39_INT 0xa7 2976 #define SQ_SRC_40_INT 0xa8 2977 #define SQ_SRC_41_INT 0xa9 2978 #define SQ_SRC_42_INT 0xaa 2979 #define SQ_SRC_43_INT 0xab 2980 #define SQ_SRC_44_INT 0xac 2981 #define SQ_SRC_45_INT 0xad 2982 #define SQ_SRC_46_INT 0xae 2983 #define SQ_SRC_47_INT 0xaf 2984 #define SQ_SRC_48_INT 0xb0 2985 #define SQ_SRC_49_INT 0xb1 2986 #define SQ_SRC_50_INT 0xb2 2987 #define SQ_SRC_51_INT 0xb3 2988 #define SQ_SRC_52_INT 0xb4 2989 #define SQ_SRC_53_INT 0xb5 2990 #define SQ_SRC_54_INT 0xb6 2991 #define SQ_SRC_55_INT 0xb7 2992 #define SQ_SRC_56_INT 0xb8 2993 #define SQ_SRC_57_INT 0xb9 2994 #define SQ_SRC_58_INT 0xba 2995 #define SQ_SRC_59_INT 0xbb 2996 #define SQ_SRC_60_INT 0xbc 2997 #define SQ_SRC_61_INT 0xbd 2998 #define SQ_SRC_62_INT 0xbe 2999 #define SQ_SRC_63_INT 0xbf 3000 #define SQ_BUFFER_LOAD_FORMAT_X 0x0 3001 #define SQ_BUFFER_LOAD_FORMAT_XY 0x1 3002 #define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2 3003 #define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3 3004 #define SQ_BUFFER_STORE_FORMAT_X 0x4 3005 #define SQ_BUFFER_STORE_FORMAT_XY 0x5 3006 #define SQ_BUFFER_STORE_FORMAT_XYZ 0x6 3007 #define SQ_BUFFER_STORE_FORMAT_XYZW 0x7 3008 #define SQ_BUFFER_LOAD_UBYTE 0x8 3009 #define SQ_BUFFER_LOAD_SBYTE 0x9 3010 #define SQ_BUFFER_LOAD_USHORT 0xa 3011 #define SQ_BUFFER_LOAD_SSHORT 0xb 3012 #define SQ_BUFFER_LOAD_DWORD 0xc 3013 #define SQ_BUFFER_LOAD_DWORDX2 0xd 3014 #define SQ_BUFFER_LOAD_DWORDX4 0xe 3015 #define SQ_BUFFER_LOAD_DWORDX3 0xf 3016 #define SQ_BUFFER_STORE_BYTE 0x18 3017 #define SQ_BUFFER_STORE_SHORT 0x1a 3018 #define SQ_BUFFER_STORE_DWORD 0x1c 3019 #define SQ_BUFFER_STORE_DWORDX2 0x1d 3020 #define SQ_BUFFER_STORE_DWORDX4 0x1e 3021 #define SQ_BUFFER_STORE_DWORDX3 0x1f 3022 #define SQ_BUFFER_ATOMIC_SWAP 0x30 3023 #define SQ_BUFFER_ATOMIC_CMPSWAP 0x31 3024 #define SQ_BUFFER_ATOMIC_ADD 0x32 3025 #define SQ_BUFFER_ATOMIC_SUB 0x33 3026 #define SQ_BUFFER_ATOMIC_SMIN 0x35 3027 #define SQ_BUFFER_ATOMIC_UMIN 0x36 3028 #define SQ_BUFFER_ATOMIC_SMAX 0x37 3029 #define SQ_BUFFER_ATOMIC_UMAX 0x38 3030 #define SQ_BUFFER_ATOMIC_AND 0x39 3031 #define SQ_BUFFER_ATOMIC_OR 0x3a 3032 #define SQ_BUFFER_ATOMIC_XOR 0x3b 3033 #define SQ_BUFFER_ATOMIC_INC 0x3c 3034 #define SQ_BUFFER_ATOMIC_DEC 0x3d 3035 #define SQ_BUFFER_ATOMIC_FCMPSWAP 0x3e 3036 #define SQ_BUFFER_ATOMIC_FMIN 0x3f 3037 #define SQ_BUFFER_ATOMIC_FMAX 0x40 3038 #define SQ_BUFFER_ATOMIC_SWAP_X2 0x50 3039 #define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51 3040 #define SQ_BUFFER_ATOMIC_ADD_X2 0x52 3041 #define SQ_BUFFER_ATOMIC_SUB_X2 0x53 3042 #define SQ_BUFFER_ATOMIC_SMIN_X2 0x55 3043 #define SQ_BUFFER_ATOMIC_UMIN_X2 0x56 3044 #define SQ_BUFFER_ATOMIC_SMAX_X2 0x57 3045 #define SQ_BUFFER_ATOMIC_UMAX_X2 0x58 3046 #define SQ_BUFFER_ATOMIC_AND_X2 0x59 3047 #define SQ_BUFFER_ATOMIC_OR_X2 0x5a 3048 #define SQ_BUFFER_ATOMIC_XOR_X2 0x5b 3049 #define SQ_BUFFER_ATOMIC_INC_X2 0x5c 3050 #define SQ_BUFFER_ATOMIC_DEC_X2 0x5d 3051 #define SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5e 3052 #define SQ_BUFFER_ATOMIC_FMIN_X2 0x5f 3053 #define SQ_BUFFER_ATOMIC_FMAX_X2 0x60 3054 #define SQ_BUFFER_WBINVL1_VOL 0x70 3055 #define SQ_BUFFER_WBINVL1 0x71 3056 #define SQ_DS_ADD_U32 0x0 3057 #define SQ_DS_SUB_U32 0x1 3058 #define SQ_DS_RSUB_U32 0x2 3059 #define SQ_DS_INC_U32 0x3 3060 #define SQ_DS_DEC_U32 0x4 3061 #define SQ_DS_MIN_I32 0x5 3062 #define SQ_DS_MAX_I32 0x6 3063 #define SQ_DS_MIN_U32 0x7 3064 #define SQ_DS_MAX_U32 0x8 3065 #define SQ_DS_AND_B32 0x9 3066 #define SQ_DS_OR_B32 0xa 3067 #define SQ_DS_XOR_B32 0xb 3068 #define SQ_DS_MSKOR_B32 0xc 3069 #define SQ_DS_WRITE_B32 0xd 3070 #define SQ_DS_WRITE2_B32 0xe 3071 #define SQ_DS_WRITE2ST64_B32 0xf 3072 #define SQ_DS_CMPST_B32 0x10 3073 #define SQ_DS_CMPST_F32 0x11 3074 #define SQ_DS_MIN_F32 0x12 3075 #define SQ_DS_MAX_F32 0x13 3076 #define SQ_DS_NOP 0x14 3077 #define SQ_DS_GWS_SEMA_RELEASE_ALL 0x18 3078 #define SQ_DS_GWS_INIT 0x19 3079 #define SQ_DS_GWS_SEMA_V 0x1a 3080 #define SQ_DS_GWS_SEMA_BR 0x1b 3081 #define SQ_DS_GWS_SEMA_P 0x1c 3082 #define SQ_DS_GWS_BARRIER 0x1d 3083 #define SQ_DS_WRITE_B8 0x1e 3084 #define SQ_DS_WRITE_B16 0x1f 3085 #define SQ_DS_ADD_RTN_U32 0x20 3086 #define SQ_DS_SUB_RTN_U32 0x21 3087 #define SQ_DS_RSUB_RTN_U32 0x22 3088 #define SQ_DS_INC_RTN_U32 0x23 3089 #define SQ_DS_DEC_RTN_U32 0x24 3090 #define SQ_DS_MIN_RTN_I32 0x25 3091 #define SQ_DS_MAX_RTN_I32 0x26 3092 #define SQ_DS_MIN_RTN_U32 0x27 3093 #define SQ_DS_MAX_RTN_U32 0x28 3094 #define SQ_DS_AND_RTN_B32 0x29 3095 #define SQ_DS_OR_RTN_B32 0x2a 3096 #define SQ_DS_XOR_RTN_B32 0x2b 3097 #define SQ_DS_MSKOR_RTN_B32 0x2c 3098 #define SQ_DS_WRXCHG_RTN_B32 0x2d 3099 #define SQ_DS_WRXCHG2_RTN_B32 0x2e 3100 #define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f 3101 #define SQ_DS_CMPST_RTN_B32 0x30 3102 #define SQ_DS_CMPST_RTN_F32 0x31 3103 #define SQ_DS_MIN_RTN_F32 0x32 3104 #define SQ_DS_MAX_RTN_F32 0x33 3105 #define SQ_DS_WRAP_RTN_B32 0x34 3106 #define SQ_DS_SWIZZLE_B32 0x35 3107 #define SQ_DS_READ_B32 0x36 3108 #define SQ_DS_READ2_B32 0x37 3109 #define SQ_DS_READ2ST64_B32 0x38 3110 #define SQ_DS_READ_I8 0x39 3111 #define SQ_DS_READ_U8 0x3a 3112 #define SQ_DS_READ_I16 0x3b 3113 #define SQ_DS_READ_U16 0x3c 3114 #define SQ_DS_CONSUME 0x3d 3115 #define SQ_DS_APPEND 0x3e 3116 #define SQ_DS_ORDERED_COUNT 0x3f 3117 #define SQ_DS_ADD_U64 0x40 3118 #define SQ_DS_SUB_U64 0x41 3119 #define SQ_DS_RSUB_U64 0x42 3120 #define SQ_DS_INC_U64 0x43 3121 #define SQ_DS_DEC_U64 0x44 3122 #define SQ_DS_MIN_I64 0x45 3123 #define SQ_DS_MAX_I64 0x46 3124 #define SQ_DS_MIN_U64 0x47 3125 #define SQ_DS_MAX_U64 0x48 3126 #define SQ_DS_AND_B64 0x49 3127 #define SQ_DS_OR_B64 0x4a 3128 #define SQ_DS_XOR_B64 0x4b 3129 #define SQ_DS_MSKOR_B64 0x4c 3130 #define SQ_DS_WRITE_B64 0x4d 3131 #define SQ_DS_WRITE2_B64 0x4e 3132 #define SQ_DS_WRITE2ST64_B64 0x4f 3133 #define SQ_DS_CMPST_B64 0x50 3134 #define SQ_DS_CMPST_F64 0x51 3135 #define SQ_DS_MIN_F64 0x52 3136 #define SQ_DS_MAX_F64 0x53 3137 #define SQ_DS_ADD_RTN_U64 0x60 3138 #define SQ_DS_SUB_RTN_U64 0x61 3139 #define SQ_DS_RSUB_RTN_U64 0x62 3140 #define SQ_DS_INC_RTN_U64 0x63 3141 #define SQ_DS_DEC_RTN_U64 0x64 3142 #define SQ_DS_MIN_RTN_I64 0x65 3143 #define SQ_DS_MAX_RTN_I64 0x66 3144 #define SQ_DS_MIN_RTN_U64 0x67 3145 #define SQ_DS_MAX_RTN_U64 0x68 3146 #define SQ_DS_AND_RTN_B64 0x69 3147 #define SQ_DS_OR_RTN_B64 0x6a 3148 #define SQ_DS_XOR_RTN_B64 0x6b 3149 #define SQ_DS_MSKOR_RTN_B64 0x6c 3150 #define SQ_DS_WRXCHG_RTN_B64 0x6d 3151 #define SQ_DS_WRXCHG2_RTN_B64 0x6e 3152 #define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f 3153 #define SQ_DS_CMPST_RTN_B64 0x70 3154 #define SQ_DS_CMPST_RTN_F64 0x71 3155 #define SQ_DS_MIN_RTN_F64 0x72 3156 #define SQ_DS_MAX_RTN_F64 0x73 3157 #define SQ_DS_READ_B64 0x76 3158 #define SQ_DS_READ2_B64 0x77 3159 #define SQ_DS_READ2ST64_B64 0x78 3160 #define SQ_DS_CONDXCHG32_RTN_B64 0x7e 3161 #define SQ_DS_ADD_SRC2_U32 0x80 3162 #define SQ_DS_SUB_SRC2_U32 0x81 3163 #define SQ_DS_RSUB_SRC2_U32 0x82 3164 #define SQ_DS_INC_SRC2_U32 0x83 3165 #define SQ_DS_DEC_SRC2_U32 0x84 3166 #define SQ_DS_MIN_SRC2_I32 0x85 3167 #define SQ_DS_MAX_SRC2_I32 0x86 3168 #define SQ_DS_MIN_SRC2_U32 0x87 3169 #define SQ_DS_MAX_SRC2_U32 0x88 3170 #define SQ_DS_AND_SRC2_B32 0x89 3171 #define SQ_DS_OR_SRC2_B32 0x8a 3172 #define SQ_DS_XOR_SRC2_B32 0x8b 3173 #define SQ_DS_WRITE_SRC2_B32 0x8d 3174 #define SQ_DS_MIN_SRC2_F32 0x92 3175 #define SQ_DS_MAX_SRC2_F32 0x93 3176 #define SQ_DS_ADD_SRC2_U64 0xc0 3177 #define SQ_DS_SUB_SRC2_U64 0xc1 3178 #define SQ_DS_RSUB_SRC2_U64 0xc2 3179 #define SQ_DS_INC_SRC2_U64 0xc3 3180 #define SQ_DS_DEC_SRC2_U64 0xc4 3181 #define SQ_DS_MIN_SRC2_I64 0xc5 3182 #define SQ_DS_MAX_SRC2_I64 0xc6 3183 #define SQ_DS_MIN_SRC2_U64 0xc7 3184 #define SQ_DS_MAX_SRC2_U64 0xc8 3185 #define SQ_DS_AND_SRC2_B64 0xc9 3186 #define SQ_DS_OR_SRC2_B64 0xca 3187 #define SQ_DS_XOR_SRC2_B64 0xcb 3188 #define SQ_DS_WRITE_SRC2_B64 0xcd 3189 #define SQ_DS_MIN_SRC2_F64 0xd2 3190 #define SQ_DS_MAX_SRC2_F64 0xd3 3191 #define SQ_DS_WRITE_B96 0xde 3192 #define SQ_DS_WRITE_B128 0xdf 3193 #define SQ_DS_CONDXCHG32_RTN_B128 0xfd 3194 #define SQ_DS_READ_B96 0xfe 3195 #define SQ_DS_READ_B128 0xff 3196 #define SQ_SRC_SCC 0xfd 3197 #define SQ_OMOD_OFF 0x0 3198 #define SQ_OMOD_M2 0x1 3199 #define SQ_OMOD_M4 0x2 3200 #define SQ_OMOD_D2 0x3 3201 #define SQ_EXP_GDS0 0x18 3202 #define SQ_GS_OP_NOP 0x0 3203 #define SQ_GS_OP_CUT 0x1 3204 #define SQ_GS_OP_EMIT 0x2 3205 #define SQ_GS_OP_EMIT_CUT 0x3 3206 #define SQ_IMAGE_LOAD 0x0 3207 #define SQ_IMAGE_LOAD_MIP 0x1 3208 #define SQ_IMAGE_LOAD_PCK 0x2 3209 #define SQ_IMAGE_LOAD_PCK_SGN 0x3 3210 #define SQ_IMAGE_LOAD_MIP_PCK 0x4 3211 #define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5 3212 #define SQ_IMAGE_STORE 0x8 3213 #define SQ_IMAGE_STORE_MIP 0x9 3214 #define SQ_IMAGE_STORE_PCK 0xa 3215 #define SQ_IMAGE_STORE_MIP_PCK 0xb 3216 #define SQ_IMAGE_GET_RESINFO 0xe 3217 #define SQ_IMAGE_ATOMIC_SWAP 0xf 3218 #define SQ_IMAGE_ATOMIC_CMPSWAP 0x10 3219 #define SQ_IMAGE_ATOMIC_ADD 0x11 3220 #define SQ_IMAGE_ATOMIC_SUB 0x12 3221 #define SQ_IMAGE_ATOMIC_SMIN 0x14 3222 #define SQ_IMAGE_ATOMIC_UMIN 0x15 3223 #define SQ_IMAGE_ATOMIC_SMAX 0x16 3224 #define SQ_IMAGE_ATOMIC_UMAX 0x17 3225 #define SQ_IMAGE_ATOMIC_AND 0x18 3226 #define SQ_IMAGE_ATOMIC_OR 0x19 3227 #define SQ_IMAGE_ATOMIC_XOR 0x1a 3228 #define SQ_IMAGE_ATOMIC_INC 0x1b 3229 #define SQ_IMAGE_ATOMIC_DEC 0x1c 3230 #define SQ_IMAGE_ATOMIC_FCMPSWAP 0x1d 3231 #define SQ_IMAGE_ATOMIC_FMIN 0x1e 3232 #define SQ_IMAGE_ATOMIC_FMAX 0x1f 3233 #define SQ_IMAGE_SAMPLE 0x20 3234 #define SQ_IMAGE_SAMPLE_CL 0x21 3235 #define SQ_IMAGE_SAMPLE_D 0x22 3236 #define SQ_IMAGE_SAMPLE_D_CL 0x23 3237 #define SQ_IMAGE_SAMPLE_L 0x24 3238 #define SQ_IMAGE_SAMPLE_B 0x25 3239 #define SQ_IMAGE_SAMPLE_B_CL 0x26 3240 #define SQ_IMAGE_SAMPLE_LZ 0x27 3241 #define SQ_IMAGE_SAMPLE_C 0x28 3242 #define SQ_IMAGE_SAMPLE_C_CL 0x29 3243 #define SQ_IMAGE_SAMPLE_C_D 0x2a 3244 #define SQ_IMAGE_SAMPLE_C_D_CL 0x2b 3245 #define SQ_IMAGE_SAMPLE_C_L 0x2c 3246 #define SQ_IMAGE_SAMPLE_C_B 0x2d 3247 #define SQ_IMAGE_SAMPLE_C_B_CL 0x2e 3248 #define SQ_IMAGE_SAMPLE_C_LZ 0x2f 3249 #define SQ_IMAGE_SAMPLE_O 0x30 3250 #define SQ_IMAGE_SAMPLE_CL_O 0x31 3251 #define SQ_IMAGE_SAMPLE_D_O 0x32 3252 #define SQ_IMAGE_SAMPLE_D_CL_O 0x33 3253 #define SQ_IMAGE_SAMPLE_L_O 0x34 3254 #define SQ_IMAGE_SAMPLE_B_O 0x35 3255 #define SQ_IMAGE_SAMPLE_B_CL_O 0x36 3256 #define SQ_IMAGE_SAMPLE_LZ_O 0x37 3257 #define SQ_IMAGE_SAMPLE_C_O 0x38 3258 #define SQ_IMAGE_SAMPLE_C_CL_O 0x39 3259 #define SQ_IMAGE_SAMPLE_C_D_O 0x3a 3260 #define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b 3261 #define SQ_IMAGE_SAMPLE_C_L_O 0x3c 3262 #define SQ_IMAGE_SAMPLE_C_B_O 0x3d 3263 #define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e 3264 #define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f 3265 #define SQ_IMAGE_GATHER4 0x40 3266 #define SQ_IMAGE_GATHER4_CL 0x41 3267 #define SQ_IMAGE_GATHER4_L 0x44 3268 #define SQ_IMAGE_GATHER4_B 0x45 3269 #define SQ_IMAGE_GATHER4_B_CL 0x46 3270 #define SQ_IMAGE_GATHER4_LZ 0x47 3271 #define SQ_IMAGE_GATHER4_C 0x48 3272 #define SQ_IMAGE_GATHER4_C_CL 0x49 3273 #define SQ_IMAGE_GATHER4_C_L 0x4c 3274 #define SQ_IMAGE_GATHER4_C_B 0x4d 3275 #define SQ_IMAGE_GATHER4_C_B_CL 0x4e 3276 #define SQ_IMAGE_GATHER4_C_LZ 0x4f 3277 #define SQ_IMAGE_GATHER4_O 0x50 3278 #define SQ_IMAGE_GATHER4_CL_O 0x51 3279 #define SQ_IMAGE_GATHER4_L_O 0x54 3280 #define SQ_IMAGE_GATHER4_B_O 0x55 3281 #define SQ_IMAGE_GATHER4_B_CL_O 0x56 3282 #define SQ_IMAGE_GATHER4_LZ_O 0x57 3283 #define SQ_IMAGE_GATHER4_C_O 0x58 3284 #define SQ_IMAGE_GATHER4_C_CL_O 0x59 3285 #define SQ_IMAGE_GATHER4_C_L_O 0x5c 3286 #define SQ_IMAGE_GATHER4_C_B_O 0x5d 3287 #define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e 3288 #define SQ_IMAGE_GATHER4_C_LZ_O 0x5f 3289 #define SQ_IMAGE_GET_LOD 0x60 3290 #define SQ_IMAGE_SAMPLE_CD 0x68 3291 #define SQ_IMAGE_SAMPLE_CD_CL 0x69 3292 #define SQ_IMAGE_SAMPLE_C_CD 0x6a 3293 #define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b 3294 #define SQ_IMAGE_SAMPLE_CD_O 0x6c 3295 #define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d 3296 #define SQ_IMAGE_SAMPLE_C_CD_O 0x6e 3297 #define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f 3298 #define SQ_IMAGE_RSRC256 0x7e 3299 #define SQ_IMAGE_SAMPLER 0x7f 3300 #define SQ_SRC_VCCZ 0xfb 3301 #define SQ_SRC_VGPR0 0x100 3302 #define SQ_DFMT_INVALID 0x0 3303 #define SQ_DFMT_8 0x1 3304 #define SQ_DFMT_16 0x2 3305 #define SQ_DFMT_8_8 0x3 3306 #define SQ_DFMT_32 0x4 3307 #define SQ_DFMT_16_16 0x5 3308 #define SQ_DFMT_10_11_11 0x6 3309 #define SQ_DFMT_11_11_10 0x7 3310 #define SQ_DFMT_10_10_10_2 0x8 3311 #define SQ_DFMT_2_10_10_10 0x9 3312 #define SQ_DFMT_8_8_8_8 0xa 3313 #define SQ_DFMT_32_32 0xb 3314 #define SQ_DFMT_16_16_16_16 0xc 3315 #define SQ_DFMT_32_32_32 0xd 3316 #define SQ_DFMT_32_32_32_32 0xe 3317 #define SQ_TBUFFER_LOAD_FORMAT_X 0x0 3318 #define SQ_TBUFFER_LOAD_FORMAT_XY 0x1 3319 #define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2 3320 #define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3 3321 #define SQ_TBUFFER_STORE_FORMAT_X 0x4 3322 #define SQ_TBUFFER_STORE_FORMAT_XY 0x5 3323 #define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6 3324 #define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7 3325 #define SQ_CHAN_X 0x0 3326 #define SQ_CHAN_Y 0x1 3327 #define SQ_CHAN_Z 0x2 3328 #define SQ_CHAN_W 0x3 3329 #define SQ_EXEC_LO 0x7e 3330 #define SQ_EXEC_HI 0x7f 3331 #define SQ_S_LOAD_DWORD 0x0 3332 #define SQ_S_LOAD_DWORDX2 0x1 3333 #define SQ_S_LOAD_DWORDX4 0x2 3334 #define SQ_S_LOAD_DWORDX8 0x3 3335 #define SQ_S_LOAD_DWORDX16 0x4 3336 #define SQ_S_BUFFER_LOAD_DWORD 0x8 3337 #define SQ_S_BUFFER_LOAD_DWORDX2 0x9 3338 #define SQ_S_BUFFER_LOAD_DWORDX4 0xa 3339 #define SQ_S_BUFFER_LOAD_DWORDX8 0xb 3340 #define SQ_S_BUFFER_LOAD_DWORDX16 0xc 3341 #define SQ_S_DCACHE_INV_VOL 0x1d 3342 #define SQ_S_MEMTIME 0x1e 3343 #define SQ_S_DCACHE_INV 0x1f 3344 #define SQ_V_NOP 0x0 3345 #define SQ_V_MOV_B32 0x1 3346 #define SQ_V_READFIRSTLANE_B32 0x2 3347 #define SQ_V_CVT_I32_F64 0x3 3348 #define SQ_V_CVT_F64_I32 0x4 3349 #define SQ_V_CVT_F32_I32 0x5 3350 #define SQ_V_CVT_F32_U32 0x6 3351 #define SQ_V_CVT_U32_F32 0x7 3352 #define SQ_V_CVT_I32_F32 0x8 3353 #define SQ_V_MOV_FED_B32 0x9 3354 #define SQ_V_CVT_F16_F32 0xa 3355 #define SQ_V_CVT_F32_F16 0xb 3356 #define SQ_V_CVT_RPI_I32_F32 0xc 3357 #define SQ_V_CVT_FLR_I32_F32 0xd 3358 #define SQ_V_CVT_OFF_F32_I4 0xe 3359 #define SQ_V_CVT_F32_F64 0xf 3360 #define SQ_V_CVT_F64_F32 0x10 3361 #define SQ_V_CVT_F32_UBYTE0 0x11 3362 #define SQ_V_CVT_F32_UBYTE1 0x12 3363 #define SQ_V_CVT_F32_UBYTE2 0x13 3364 #define SQ_V_CVT_F32_UBYTE3 0x14 3365 #define SQ_V_CVT_U32_F64 0x15 3366 #define SQ_V_CVT_F64_U32 0x16 3367 #define SQ_V_TRUNC_F64 0x17 3368 #define SQ_V_CEIL_F64 0x18 3369 #define SQ_V_RNDNE_F64 0x19 3370 #define SQ_V_FLOOR_F64 0x1a 3371 #define SQ_V_FRACT_F32 0x20 3372 #define SQ_V_TRUNC_F32 0x21 3373 #define SQ_V_CEIL_F32 0x22 3374 #define SQ_V_RNDNE_F32 0x23 3375 #define SQ_V_FLOOR_F32 0x24 3376 #define SQ_V_EXP_F32 0x25 3377 #define SQ_V_LOG_CLAMP_F32 0x26 3378 #define SQ_V_LOG_F32 0x27 3379 #define SQ_V_RCP_CLAMP_F32 0x28 3380 #define SQ_V_RCP_LEGACY_F32 0x29 3381 #define SQ_V_RCP_F32 0x2a 3382 #define SQ_V_RCP_IFLAG_F32 0x2b 3383 #define SQ_V_RSQ_CLAMP_F32 0x2c 3384 #define SQ_V_RSQ_LEGACY_F32 0x2d 3385 #define SQ_V_RSQ_F32 0x2e 3386 #define SQ_V_RCP_F64 0x2f 3387 #define SQ_V_RCP_CLAMP_F64 0x30 3388 #define SQ_V_RSQ_F64 0x31 3389 #define SQ_V_RSQ_CLAMP_F64 0x32 3390 #define SQ_V_SQRT_F32 0x33 3391 #define SQ_V_SQRT_F64 0x34 3392 #define SQ_V_SIN_F32 0x35 3393 #define SQ_V_COS_F32 0x36 3394 #define SQ_V_NOT_B32 0x37 3395 #define SQ_V_BFREV_B32 0x38 3396 #define SQ_V_FFBH_U32 0x39 3397 #define SQ_V_FFBL_B32 0x3a 3398 #define SQ_V_FFBH_I32 0x3b 3399 #define SQ_V_FREXP_EXP_I32_F64 0x3c 3400 #define SQ_V_FREXP_MANT_F64 0x3d 3401 #define SQ_V_FRACT_F64 0x3e 3402 #define SQ_V_FREXP_EXP_I32_F32 0x3f 3403 #define SQ_V_FREXP_MANT_F32 0x40 3404 #define SQ_V_CLREXCP 0x41 3405 #define SQ_V_MOVRELD_B32 0x42 3406 #define SQ_V_MOVRELS_B32 0x43 3407 #define SQ_V_MOVRELSD_B32 0x44 3408 #define SQ_V_LOG_LEGACY_F32 0x45 3409 #define SQ_V_EXP_LEGACY_F32 0x46 3410 #define SQ_NFMT_UNORM 0x0 3411 #define SQ_NFMT_SNORM 0x1 3412 #define SQ_NFMT_USCALED 0x2 3413 #define SQ_NFMT_SSCALED 0x3 3414 #define SQ_NFMT_UINT 0x4 3415 #define SQ_NFMT_SINT 0x5 3416 #define SQ_NFMT_SNORM_OGL 0x6 3417 #define SQ_NFMT_FLOAT 0x7 3418 #define SQ_V_OP1_OFFSET 0x180 3419 #define SQ_V_OP2_OFFSET 0x100 3420 #define SQ_V_OPC_OFFSET 0x0 3421 #define SQ_V_INTERP_P1_F32 0x0 3422 #define SQ_V_INTERP_P2_F32 0x1 3423 #define SQ_V_INTERP_MOV_F32 0x2 3424 #define SQ_S_NOP 0x0 3425 #define SQ_S_ENDPGM 0x1 3426 #define SQ_S_BRANCH 0x2 3427 #define SQ_S_CBRANCH_SCC0 0x4 3428 #define SQ_S_CBRANCH_SCC1 0x5 3429 #define SQ_S_CBRANCH_VCCZ 0x6 3430 #define SQ_S_CBRANCH_VCCNZ 0x7 3431 #define SQ_S_CBRANCH_EXECZ 0x8 3432 #define SQ_S_CBRANCH_EXECNZ 0x9 3433 #define SQ_S_BARRIER 0xa 3434 #define SQ_S_SETKILL 0xb 3435 #define SQ_S_WAITCNT 0xc 3436 #define SQ_S_SETHALT 0xd 3437 #define SQ_S_SLEEP 0xe 3438 #define SQ_S_SETPRIO 0xf 3439 #define SQ_S_SENDMSG 0x10 3440 #define SQ_S_SENDMSGHALT 0x11 3441 #define SQ_S_TRAP 0x12 3442 #define SQ_S_ICACHE_INV 0x13 3443 #define SQ_S_INCPERFLEVEL 0x14 3444 #define SQ_S_DECPERFLEVEL 0x15 3445 #define SQ_S_TTRACEDATA 0x16 3446 #define SQ_S_CBRANCH_CDBGSYS 0x17 3447 #define SQ_S_CBRANCH_CDBGUSER 0x18 3448 #define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19 3449 #define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a 3450 #define SQ_SRC_LITERAL 0xff 3451 #define SQ_VCC_LO 0x6a 3452 #define SQ_VCC_HI 0x6b 3453 #define SQ_PARAM_P10 0x0 3454 #define SQ_PARAM_P20 0x1 3455 #define SQ_PARAM_P0 0x2 3456 #define SQ_SRC_LDS_DIRECT 0xfe 3457 #define SQ_FLAT_SCRATCH_LO 0x68 3458 #define SQ_FLAT_SCRATCH_HI 0x69 3459 #define SQ_V_CNDMASK_B32 0x0 3460 #define SQ_V_READLANE_B32 0x1 3461 #define SQ_V_WRITELANE_B32 0x2 3462 #define SQ_V_ADD_F32 0x3 3463 #define SQ_V_SUB_F32 0x4 3464 #define SQ_V_SUBREV_F32 0x5 3465 #define SQ_V_MAC_LEGACY_F32 0x6 3466 #define SQ_V_MUL_LEGACY_F32 0x7 3467 #define SQ_V_MUL_F32 0x8 3468 #define SQ_V_MUL_I32_I24 0x9 3469 #define SQ_V_MUL_HI_I32_I24 0xa 3470 #define SQ_V_MUL_U32_U24 0xb 3471 #define SQ_V_MUL_HI_U32_U24 0xc 3472 #define SQ_V_MIN_LEGACY_F32 0xd 3473 #define SQ_V_MAX_LEGACY_F32 0xe 3474 #define SQ_V_MIN_F32 0xf 3475 #define SQ_V_MAX_F32 0x10 3476 #define SQ_V_MIN_I32 0x11 3477 #define SQ_V_MAX_I32 0x12 3478 #define SQ_V_MIN_U32 0x13 3479 #define SQ_V_MAX_U32 0x14 3480 #define SQ_V_LSHR_B32 0x15 3481 #define SQ_V_LSHRREV_B32 0x16 3482 #define SQ_V_ASHR_I32 0x17 3483 #define SQ_V_ASHRREV_I32 0x18 3484 #define SQ_V_LSHL_B32 0x19 3485 #define SQ_V_LSHLREV_B32 0x1a 3486 #define SQ_V_AND_B32 0x1b 3487 #define SQ_V_OR_B32 0x1c 3488 #define SQ_V_XOR_B32 0x1d 3489 #define SQ_V_BFM_B32 0x1e 3490 #define SQ_V_MAC_F32 0x1f 3491 #define SQ_V_MADMK_F32 0x20 3492 #define SQ_V_MADAK_F32 0x21 3493 #define SQ_V_BCNT_U32_B32 0x22 3494 #define SQ_V_MBCNT_LO_U32_B32 0x23 3495 #define SQ_V_MBCNT_HI_U32_B32 0x24 3496 #define SQ_V_ADD_I32 0x25 3497 #define SQ_V_SUB_I32 0x26 3498 #define SQ_V_SUBREV_I32 0x27 3499 #define SQ_V_ADDC_U32 0x28 3500 #define SQ_V_SUBB_U32 0x29 3501 #define SQ_V_SUBBREV_U32 0x2a 3502 #define SQ_V_LDEXP_F32 0x2b 3503 #define SQ_V_CVT_PKACCUM_U8_F32 0x2c 3504 #define SQ_V_CVT_PKNORM_I16_F32 0x2d 3505 #define SQ_V_CVT_PKNORM_U16_F32 0x2e 3506 #define SQ_V_CVT_PKRTZ_F16_F32 0x2f 3507 #define SQ_V_CVT_PK_U16_U32 0x30 3508 #define SQ_V_CVT_PK_I16_I32 0x31 3509 #define SQ_FLAT_LOAD_UBYTE 0x8 3510 #define SQ_FLAT_LOAD_SBYTE 0x9 3511 #define SQ_FLAT_LOAD_USHORT 0xa 3512 #define SQ_FLAT_LOAD_SSHORT 0xb 3513 #define SQ_FLAT_LOAD_DWORD 0xc 3514 #define SQ_FLAT_LOAD_DWORDX2 0xd 3515 #define SQ_FLAT_LOAD_DWORDX4 0xe 3516 #define SQ_FLAT_LOAD_DWORDX3 0xf 3517 #define SQ_FLAT_STORE_BYTE 0x18 3518 #define SQ_FLAT_STORE_SHORT 0x1a 3519 #define SQ_FLAT_STORE_DWORD 0x1c 3520 #define SQ_FLAT_STORE_DWORDX2 0x1d 3521 #define SQ_FLAT_STORE_DWORDX4 0x1e 3522 #define SQ_FLAT_STORE_DWORDX3 0x1f 3523 #define SQ_FLAT_ATOMIC_SWAP 0x30 3524 #define SQ_FLAT_ATOMIC_CMPSWAP 0x31 3525 #define SQ_FLAT_ATOMIC_ADD 0x32 3526 #define SQ_FLAT_ATOMIC_SUB 0x33 3527 #define SQ_FLAT_ATOMIC_SMIN 0x35 3528 #define SQ_FLAT_ATOMIC_UMIN 0x36 3529 #define SQ_FLAT_ATOMIC_SMAX 0x37 3530 #define SQ_FLAT_ATOMIC_UMAX 0x38 3531 #define SQ_FLAT_ATOMIC_AND 0x39 3532 #define SQ_FLAT_ATOMIC_OR 0x3a 3533 #define SQ_FLAT_ATOMIC_XOR 0x3b 3534 #define SQ_FLAT_ATOMIC_INC 0x3c 3535 #define SQ_FLAT_ATOMIC_DEC 0x3d 3536 #define SQ_FLAT_ATOMIC_FCMPSWAP 0x3e 3537 #define SQ_FLAT_ATOMIC_FMIN 0x3f 3538 #define SQ_FLAT_ATOMIC_FMAX 0x40 3539 #define SQ_FLAT_ATOMIC_SWAP_X2 0x50 3540 #define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x51 3541 #define SQ_FLAT_ATOMIC_ADD_X2 0x52 3542 #define SQ_FLAT_ATOMIC_SUB_X2 0x53 3543 #define SQ_FLAT_ATOMIC_SMIN_X2 0x55 3544 #define SQ_FLAT_ATOMIC_UMIN_X2 0x56 3545 #define SQ_FLAT_ATOMIC_SMAX_X2 0x57 3546 #define SQ_FLAT_ATOMIC_UMAX_X2 0x58 3547 #define SQ_FLAT_ATOMIC_AND_X2 0x59 3548 #define SQ_FLAT_ATOMIC_OR_X2 0x5a 3549 #define SQ_FLAT_ATOMIC_XOR_X2 0x5b 3550 #define SQ_FLAT_ATOMIC_INC_X2 0x5c 3551 #define SQ_FLAT_ATOMIC_DEC_X2 0x5d 3552 #define SQ_FLAT_ATOMIC_FCMPSWAP_X2 0x5e 3553 #define SQ_FLAT_ATOMIC_FMIN_X2 0x5f 3554 #define SQ_FLAT_ATOMIC_FMAX_X2 0x60 3555 #define SQ_S_CMP_EQ_I32 0x0 3556 #define SQ_S_CMP_LG_I32 0x1 3557 #define SQ_S_CMP_GT_I32 0x2 3558 #define SQ_S_CMP_GE_I32 0x3 3559 #define SQ_S_CMP_LT_I32 0x4 3560 #define SQ_S_CMP_LE_I32 0x5 3561 #define SQ_S_CMP_EQ_U32 0x6 3562 #define SQ_S_CMP_LG_U32 0x7 3563 #define SQ_S_CMP_GT_U32 0x8 3564 #define SQ_S_CMP_GE_U32 0x9 3565 #define SQ_S_CMP_LT_U32 0xa 3566 #define SQ_S_CMP_LE_U32 0xb 3567 #define SQ_S_BITCMP0_B32 0xc 3568 #define SQ_S_BITCMP1_B32 0xd 3569 #define SQ_S_BITCMP0_B64 0xe 3570 #define SQ_S_BITCMP1_B64 0xf 3571 #define SQ_S_SETVSKIP 0x10 3572 #define SQ_M0 0x7c 3573 #define SQ_V_MAD_LEGACY_F32 0x140 3574 #define SQ_V_MAD_F32 0x141 3575 #define SQ_V_MAD_I32_I24 0x142 3576 #define SQ_V_MAD_U32_U24 0x143 3577 #define SQ_V_CUBEID_F32 0x144 3578 #define SQ_V_CUBESC_F32 0x145 3579 #define SQ_V_CUBETC_F32 0x146 3580 #define SQ_V_CUBEMA_F32 0x147 3581 #define SQ_V_BFE_U32 0x148 3582 #define SQ_V_BFE_I32 0x149 3583 #define SQ_V_BFI_B32 0x14a 3584 #define SQ_V_FMA_F32 0x14b 3585 #define SQ_V_FMA_F64 0x14c 3586 #define SQ_V_LERP_U8 0x14d 3587 #define SQ_V_ALIGNBIT_B32 0x14e 3588 #define SQ_V_ALIGNBYTE_B32 0x14f 3589 #define SQ_V_MULLIT_F32 0x150 3590 #define SQ_V_MIN3_F32 0x151 3591 #define SQ_V_MIN3_I32 0x152 3592 #define SQ_V_MIN3_U32 0x153 3593 #define SQ_V_MAX3_F32 0x154 3594 #define SQ_V_MAX3_I32 0x155 3595 #define SQ_V_MAX3_U32 0x156 3596 #define SQ_V_MED3_F32 0x157 3597 #define SQ_V_MED3_I32 0x158 3598 #define SQ_V_MED3_U32 0x159 3599 #define SQ_V_SAD_U8 0x15a 3600 #define SQ_V_SAD_HI_U8 0x15b 3601 #define SQ_V_SAD_U16 0x15c 3602 #define SQ_V_SAD_U32 0x15d 3603 #define SQ_V_CVT_PK_U8_F32 0x15e 3604 #define SQ_V_DIV_FIXUP_F32 0x15f 3605 #define SQ_V_DIV_FIXUP_F64 0x160 3606 #define SQ_V_LSHL_B64 0x161 3607 #define SQ_V_LSHR_B64 0x162 3608 #define SQ_V_ASHR_I64 0x163 3609 #define SQ_V_ADD_F64 0x164 3610 #define SQ_V_MUL_F64 0x165 3611 #define SQ_V_MIN_F64 0x166 3612 #define SQ_V_MAX_F64 0x167 3613 #define SQ_V_LDEXP_F64 0x168 3614 #define SQ_V_MUL_LO_U32 0x169 3615 #define SQ_V_MUL_HI_U32 0x16a 3616 #define SQ_V_MUL_LO_I32 0x16b 3617 #define SQ_V_MUL_HI_I32 0x16c 3618 #define SQ_V_DIV_SCALE_F32 0x16d 3619 #define SQ_V_DIV_SCALE_F64 0x16e 3620 #define SQ_V_DIV_FMAS_F32 0x16f 3621 #define SQ_V_DIV_FMAS_F64 0x170 3622 #define SQ_V_MSAD_U8 0x171 3623 #define SQ_V_QSAD_PK_U16_U8 0x172 3624 #define SQ_V_MQSAD_PK_U16_U8 0x173 3625 #define SQ_V_TRIG_PREOP_F64 0x174 3626 #define SQ_V_MQSAD_U32_U8 0x175 3627 #define SQ_V_MAD_U64_U32 0x176 3628 #define SQ_V_MAD_I64_I32 0x177 3629 #define SQ_VCC_ALL 0x0 3630 #define SQ_SRC_EXECZ 0xfc 3631 #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1 3632 #define SQ_SYSMSG_OP_REG_RD 0x2 3633 #define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3 3634 #define SQ_SYSMSG_OP_TTRACE_PC 0x4 3635 #define SQ_HW_REG_MODE 0x1 3636 #define SQ_HW_REG_STATUS 0x2 3637 #define SQ_HW_REG_TRAPSTS 0x3 3638 #define SQ_HW_REG_HW_ID 0x4 3639 #define SQ_HW_REG_GPR_ALLOC 0x5 3640 #define SQ_HW_REG_LDS_ALLOC 0x6 3641 #define SQ_HW_REG_IB_STS 0x7 3642 #define SQ_HW_REG_PC_LO 0x8 3643 #define SQ_HW_REG_PC_HI 0x9 3644 #define SQ_HW_REG_INST_DW0 0xa 3645 #define SQ_HW_REG_INST_DW1 0xb 3646 #define SQ_HW_REG_IB_DBG0 0xc 3647 #define SQ_S_ADD_U32 0x0 3648 #define SQ_S_SUB_U32 0x1 3649 #define SQ_S_ADD_I32 0x2 3650 #define SQ_S_SUB_I32 0x3 3651 #define SQ_S_ADDC_U32 0x4 3652 #define SQ_S_SUBB_U32 0x5 3653 #define SQ_S_MIN_I32 0x6 3654 #define SQ_S_MIN_U32 0x7 3655 #define SQ_S_MAX_I32 0x8 3656 #define SQ_S_MAX_U32 0x9 3657 #define SQ_S_CSELECT_B32 0xa 3658 #define SQ_S_CSELECT_B64 0xb 3659 #define SQ_S_AND_B32 0xe 3660 #define SQ_S_AND_B64 0xf 3661 #define SQ_S_OR_B32 0x10 3662 #define SQ_S_OR_B64 0x11 3663 #define SQ_S_XOR_B32 0x12 3664 #define SQ_S_XOR_B64 0x13 3665 #define SQ_S_ANDN2_B32 0x14 3666 #define SQ_S_ANDN2_B64 0x15 3667 #define SQ_S_ORN2_B32 0x16 3668 #define SQ_S_ORN2_B64 0x17 3669 #define SQ_S_NAND_B32 0x18 3670 #define SQ_S_NAND_B64 0x19 3671 #define SQ_S_NOR_B32 0x1a 3672 #define SQ_S_NOR_B64 0x1b 3673 #define SQ_S_XNOR_B32 0x1c 3674 #define SQ_S_XNOR_B64 0x1d 3675 #define SQ_S_LSHL_B32 0x1e 3676 #define SQ_S_LSHL_B64 0x1f 3677 #define SQ_S_LSHR_B32 0x20 3678 #define SQ_S_LSHR_B64 0x21 3679 #define SQ_S_ASHR_I32 0x22 3680 #define SQ_S_ASHR_I64 0x23 3681 #define SQ_S_BFM_B32 0x24 3682 #define SQ_S_BFM_B64 0x25 3683 #define SQ_S_MUL_I32 0x26 3684 #define SQ_S_BFE_U32 0x27 3685 #define SQ_S_BFE_I32 0x28 3686 #define SQ_S_BFE_U64 0x29 3687 #define SQ_S_BFE_I64 0x2a 3688 #define SQ_S_CBRANCH_G_FORK 0x2b 3689 #define SQ_S_ABSDIFF_I32 0x2c 3690 #define SQ_MSG_INTERRUPT 0x1 3691 #define SQ_MSG_GS 0x2 3692 #define SQ_MSG_GS_DONE 0x3 3693 #define SQ_MSG_SYSMSG 0xf 3694 typedef enum TEX_BORDER_COLOR_TYPE { 3695 TEX_BorderColor_TransparentBlack = 0x0, 3696 TEX_BorderColor_OpaqueBlack = 0x1, 3697 TEX_BorderColor_OpaqueWhite = 0x2, 3698 TEX_BorderColor_Register = 0x3, 3699 } TEX_BORDER_COLOR_TYPE; 3700 typedef enum TEX_CHROMA_KEY { 3701 TEX_ChromaKey_Disabled = 0x0, 3702 TEX_ChromaKey_Kill = 0x1, 3703 TEX_ChromaKey_Blend = 0x2, 3704 TEX_ChromaKey_RESERVED_3 = 0x3, 3705 } TEX_CHROMA_KEY; 3706 typedef enum TEX_CLAMP { 3707 TEX_Clamp_Repeat = 0x0, 3708 TEX_Clamp_Mirror = 0x1, 3709 TEX_Clamp_ClampToLast = 0x2, 3710 TEX_Clamp_MirrorOnceToLast = 0x3, 3711 TEX_Clamp_ClampHalfToBorder = 0x4, 3712 TEX_Clamp_MirrorOnceHalfToBorder = 0x5, 3713 TEX_Clamp_ClampToBorder = 0x6, 3714 TEX_Clamp_MirrorOnceToBorder = 0x7, 3715 } TEX_CLAMP; 3716 typedef enum TEX_COORD_TYPE { 3717 TEX_CoordType_Unnormalized = 0x0, 3718 TEX_CoordType_Normalized = 0x1, 3719 } TEX_COORD_TYPE; 3720 typedef enum TEX_DEPTH_COMPARE_FUNCTION { 3721 TEX_DepthCompareFunction_Never = 0x0, 3722 TEX_DepthCompareFunction_Less = 0x1, 3723 TEX_DepthCompareFunction_Equal = 0x2, 3724 TEX_DepthCompareFunction_LessEqual = 0x3, 3725 TEX_DepthCompareFunction_Greater = 0x4, 3726 TEX_DepthCompareFunction_NotEqual = 0x5, 3727 TEX_DepthCompareFunction_GreaterEqual = 0x6, 3728 TEX_DepthCompareFunction_Always = 0x7, 3729 } TEX_DEPTH_COMPARE_FUNCTION; 3730 typedef enum TEX_DIM { 3731 TEX_Dim_1D = 0x0, 3732 TEX_Dim_2D = 0x1, 3733 TEX_Dim_3D = 0x2, 3734 TEX_Dim_CubeMap = 0x3, 3735 TEX_Dim_1DArray = 0x4, 3736 TEX_Dim_2DArray = 0x5, 3737 TEX_Dim_2D_MSAA = 0x6, 3738 TEX_Dim_2DArray_MSAA = 0x7, 3739 } TEX_DIM; 3740 typedef enum TEX_FORMAT_COMP { 3741 TEX_FormatComp_Unsigned = 0x0, 3742 TEX_FormatComp_Signed = 0x1, 3743 TEX_FormatComp_UnsignedBiased = 0x2, 3744 TEX_FormatComp_RESERVED_3 = 0x3, 3745 } TEX_FORMAT_COMP; 3746 typedef enum TEX_MAX_ANISO_RATIO { 3747 TEX_MaxAnisoRatio_1to1 = 0x0, 3748 TEX_MaxAnisoRatio_2to1 = 0x1, 3749 TEX_MaxAnisoRatio_4to1 = 0x2, 3750 TEX_MaxAnisoRatio_8to1 = 0x3, 3751 TEX_MaxAnisoRatio_16to1 = 0x4, 3752 TEX_MaxAnisoRatio_RESERVED_5 = 0x5, 3753 TEX_MaxAnisoRatio_RESERVED_6 = 0x6, 3754 TEX_MaxAnisoRatio_RESERVED_7 = 0x7, 3755 } TEX_MAX_ANISO_RATIO; 3756 typedef enum TEX_MIP_FILTER { 3757 TEX_MipFilter_None = 0x0, 3758 TEX_MipFilter_Point = 0x1, 3759 TEX_MipFilter_Linear = 0x2, 3760 TEX_MipFilter_RESERVED_3 = 0x3, 3761 } TEX_MIP_FILTER; 3762 typedef enum TEX_REQUEST_SIZE { 3763 TEX_RequestSize_32B = 0x0, 3764 TEX_RequestSize_64B = 0x1, 3765 TEX_RequestSize_128B = 0x2, 3766 TEX_RequestSize_2X64B = 0x3, 3767 } TEX_REQUEST_SIZE; 3768 typedef enum TEX_SAMPLER_TYPE { 3769 TEX_SamplerType_Invalid = 0x0, 3770 TEX_SamplerType_Valid = 0x1, 3771 } TEX_SAMPLER_TYPE; 3772 typedef enum TEX_XY_FILTER { 3773 TEX_XYFilter_Point = 0x0, 3774 TEX_XYFilter_Linear = 0x1, 3775 TEX_XYFilter_AnisoPoint = 0x2, 3776 TEX_XYFilter_AnisoLinear = 0x3, 3777 } TEX_XY_FILTER; 3778 typedef enum TEX_Z_FILTER { 3779 TEX_ZFilter_None = 0x0, 3780 TEX_ZFilter_Point = 0x1, 3781 TEX_ZFilter_Linear = 0x2, 3782 TEX_ZFilter_RESERVED_3 = 0x3, 3783 } TEX_Z_FILTER; 3784 typedef enum VTX_CLAMP { 3785 VTX_Clamp_ClampToZero = 0x0, 3786 VTX_Clamp_ClampToNAN = 0x1, 3787 } VTX_CLAMP; 3788 typedef enum VTX_FETCH_TYPE { 3789 VTX_FetchType_VertexData = 0x0, 3790 VTX_FetchType_InstanceData = 0x1, 3791 VTX_FetchType_NoIndexOffset = 0x2, 3792 VTX_FetchType_RESERVED_3 = 0x3, 3793 } VTX_FETCH_TYPE; 3794 typedef enum VTX_FORMAT_COMP_ALL { 3795 VTX_FormatCompAll_Unsigned = 0x0, 3796 VTX_FormatCompAll_Signed = 0x1, 3797 } VTX_FORMAT_COMP_ALL; 3798 typedef enum VTX_MEM_REQUEST_SIZE { 3799 VTX_MemRequestSize_32B = 0x0, 3800 VTX_MemRequestSize_64B = 0x1, 3801 } VTX_MEM_REQUEST_SIZE; 3802 typedef enum TVX_DATA_FORMAT { 3803 TVX_FMT_INVALID = 0x0, 3804 TVX_FMT_8 = 0x1, 3805 TVX_FMT_4_4 = 0x2, 3806 TVX_FMT_3_3_2 = 0x3, 3807 TVX_FMT_RESERVED_4 = 0x4, 3808 TVX_FMT_16 = 0x5, 3809 TVX_FMT_16_FLOAT = 0x6, 3810 TVX_FMT_8_8 = 0x7, 3811 TVX_FMT_5_6_5 = 0x8, 3812 TVX_FMT_6_5_5 = 0x9, 3813 TVX_FMT_1_5_5_5 = 0xa, 3814 TVX_FMT_4_4_4_4 = 0xb, 3815 TVX_FMT_5_5_5_1 = 0xc, 3816 TVX_FMT_32 = 0xd, 3817 TVX_FMT_32_FLOAT = 0xe, 3818 TVX_FMT_16_16 = 0xf, 3819 TVX_FMT_16_16_FLOAT = 0x10, 3820 TVX_FMT_8_24 = 0x11, 3821 TVX_FMT_8_24_FLOAT = 0x12, 3822 TVX_FMT_24_8 = 0x13, 3823 TVX_FMT_24_8_FLOAT = 0x14, 3824 TVX_FMT_10_11_11 = 0x15, 3825 TVX_FMT_10_11_11_FLOAT = 0x16, 3826 TVX_FMT_11_11_10 = 0x17, 3827 TVX_FMT_11_11_10_FLOAT = 0x18, 3828 TVX_FMT_2_10_10_10 = 0x19, 3829 TVX_FMT_8_8_8_8 = 0x1a, 3830 TVX_FMT_10_10_10_2 = 0x1b, 3831 TVX_FMT_X24_8_32_FLOAT = 0x1c, 3832 TVX_FMT_32_32 = 0x1d, 3833 TVX_FMT_32_32_FLOAT = 0x1e, 3834 TVX_FMT_16_16_16_16 = 0x1f, 3835 TVX_FMT_16_16_16_16_FLOAT = 0x20, 3836 TVX_FMT_RESERVED_33 = 0x21, 3837 TVX_FMT_32_32_32_32 = 0x22, 3838 TVX_FMT_32_32_32_32_FLOAT = 0x23, 3839 TVX_FMT_RESERVED_36 = 0x24, 3840 TVX_FMT_1 = 0x25, 3841 TVX_FMT_1_REVERSED = 0x26, 3842 TVX_FMT_GB_GR = 0x27, 3843 TVX_FMT_BG_RG = 0x28, 3844 TVX_FMT_32_AS_8 = 0x29, 3845 TVX_FMT_32_AS_8_8 = 0x2a, 3846 TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b, 3847 TVX_FMT_8_8_8 = 0x2c, 3848 TVX_FMT_16_16_16 = 0x2d, 3849 TVX_FMT_16_16_16_FLOAT = 0x2e, 3850 TVX_FMT_32_32_32 = 0x2f, 3851 TVX_FMT_32_32_32_FLOAT = 0x30, 3852 TVX_FMT_BC1 = 0x31, 3853 TVX_FMT_BC2 = 0x32, 3854 TVX_FMT_BC3 = 0x33, 3855 TVX_FMT_BC4 = 0x34, 3856 TVX_FMT_BC5 = 0x35, 3857 TVX_FMT_APC0 = 0x36, 3858 TVX_FMT_APC1 = 0x37, 3859 TVX_FMT_APC2 = 0x38, 3860 TVX_FMT_APC3 = 0x39, 3861 TVX_FMT_APC4 = 0x3a, 3862 TVX_FMT_APC5 = 0x3b, 3863 TVX_FMT_APC6 = 0x3c, 3864 TVX_FMT_APC7 = 0x3d, 3865 TVX_FMT_CTX1 = 0x3e, 3866 TVX_FMT_RESERVED_63 = 0x3f, 3867 } TVX_DATA_FORMAT; 3868 typedef enum TVX_DST_SEL { 3869 TVX_DstSel_X = 0x0, 3870 TVX_DstSel_Y = 0x1, 3871 TVX_DstSel_Z = 0x2, 3872 TVX_DstSel_W = 0x3, 3873 TVX_DstSel_0f = 0x4, 3874 TVX_DstSel_1f = 0x5, 3875 TVX_DstSel_RESERVED_6 = 0x6, 3876 TVX_DstSel_Mask = 0x7, 3877 } TVX_DST_SEL; 3878 typedef enum TVX_ENDIAN_SWAP { 3879 TVX_EndianSwap_None = 0x0, 3880 TVX_EndianSwap_8in16 = 0x1, 3881 TVX_EndianSwap_8in32 = 0x2, 3882 TVX_EndianSwap_8in64 = 0x3, 3883 } TVX_ENDIAN_SWAP; 3884 typedef enum TVX_INST { 3885 TVX_Inst_NormalVertexFetch = 0x0, 3886 TVX_Inst_SemanticVertexFetch = 0x1, 3887 TVX_Inst_RESERVED_2 = 0x2, 3888 TVX_Inst_LD = 0x3, 3889 TVX_Inst_GetTextureResInfo = 0x4, 3890 TVX_Inst_GetNumberOfSamples = 0x5, 3891 TVX_Inst_GetLOD = 0x6, 3892 TVX_Inst_GetGradientsH = 0x7, 3893 TVX_Inst_GetGradientsV = 0x8, 3894 TVX_Inst_SetTextureOffsets = 0x9, 3895 TVX_Inst_KeepGradients = 0xa, 3896 TVX_Inst_SetGradientsH = 0xb, 3897 TVX_Inst_SetGradientsV = 0xc, 3898 TVX_Inst_Pass = 0xd, 3899 TVX_Inst_GetBufferResInfo = 0xe, 3900 TVX_Inst_RESERVED_15 = 0xf, 3901 TVX_Inst_Sample = 0x10, 3902 TVX_Inst_Sample_L = 0x11, 3903 TVX_Inst_Sample_LB = 0x12, 3904 TVX_Inst_Sample_LZ = 0x13, 3905 TVX_Inst_Sample_G = 0x14, 3906 TVX_Inst_Gather4 = 0x15, 3907 TVX_Inst_Sample_G_LB = 0x16, 3908 TVX_Inst_Gather4_O = 0x17, 3909 TVX_Inst_Sample_C = 0x18, 3910 TVX_Inst_Sample_C_L = 0x19, 3911 TVX_Inst_Sample_C_LB = 0x1a, 3912 TVX_Inst_Sample_C_LZ = 0x1b, 3913 TVX_Inst_Sample_C_G = 0x1c, 3914 TVX_Inst_Gather4_C = 0x1d, 3915 TVX_Inst_Sample_C_G_LB = 0x1e, 3916 TVX_Inst_Gather4_C_O = 0x1f, 3917 } TVX_INST; 3918 typedef enum TVX_NUM_FORMAT_ALL { 3919 TVX_NumFormatAll_Norm = 0x0, 3920 TVX_NumFormatAll_Int = 0x1, 3921 TVX_NumFormatAll_Scaled = 0x2, 3922 TVX_NumFormatAll_RESERVED_3 = 0x3, 3923 } TVX_NUM_FORMAT_ALL; 3924 typedef enum TVX_SRC_SEL { 3925 TVX_SrcSel_X = 0x0, 3926 TVX_SrcSel_Y = 0x1, 3927 TVX_SrcSel_Z = 0x2, 3928 TVX_SrcSel_W = 0x3, 3929 TVX_SrcSel_0f = 0x4, 3930 TVX_SrcSel_1f = 0x5, 3931 } TVX_SRC_SEL; 3932 typedef enum TVX_SRF_MODE_ALL { 3933 TVX_SRFModeAll_ZCMO = 0x0, 3934 TVX_SRFModeAll_NZ = 0x1, 3935 } TVX_SRF_MODE_ALL; 3936 typedef enum TVX_TYPE { 3937 TVX_Type_InvalidTextureResource = 0x0, 3938 TVX_Type_InvalidVertexBuffer = 0x1, 3939 TVX_Type_ValidTextureResource = 0x2, 3940 TVX_Type_ValidVertexBuffer = 0x3, 3941 } TVX_TYPE; 3942 typedef enum TC_OP_MASKS { 3943 TC_OP_MASK_FLUSH_DENROM = 0x8, 3944 TC_OP_MASK_64 = 0x20, 3945 TC_OP_MASK_NO_RTN = 0x40, 3946 } TC_OP_MASKS; 3947 typedef enum TC_OP { 3948 TC_OP_READ = 0x0, 3949 TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1, 3950 TC_OP_ATOMIC_FMIN_RTN_32 = 0x2, 3951 TC_OP_ATOMIC_FMAX_RTN_32 = 0x3, 3952 TC_OP_RESERVED_FOP_RTN_32_0 = 0x4, 3953 TC_OP_RESERVED_FOP_RTN_32_1 = 0x5, 3954 TC_OP_RESERVED_FOP_RTN_32_2 = 0x6, 3955 TC_OP_ATOMIC_SWAP_RTN_32 = 0x7, 3956 TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8, 3957 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9, 3958 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa, 3959 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb, 3960 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc, 3961 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd, 3962 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe, 3963 TC_OP_ATOMIC_ADD_RTN_32 = 0xf, 3964 TC_OP_ATOMIC_SUB_RTN_32 = 0x10, 3965 TC_OP_ATOMIC_SMIN_RTN_32 = 0x11, 3966 TC_OP_ATOMIC_UMIN_RTN_32 = 0x12, 3967 TC_OP_ATOMIC_SMAX_RTN_32 = 0x13, 3968 TC_OP_ATOMIC_UMAX_RTN_32 = 0x14, 3969 TC_OP_ATOMIC_AND_RTN_32 = 0x15, 3970 TC_OP_ATOMIC_OR_RTN_32 = 0x16, 3971 TC_OP_ATOMIC_XOR_RTN_32 = 0x17, 3972 TC_OP_ATOMIC_INC_RTN_32 = 0x18, 3973 TC_OP_ATOMIC_DEC_RTN_32 = 0x19, 3974 TC_OP_WBINVL1_VOL = 0x1a, 3975 TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1b, 3976 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1c, 3977 TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1d, 3978 TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1e, 3979 TC_OP_RESERVED_NON_FLOAT_RTN_32_4 = 0x1f, 3980 TC_OP_WRITE = 0x20, 3981 TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21, 3982 TC_OP_ATOMIC_FMIN_RTN_64 = 0x22, 3983 TC_OP_ATOMIC_FMAX_RTN_64 = 0x23, 3984 TC_OP_RESERVED_FOP_RTN_64_0 = 0x24, 3985 TC_OP_RESERVED_FOP_RTN_64_1 = 0x25, 3986 TC_OP_RESERVED_FOP_RTN_64_2 = 0x26, 3987 TC_OP_ATOMIC_SWAP_RTN_64 = 0x27, 3988 TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28, 3989 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29, 3990 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a, 3991 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b, 3992 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2c, 3993 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2d, 3994 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2 = 0x2e, 3995 TC_OP_ATOMIC_ADD_RTN_64 = 0x2f, 3996 TC_OP_ATOMIC_SUB_RTN_64 = 0x30, 3997 TC_OP_ATOMIC_SMIN_RTN_64 = 0x31, 3998 TC_OP_ATOMIC_UMIN_RTN_64 = 0x32, 3999 TC_OP_ATOMIC_SMAX_RTN_64 = 0x33, 4000 TC_OP_ATOMIC_UMAX_RTN_64 = 0x34, 4001 TC_OP_ATOMIC_AND_RTN_64 = 0x35, 4002 TC_OP_ATOMIC_OR_RTN_64 = 0x36, 4003 TC_OP_ATOMIC_XOR_RTN_64 = 0x37, 4004 TC_OP_ATOMIC_INC_RTN_64 = 0x38, 4005 TC_OP_ATOMIC_DEC_RTN_64 = 0x39, 4006 TC_OP_WBL2_VOL = 0x3a, 4007 TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b, 4008 TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c, 4009 TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d, 4010 TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e, 4011 TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f, 4012 TC_OP_WBINVL1 = 0x40, 4013 TC_OP_ATOMIC_FCMPSWAP_32 = 0x41, 4014 TC_OP_ATOMIC_FMIN_32 = 0x42, 4015 TC_OP_ATOMIC_FMAX_32 = 0x43, 4016 TC_OP_RESERVED_FOP_32_0 = 0x44, 4017 TC_OP_RESERVED_FOP_32_1 = 0x45, 4018 TC_OP_RESERVED_FOP_32_2 = 0x46, 4019 TC_OP_ATOMIC_SWAP_32 = 0x47, 4020 TC_OP_ATOMIC_CMPSWAP_32 = 0x48, 4021 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49, 4022 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a, 4023 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b, 4024 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c, 4025 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d, 4026 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e, 4027 TC_OP_ATOMIC_ADD_32 = 0x4f, 4028 TC_OP_ATOMIC_SUB_32 = 0x50, 4029 TC_OP_ATOMIC_SMIN_32 = 0x51, 4030 TC_OP_ATOMIC_UMIN_32 = 0x52, 4031 TC_OP_ATOMIC_SMAX_32 = 0x53, 4032 TC_OP_ATOMIC_UMAX_32 = 0x54, 4033 TC_OP_ATOMIC_AND_32 = 0x55, 4034 TC_OP_ATOMIC_OR_32 = 0x56, 4035 TC_OP_ATOMIC_XOR_32 = 0x57, 4036 TC_OP_ATOMIC_INC_32 = 0x58, 4037 TC_OP_ATOMIC_DEC_32 = 0x59, 4038 TC_OP_INVL2_VOL = 0x5a, 4039 TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b, 4040 TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c, 4041 TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d, 4042 TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e, 4043 TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f, 4044 TC_OP_WBINVL2 = 0x60, 4045 TC_OP_ATOMIC_FCMPSWAP_64 = 0x61, 4046 TC_OP_ATOMIC_FMIN_64 = 0x62, 4047 TC_OP_ATOMIC_FMAX_64 = 0x63, 4048 TC_OP_RESERVED_FOP_64_0 = 0x64, 4049 TC_OP_RESERVED_FOP_64_1 = 0x65, 4050 TC_OP_RESERVED_FOP_64_2 = 0x66, 4051 TC_OP_ATOMIC_SWAP_64 = 0x67, 4052 TC_OP_ATOMIC_CMPSWAP_64 = 0x68, 4053 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69, 4054 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a, 4055 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b, 4056 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c, 4057 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d, 4058 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e, 4059 TC_OP_ATOMIC_ADD_64 = 0x6f, 4060 TC_OP_ATOMIC_SUB_64 = 0x70, 4061 TC_OP_ATOMIC_SMIN_64 = 0x71, 4062 TC_OP_ATOMIC_UMIN_64 = 0x72, 4063 TC_OP_ATOMIC_SMAX_64 = 0x73, 4064 TC_OP_ATOMIC_UMAX_64 = 0x74, 4065 TC_OP_ATOMIC_AND_64 = 0x75, 4066 TC_OP_ATOMIC_OR_64 = 0x76, 4067 TC_OP_ATOMIC_XOR_64 = 0x77, 4068 TC_OP_ATOMIC_INC_64 = 0x78, 4069 TC_OP_ATOMIC_DEC_64 = 0x79, 4070 TC_OP_INVL1L2_VOL = 0x7a, 4071 TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b, 4072 TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c, 4073 TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d, 4074 TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e, 4075 TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f, 4076 } TC_OP; 4077 typedef enum TC_CHUB_REQ_CREDITS_ENUM { 4078 TC_CHUB_REQ_CREDITS = 0x10, 4079 } TC_CHUB_REQ_CREDITS_ENUM; 4080 typedef enum CHUB_TC_RET_CREDITS_ENUM { 4081 CHUB_TC_RET_CREDITS = 0x20, 4082 } CHUB_TC_RET_CREDITS_ENUM; 4083 typedef enum TC_NACKS { 4084 TC_NACK_NO_FAULT = 0x0, 4085 TC_NACK_PAGE_FAULT = 0x1, 4086 TC_NACK_PROTECTION_FAULT = 0x2, 4087 TC_NACK_DATA_ERROR = 0x3, 4088 } TC_NACKS; 4089 typedef enum TCC_PERF_SEL { 4090 TCC_PERF_SEL_NONE = 0x0, 4091 TCC_PERF_SEL_CYCLE = 0x1, 4092 TCC_PERF_SEL_BUSY = 0x2, 4093 TCC_PERF_SEL_REQ = 0x3, 4094 TCC_PERF_SEL_STREAMING_REQ = 0x4, 4095 TCC_PERF_SEL_READ = 0x5, 4096 TCC_PERF_SEL_WRITE = 0x6, 4097 TCC_PERF_SEL_ATOMIC = 0x7, 4098 TCC_PERF_SEL_WBINVL2 = 0x8, 4099 TCC_PERF_SEL_WBINVL2_CYCLE = 0x9, 4100 TCC_PERF_SEL_HIT = 0xa, 4101 TCC_PERF_SEL_MISS = 0xb, 4102 TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0xc, 4103 TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0xd, 4104 TCC_PERF_SEL_WRITEBACK = 0xe, 4105 TCC_PERF_SEL_LATENCY_FIFO_FULL = 0xf, 4106 TCC_PERF_SEL_SRC_FIFO_FULL = 0x10, 4107 TCC_PERF_SEL_HOLE_FIFO_FULL = 0x11, 4108 TCC_PERF_SEL_MC_WRREQ = 0x12, 4109 TCC_PERF_SEL_MC_WRREQ_STALL = 0x13, 4110 TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x14, 4111 TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x15, 4112 TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x16, 4113 TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x17, 4114 TCC_PERF_SEL_MC_RDREQ = 0x18, 4115 TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x19, 4116 TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x1a, 4117 TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x1b, 4118 TCC_PERF_SEL_TAG_STALL = 0x1c, 4119 TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL = 0x1d, 4120 TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x1e, 4121 TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x1f, 4122 TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x20, 4123 TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x21, 4124 TCC_PERF_SEL_BUBBLE = 0x22, 4125 TCC_PERF_SEL_RETURN_ACK = 0x23, 4126 TCC_PERF_SEL_RETURN_DATA = 0x24, 4127 TCC_PERF_SEL_RETURN_HOLE = 0x25, 4128 TCC_PERF_SEL_RETURN_ACK_HOLE = 0x26, 4129 TCC_PERF_SEL_IB_STALL = 0x27, 4130 TCC_PERF_SEL_TCA_LEVEL = 0x28, 4131 TCC_PERF_SEL_HOLE_LEVEL = 0x29, 4132 TCC_PERF_SEL_MC_RDRET_NACK = 0x2a, 4133 TCC_PERF_SEL_MC_WRRET_NACK = 0x2b, 4134 TCC_PERF_SEL_EXE_REQ = 0x2c, 4135 TCC_PERF_SEL_CLIENT0_REQ = 0x40, 4136 TCC_PERF_SEL_CLIENT1_REQ = 0x41, 4137 TCC_PERF_SEL_CLIENT2_REQ = 0x42, 4138 TCC_PERF_SEL_CLIENT3_REQ = 0x43, 4139 TCC_PERF_SEL_CLIENT4_REQ = 0x44, 4140 TCC_PERF_SEL_CLIENT5_REQ = 0x45, 4141 TCC_PERF_SEL_CLIENT6_REQ = 0x46, 4142 TCC_PERF_SEL_CLIENT7_REQ = 0x47, 4143 TCC_PERF_SEL_CLIENT8_REQ = 0x48, 4144 TCC_PERF_SEL_CLIENT9_REQ = 0x49, 4145 TCC_PERF_SEL_CLIENT10_REQ = 0x4a, 4146 TCC_PERF_SEL_CLIENT11_REQ = 0x4b, 4147 TCC_PERF_SEL_CLIENT12_REQ = 0x4c, 4148 TCC_PERF_SEL_CLIENT13_REQ = 0x4d, 4149 TCC_PERF_SEL_CLIENT14_REQ = 0x4e, 4150 TCC_PERF_SEL_CLIENT15_REQ = 0x4f, 4151 TCC_PERF_SEL_CLIENT16_REQ = 0x50, 4152 TCC_PERF_SEL_CLIENT17_REQ = 0x51, 4153 TCC_PERF_SEL_CLIENT18_REQ = 0x52, 4154 TCC_PERF_SEL_CLIENT19_REQ = 0x53, 4155 TCC_PERF_SEL_CLIENT20_REQ = 0x54, 4156 TCC_PERF_SEL_CLIENT21_REQ = 0x55, 4157 TCC_PERF_SEL_CLIENT22_REQ = 0x56, 4158 TCC_PERF_SEL_CLIENT23_REQ = 0x57, 4159 TCC_PERF_SEL_CLIENT24_REQ = 0x58, 4160 TCC_PERF_SEL_CLIENT25_REQ = 0x59, 4161 TCC_PERF_SEL_CLIENT26_REQ = 0x5a, 4162 TCC_PERF_SEL_CLIENT27_REQ = 0x5b, 4163 TCC_PERF_SEL_CLIENT28_REQ = 0x5c, 4164 TCC_PERF_SEL_CLIENT29_REQ = 0x5d, 4165 TCC_PERF_SEL_CLIENT30_REQ = 0x5e, 4166 TCC_PERF_SEL_CLIENT31_REQ = 0x5f, 4167 TCC_PERF_SEL_CLIENT32_REQ = 0x60, 4168 TCC_PERF_SEL_CLIENT33_REQ = 0x61, 4169 TCC_PERF_SEL_CLIENT34_REQ = 0x62, 4170 TCC_PERF_SEL_CLIENT35_REQ = 0x63, 4171 TCC_PERF_SEL_CLIENT36_REQ = 0x64, 4172 TCC_PERF_SEL_CLIENT37_REQ = 0x65, 4173 TCC_PERF_SEL_CLIENT38_REQ = 0x66, 4174 TCC_PERF_SEL_CLIENT39_REQ = 0x67, 4175 TCC_PERF_SEL_CLIENT40_REQ = 0x68, 4176 TCC_PERF_SEL_CLIENT41_REQ = 0x69, 4177 TCC_PERF_SEL_CLIENT42_REQ = 0x6a, 4178 TCC_PERF_SEL_CLIENT43_REQ = 0x6b, 4179 TCC_PERF_SEL_CLIENT44_REQ = 0x6c, 4180 TCC_PERF_SEL_CLIENT45_REQ = 0x6d, 4181 TCC_PERF_SEL_CLIENT46_REQ = 0x6e, 4182 TCC_PERF_SEL_CLIENT47_REQ = 0x6f, 4183 TCC_PERF_SEL_CLIENT48_REQ = 0x70, 4184 TCC_PERF_SEL_CLIENT49_REQ = 0x71, 4185 TCC_PERF_SEL_CLIENT50_REQ = 0x72, 4186 TCC_PERF_SEL_CLIENT51_REQ = 0x73, 4187 TCC_PERF_SEL_CLIENT52_REQ = 0x74, 4188 TCC_PERF_SEL_CLIENT53_REQ = 0x75, 4189 TCC_PERF_SEL_CLIENT54_REQ = 0x76, 4190 TCC_PERF_SEL_CLIENT55_REQ = 0x77, 4191 TCC_PERF_SEL_CLIENT56_REQ = 0x78, 4192 TCC_PERF_SEL_CLIENT57_REQ = 0x79, 4193 TCC_PERF_SEL_CLIENT58_REQ = 0x7a, 4194 TCC_PERF_SEL_CLIENT59_REQ = 0x7b, 4195 TCC_PERF_SEL_CLIENT60_REQ = 0x7c, 4196 TCC_PERF_SEL_CLIENT61_REQ = 0x7d, 4197 TCC_PERF_SEL_CLIENT62_REQ = 0x7e, 4198 TCC_PERF_SEL_CLIENT63_REQ = 0x7f, 4199 TCC_PERF_SEL_NORMAL_WRITEBACK = 0x80, 4200 TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK = 0x81, 4201 TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x82, 4202 TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x83, 4203 TCC_PERF_SEL_NORMAL_EVICT = 0x84, 4204 TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT = 0x85, 4205 TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT = 0x86, 4206 TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT = 0x87, 4207 TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x88, 4208 TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x89, 4209 TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT = 0x8a, 4210 TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE = 0x8b, 4211 TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE = 0x8c, 4212 TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE = 0x8d, 4213 TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x8e, 4214 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x8f, 4215 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE = 0x90, 4216 TCC_PERF_SEL_TC_OP_WBL2_VOL_START = 0x91, 4217 TCC_PERF_SEL_TC_OP_INVL2_VOL_START = 0x92, 4218 TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START = 0x93, 4219 TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x94, 4220 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x95, 4221 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x96, 4222 TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH = 0x97, 4223 TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH = 0x98, 4224 TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH = 0x99, 4225 TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x9a, 4226 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x9b, 4227 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH = 0x9c, 4228 TCC_PERF_SEL_VOL_MC_WRREQ = 0x9d, 4229 TCC_PERF_SEL_VOL_MC_RDREQ = 0x9e, 4230 TCC_PERF_SEL_VOL_REQ = 0x9f, 4231 } TCC_PERF_SEL; 4232 typedef enum TCA_PERF_SEL { 4233 TCA_PERF_SEL_NONE = 0x0, 4234 TCA_PERF_SEL_CYCLE = 0x1, 4235 TCA_PERF_SEL_BUSY = 0x2, 4236 TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3, 4237 TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4, 4238 TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5, 4239 TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6, 4240 TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7, 4241 TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8, 4242 TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9, 4243 TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa, 4244 TCA_PERF_SEL_REQ_TCC0 = 0xb, 4245 TCA_PERF_SEL_REQ_TCC1 = 0xc, 4246 TCA_PERF_SEL_REQ_TCC2 = 0xd, 4247 TCA_PERF_SEL_REQ_TCC3 = 0xe, 4248 TCA_PERF_SEL_REQ_TCC4 = 0xf, 4249 TCA_PERF_SEL_REQ_TCC5 = 0x10, 4250 TCA_PERF_SEL_REQ_TCC6 = 0x11, 4251 TCA_PERF_SEL_REQ_TCC7 = 0x12, 4252 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13, 4253 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14, 4254 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15, 4255 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16, 4256 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17, 4257 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18, 4258 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19, 4259 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a, 4260 TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b, 4261 TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c, 4262 TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, 4263 TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e, 4264 TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f, 4265 TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20, 4266 TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21, 4267 TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22, 4268 TCA_PERF_SEL_FORCED_HOLE_TCS = 0x23, 4269 TCA_PERF_SEL_REQ_TCS = 0x24, 4270 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS = 0x25, 4271 TCA_PERF_SEL_CROSSBAR_STALL_TCS = 0x26, 4272 } TCA_PERF_SEL; 4273 typedef enum TCS_PERF_SEL { 4274 TCS_PERF_SEL_NONE = 0x0, 4275 TCS_PERF_SEL_CYCLE = 0x1, 4276 TCS_PERF_SEL_BUSY = 0x2, 4277 TCS_PERF_SEL_REQ = 0x3, 4278 TCS_PERF_SEL_READ = 0x4, 4279 TCS_PERF_SEL_WRITE = 0x5, 4280 TCS_PERF_SEL_ATOMIC = 0x6, 4281 TCS_PERF_SEL_HOLE_FIFO_FULL = 0x7, 4282 TCS_PERF_SEL_REQ_FIFO_FULL = 0x8, 4283 TCS_PERF_SEL_REQ_CREDIT_STALL = 0x9, 4284 TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL = 0xa, 4285 TCS_PERF_SEL_REQ_STALL = 0xb, 4286 TCS_PERF_SEL_TCS_CHUB_REQ_SEND = 0xc, 4287 TCS_PERF_SEL_CHUB_TCS_RET_SEND = 0xd, 4288 TCS_PERF_SEL_RETURN_ACK = 0xe, 4289 TCS_PERF_SEL_RETURN_DATA = 0xf, 4290 TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL = 0x10, 4291 TCS_PERF_SEL_IB_STALL = 0x11, 4292 TCS_PERF_SEL_TCA_LEVEL = 0x12, 4293 TCS_PERF_SEL_HOLE_LEVEL = 0x13, 4294 TCS_PERF_SEL_CHUB_LEVEL = 0x14, 4295 TCS_PERF_SEL_CLIENT0_REQ = 0x40, 4296 TCS_PERF_SEL_CLIENT1_REQ = 0x41, 4297 TCS_PERF_SEL_CLIENT2_REQ = 0x42, 4298 TCS_PERF_SEL_CLIENT3_REQ = 0x43, 4299 TCS_PERF_SEL_CLIENT4_REQ = 0x44, 4300 TCS_PERF_SEL_CLIENT5_REQ = 0x45, 4301 TCS_PERF_SEL_CLIENT6_REQ = 0x46, 4302 TCS_PERF_SEL_CLIENT7_REQ = 0x47, 4303 TCS_PERF_SEL_CLIENT8_REQ = 0x48, 4304 TCS_PERF_SEL_CLIENT9_REQ = 0x49, 4305 TCS_PERF_SEL_CLIENT10_REQ = 0x4a, 4306 TCS_PERF_SEL_CLIENT11_REQ = 0x4b, 4307 TCS_PERF_SEL_CLIENT12_REQ = 0x4c, 4308 TCS_PERF_SEL_CLIENT13_REQ = 0x4d, 4309 TCS_PERF_SEL_CLIENT14_REQ = 0x4e, 4310 TCS_PERF_SEL_CLIENT15_REQ = 0x4f, 4311 TCS_PERF_SEL_CLIENT16_REQ = 0x50, 4312 TCS_PERF_SEL_CLIENT17_REQ = 0x51, 4313 TCS_PERF_SEL_CLIENT18_REQ = 0x52, 4314 TCS_PERF_SEL_CLIENT19_REQ = 0x53, 4315 TCS_PERF_SEL_CLIENT20_REQ = 0x54, 4316 TCS_PERF_SEL_CLIENT21_REQ = 0x55, 4317 TCS_PERF_SEL_CLIENT22_REQ = 0x56, 4318 TCS_PERF_SEL_CLIENT23_REQ = 0x57, 4319 TCS_PERF_SEL_CLIENT24_REQ = 0x58, 4320 TCS_PERF_SEL_CLIENT25_REQ = 0x59, 4321 TCS_PERF_SEL_CLIENT26_REQ = 0x5a, 4322 TCS_PERF_SEL_CLIENT27_REQ = 0x5b, 4323 TCS_PERF_SEL_CLIENT28_REQ = 0x5c, 4324 TCS_PERF_SEL_CLIENT29_REQ = 0x5d, 4325 TCS_PERF_SEL_CLIENT30_REQ = 0x5e, 4326 TCS_PERF_SEL_CLIENT31_REQ = 0x5f, 4327 TCS_PERF_SEL_CLIENT32_REQ = 0x60, 4328 TCS_PERF_SEL_CLIENT33_REQ = 0x61, 4329 TCS_PERF_SEL_CLIENT34_REQ = 0x62, 4330 TCS_PERF_SEL_CLIENT35_REQ = 0x63, 4331 TCS_PERF_SEL_CLIENT36_REQ = 0x64, 4332 TCS_PERF_SEL_CLIENT37_REQ = 0x65, 4333 TCS_PERF_SEL_CLIENT38_REQ = 0x66, 4334 TCS_PERF_SEL_CLIENT39_REQ = 0x67, 4335 TCS_PERF_SEL_CLIENT40_REQ = 0x68, 4336 TCS_PERF_SEL_CLIENT41_REQ = 0x69, 4337 TCS_PERF_SEL_CLIENT42_REQ = 0x6a, 4338 TCS_PERF_SEL_CLIENT43_REQ = 0x6b, 4339 TCS_PERF_SEL_CLIENT44_REQ = 0x6c, 4340 TCS_PERF_SEL_CLIENT45_REQ = 0x6d, 4341 TCS_PERF_SEL_CLIENT46_REQ = 0x6e, 4342 TCS_PERF_SEL_CLIENT47_REQ = 0x6f, 4343 TCS_PERF_SEL_CLIENT48_REQ = 0x70, 4344 TCS_PERF_SEL_CLIENT49_REQ = 0x71, 4345 TCS_PERF_SEL_CLIENT50_REQ = 0x72, 4346 TCS_PERF_SEL_CLIENT51_REQ = 0x73, 4347 TCS_PERF_SEL_CLIENT52_REQ = 0x74, 4348 TCS_PERF_SEL_CLIENT53_REQ = 0x75, 4349 TCS_PERF_SEL_CLIENT54_REQ = 0x76, 4350 TCS_PERF_SEL_CLIENT55_REQ = 0x77, 4351 TCS_PERF_SEL_CLIENT56_REQ = 0x78, 4352 TCS_PERF_SEL_CLIENT57_REQ = 0x79, 4353 TCS_PERF_SEL_CLIENT58_REQ = 0x7a, 4354 TCS_PERF_SEL_CLIENT59_REQ = 0x7b, 4355 TCS_PERF_SEL_CLIENT60_REQ = 0x7c, 4356 TCS_PERF_SEL_CLIENT61_REQ = 0x7d, 4357 TCS_PERF_SEL_CLIENT62_REQ = 0x7e, 4358 TCS_PERF_SEL_CLIENT63_REQ = 0x7f, 4359 } TCS_PERF_SEL; 4360 typedef enum TA_TC_ADDR_MODES { 4361 TA_TC_ADDR_MODE_DEFAULT = 0x0, 4362 TA_TC_ADDR_MODE_COMP0 = 0x1, 4363 TA_TC_ADDR_MODE_COMP1 = 0x2, 4364 TA_TC_ADDR_MODE_COMP2 = 0x3, 4365 TA_TC_ADDR_MODE_COMP3 = 0x4, 4366 TA_TC_ADDR_MODE_UNALIGNED = 0x5, 4367 TA_TC_ADDR_MODE_BORDER_COLOR = 0x6, 4368 } TA_TC_ADDR_MODES; 4369 typedef enum TA_PERFCOUNT_SEL { 4370 TA_PERF_SEL_ta_busy = 0x0, 4371 TA_PERF_SEL_sh_fifo_busy = 0x1, 4372 TA_PERF_SEL_sh_fifo_cmd_busy = 0x2, 4373 TA_PERF_SEL_sh_fifo_addr_busy = 0x3, 4374 TA_PERF_SEL_sh_fifo_data_busy = 0x4, 4375 TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5, 4376 TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6, 4377 TA_PERF_SEL_gradient_busy = 0x7, 4378 TA_PERF_SEL_gradient_fifo_busy = 0x8, 4379 TA_PERF_SEL_lod_busy = 0x9, 4380 TA_PERF_SEL_lod_fifo_busy = 0xa, 4381 TA_PERF_SEL_addresser_busy = 0xb, 4382 TA_PERF_SEL_addresser_fifo_busy = 0xc, 4383 TA_PERF_SEL_aligner_busy = 0xd, 4384 TA_PERF_SEL_write_path_busy = 0xe, 4385 TA_PERF_SEL_RESERVED_15 = 0xf, 4386 TA_PERF_SEL_sq_ta_cmd_cycles = 0x10, 4387 TA_PERF_SEL_sp_ta_addr_cycles = 0x11, 4388 TA_PERF_SEL_sp_ta_data_cycles = 0x12, 4389 TA_PERF_SEL_ta_fa_data_state_cycles = 0x13, 4390 TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14, 4391 TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15, 4392 TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16, 4393 TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17, 4394 TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18, 4395 TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19, 4396 TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a, 4397 TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b, 4398 TA_PERF_SEL_RESERVED_28 = 0x1c, 4399 TA_PERF_SEL_RESERVED_29 = 0x1d, 4400 TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e, 4401 TA_PERF_SEL_sh_fifo_data_cycles = 0x1f, 4402 TA_PERF_SEL_total_wavefronts = 0x20, 4403 TA_PERF_SEL_gradient_cycles = 0x21, 4404 TA_PERF_SEL_walker_cycles = 0x22, 4405 TA_PERF_SEL_aligner_cycles = 0x23, 4406 TA_PERF_SEL_image_wavefronts = 0x24, 4407 TA_PERF_SEL_image_read_wavefronts = 0x25, 4408 TA_PERF_SEL_image_write_wavefronts = 0x26, 4409 TA_PERF_SEL_image_atomic_wavefronts = 0x27, 4410 TA_PERF_SEL_image_total_cycles = 0x28, 4411 TA_PERF_SEL_RESERVED_41 = 0x29, 4412 TA_PERF_SEL_RESERVED_42 = 0x2a, 4413 TA_PERF_SEL_RESERVED_43 = 0x2b, 4414 TA_PERF_SEL_buffer_wavefronts = 0x2c, 4415 TA_PERF_SEL_buffer_read_wavefronts = 0x2d, 4416 TA_PERF_SEL_buffer_write_wavefronts = 0x2e, 4417 TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f, 4418 TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30, 4419 TA_PERF_SEL_buffer_total_cycles = 0x31, 4420 TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32, 4421 TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33, 4422 TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34, 4423 TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35, 4424 TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36, 4425 TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37, 4426 TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38, 4427 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39, 4428 TA_PERF_SEL_addresser_stalled_cycles = 0x3a, 4429 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b, 4430 TA_PERF_SEL_aniso_stalled_cycles = 0x3c, 4431 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d, 4432 TA_PERF_SEL_deriv_stalled_cycles = 0x3e, 4433 TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f, 4434 TA_PERF_SEL_color_1_cycle_pixels = 0x40, 4435 TA_PERF_SEL_color_2_cycle_pixels = 0x41, 4436 TA_PERF_SEL_color_3_cycle_pixels = 0x42, 4437 TA_PERF_SEL_color_4_cycle_pixels = 0x43, 4438 TA_PERF_SEL_mip_1_cycle_pixels = 0x44, 4439 TA_PERF_SEL_mip_2_cycle_pixels = 0x45, 4440 TA_PERF_SEL_vol_1_cycle_pixels = 0x46, 4441 TA_PERF_SEL_vol_2_cycle_pixels = 0x47, 4442 TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48, 4443 TA_PERF_SEL_mipmap_lod_0_samples = 0x49, 4444 TA_PERF_SEL_mipmap_lod_1_samples = 0x4a, 4445 TA_PERF_SEL_mipmap_lod_2_samples = 0x4b, 4446 TA_PERF_SEL_mipmap_lod_3_samples = 0x4c, 4447 TA_PERF_SEL_mipmap_lod_4_samples = 0x4d, 4448 TA_PERF_SEL_mipmap_lod_5_samples = 0x4e, 4449 TA_PERF_SEL_mipmap_lod_6_samples = 0x4f, 4450 TA_PERF_SEL_mipmap_lod_7_samples = 0x50, 4451 TA_PERF_SEL_mipmap_lod_8_samples = 0x51, 4452 TA_PERF_SEL_mipmap_lod_9_samples = 0x52, 4453 TA_PERF_SEL_mipmap_lod_10_samples = 0x53, 4454 TA_PERF_SEL_mipmap_lod_11_samples = 0x54, 4455 TA_PERF_SEL_mipmap_lod_12_samples = 0x55, 4456 TA_PERF_SEL_mipmap_lod_13_samples = 0x56, 4457 TA_PERF_SEL_mipmap_lod_14_samples = 0x57, 4458 TA_PERF_SEL_mipmap_invalid_samples = 0x58, 4459 TA_PERF_SEL_aniso_1_cycle_quads = 0x59, 4460 TA_PERF_SEL_aniso_2_cycle_quads = 0x5a, 4461 TA_PERF_SEL_aniso_4_cycle_quads = 0x5b, 4462 TA_PERF_SEL_aniso_6_cycle_quads = 0x5c, 4463 TA_PERF_SEL_aniso_8_cycle_quads = 0x5d, 4464 TA_PERF_SEL_aniso_10_cycle_quads = 0x5e, 4465 TA_PERF_SEL_aniso_12_cycle_quads = 0x5f, 4466 TA_PERF_SEL_aniso_14_cycle_quads = 0x60, 4467 TA_PERF_SEL_aniso_16_cycle_quads = 0x61, 4468 TA_PERF_SEL_write_path_input_cycles = 0x62, 4469 TA_PERF_SEL_write_path_output_cycles = 0x63, 4470 TA_PERF_SEL_flat_wavefronts = 0x64, 4471 TA_PERF_SEL_flat_read_wavefronts = 0x65, 4472 TA_PERF_SEL_flat_write_wavefronts = 0x66, 4473 TA_PERF_SEL_flat_atomic_wavefronts = 0x67, 4474 TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68, 4475 TA_PERF_SEL_reg_sclk_vld = 0x69, 4476 TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a, 4477 TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b, 4478 TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c, 4479 TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d, 4480 TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e, 4481 } TA_PERFCOUNT_SEL; 4482 typedef enum TD_PERFCOUNT_SEL { 4483 TD_PERF_SEL_td_busy = 0x0, 4484 TD_PERF_SEL_input_busy = 0x1, 4485 TD_PERF_SEL_output_busy = 0x2, 4486 TD_PERF_SEL_lerp_busy = 0x3, 4487 TD_PERF_SEL_RESERVED_4 = 0x4, 4488 TD_PERF_SEL_reg_sclk_vld = 0x5, 4489 TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6, 4490 TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7, 4491 TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8, 4492 TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9, 4493 TD_PERF_SEL_tc_td_fifo_full = 0xa, 4494 TD_PERF_SEL_constant_state_full = 0xb, 4495 TD_PERF_SEL_sample_state_full = 0xc, 4496 TD_PERF_SEL_output_fifo_full = 0xd, 4497 TD_PERF_SEL_RESERVED_14 = 0xe, 4498 TD_PERF_SEL_tc_stall = 0xf, 4499 TD_PERF_SEL_pc_stall = 0x10, 4500 TD_PERF_SEL_gds_stall = 0x11, 4501 TD_PERF_SEL_RESERVED_18 = 0x12, 4502 TD_PERF_SEL_RESERVED_19 = 0x13, 4503 TD_PERF_SEL_gather4_wavefront = 0x14, 4504 TD_PERF_SEL_sample_c_wavefront = 0x15, 4505 TD_PERF_SEL_load_wavefront = 0x16, 4506 TD_PERF_SEL_atomic_wavefront = 0x17, 4507 TD_PERF_SEL_store_wavefront = 0x18, 4508 TD_PERF_SEL_ldfptr_wavefront = 0x19, 4509 TD_PERF_SEL_RESERVED_26 = 0x1a, 4510 TD_PERF_SEL_RESERVED_27 = 0x1b, 4511 TD_PERF_SEL_RESERVED_28 = 0x1c, 4512 TD_PERF_SEL_RESERVED_29 = 0x1d, 4513 TD_PERF_SEL_bypass_filter_wavefront = 0x1e, 4514 TD_PERF_SEL_min_max_filter_wavefront = 0x1f, 4515 TD_PERF_SEL_coalescable_wavefront = 0x20, 4516 TD_PERF_SEL_coalesced_phase = 0x21, 4517 TD_PERF_SEL_four_phase_wavefront = 0x22, 4518 TD_PERF_SEL_eight_phase_wavefront = 0x23, 4519 TD_PERF_SEL_sixteen_phase_wavefront = 0x24, 4520 TD_PERF_SEL_four_phase_forward_wavefront = 0x25, 4521 TD_PERF_SEL_write_ack_wavefront = 0x26, 4522 TD_PERF_SEL_RESERVED_39 = 0x27, 4523 TD_PERF_SEL_user_defined_border = 0x28, 4524 TD_PERF_SEL_white_border = 0x29, 4525 TD_PERF_SEL_opaque_black_border = 0x2a, 4526 TD_PERF_SEL_RESERVED_43 = 0x2b, 4527 TD_PERF_SEL_RESERVED_44 = 0x2c, 4528 TD_PERF_SEL_nack = 0x2d, 4529 TD_PERF_SEL_td_sp_traffic = 0x2e, 4530 TD_PERF_SEL_consume_gds_traffic = 0x2f, 4531 TD_PERF_SEL_addresscmd_poison = 0x30, 4532 TD_PERF_SEL_data_poison = 0x31, 4533 TD_PERF_SEL_start_cycle_0 = 0x32, 4534 TD_PERF_SEL_start_cycle_1 = 0x33, 4535 TD_PERF_SEL_start_cycle_2 = 0x34, 4536 TD_PERF_SEL_start_cycle_3 = 0x35, 4537 TD_PERF_SEL_null_cycle_output = 0x36, 4538 } TD_PERFCOUNT_SEL; 4539 typedef enum TCP_PERFCOUNT_SELECT { 4540 TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0, 4541 TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1, 4542 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2, 4543 TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3, 4544 TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4, 4545 TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5, 4546 TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6, 4547 TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7, 4548 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8, 4549 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9, 4550 TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa, 4551 TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb, 4552 TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc, 4553 TCP_PERF_SEL_TCR_RDRET_STALL = 0xd, 4554 TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe, 4555 TCP_PERF_SEL_HOLE_READ_STALL = 0xf, 4556 TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10, 4557 TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11, 4558 TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12, 4559 TCP_PERF_SEL_TCP_LATENCY = 0x13, 4560 TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14, 4561 TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15, 4562 TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16, 4563 TCP_PERF_SEL_TCC_READ_REQ = 0x17, 4564 TCP_PERF_SEL_TCC_WRITE_REQ = 0x18, 4565 TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19, 4566 TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a, 4567 TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b, 4568 TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c, 4569 TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, 4570 TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e, 4571 TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f, 4572 TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20, 4573 TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21, 4574 TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22, 4575 TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23, 4576 TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24, 4577 TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25, 4578 TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26, 4579 TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27, 4580 TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28, 4581 TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29, 4582 TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a, 4583 TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b, 4584 TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c, 4585 TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d, 4586 TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e, 4587 TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f, 4588 TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30, 4589 TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31, 4590 TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32, 4591 TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33, 4592 TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34, 4593 TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35, 4594 TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36, 4595 TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37, 4596 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38, 4597 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39, 4598 TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a, 4599 TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b, 4600 TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c, 4601 TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d, 4602 TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e, 4603 TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f, 4604 TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40, 4605 TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41, 4606 TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42, 4607 TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43, 4608 TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44, 4609 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45, 4610 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46, 4611 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47, 4612 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48, 4613 TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49, 4614 TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a, 4615 TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b, 4616 TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c, 4617 TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d, 4618 TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e, 4619 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f, 4620 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50, 4621 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51, 4622 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52, 4623 TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53, 4624 TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54, 4625 TCP_PERF_SEL_ARR_1D_THIN1 = 0x55, 4626 TCP_PERF_SEL_ARR_1D_THICK = 0x56, 4627 TCP_PERF_SEL_ARR_2D_THIN1 = 0x57, 4628 TCP_PERF_SEL_ARR_2D_THICK = 0x58, 4629 TCP_PERF_SEL_ARR_2D_XTHICK = 0x59, 4630 TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a, 4631 TCP_PERF_SEL_ARR_3D_THICK = 0x5b, 4632 TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c, 4633 TCP_PERF_SEL_DIM_1D = 0x5d, 4634 TCP_PERF_SEL_DIM_2D = 0x5e, 4635 TCP_PERF_SEL_DIM_3D = 0x5f, 4636 TCP_PERF_SEL_DIM_1D_ARRAY = 0x60, 4637 TCP_PERF_SEL_DIM_2D_ARRAY = 0x61, 4638 TCP_PERF_SEL_DIM_2D_MSAA = 0x62, 4639 TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63, 4640 TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64, 4641 TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65, 4642 TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66, 4643 TCP_PERF_SEL_TAGRAM0_REQ = 0x67, 4644 TCP_PERF_SEL_TAGRAM1_REQ = 0x68, 4645 TCP_PERF_SEL_TAGRAM2_REQ = 0x69, 4646 TCP_PERF_SEL_TAGRAM3_REQ = 0x6a, 4647 TCP_PERF_SEL_GATE_EN1 = 0x6b, 4648 TCP_PERF_SEL_GATE_EN2 = 0x6c, 4649 TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d, 4650 TCP_PERF_SEL_TCC_REQ = 0x6e, 4651 TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f, 4652 TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70, 4653 TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71, 4654 TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72, 4655 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73, 4656 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74, 4657 TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75, 4658 TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76, 4659 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77, 4660 TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78, 4661 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79, 4662 TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a, 4663 TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b, 4664 TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c, 4665 TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d, 4666 TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e, 4667 TCP_PERF_SEL_TOTAL_READ = 0x7f, 4668 TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80, 4669 TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81, 4670 TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82, 4671 TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83, 4672 TCP_PERF_SEL_TOTAL_NON_READ = 0x84, 4673 TCP_PERF_SEL_TOTAL_WRITE = 0x85, 4674 TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86, 4675 TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87, 4676 TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88, 4677 TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89, 4678 TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a, 4679 TCP_PERF_SEL_THIN_MICROTILING = 0x8b, 4680 TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c, 4681 TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d, 4682 TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e, 4683 TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f, 4684 TCP_PERF_SEL_ARR_PRT_THICK = 0x90, 4685 TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91, 4686 TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92, 4687 TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93, 4688 TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94, 4689 TCP_PERF_SEL_UNALIGNED = 0x95, 4690 TCP_PERF_SEL_ROTATED_MICROTILING = 0x96, 4691 TCP_PERF_SEL_THICK_MICROTILING = 0x97, 4692 TCP_PERF_SEL_ATC = 0x98, 4693 TCP_PERF_SEL_POWER_STALL = 0x99, 4694 } TCP_PERFCOUNT_SELECT; 4695 typedef enum TCP_CACHE_POLICIES { 4696 TCP_CACHE_POLICY_MISS_LRU = 0x0, 4697 TCP_CACHE_POLICY_MISS_EVICT = 0x1, 4698 TCP_CACHE_POLICY_HIT_LRU = 0x2, 4699 TCP_CACHE_POLICY_HIT_EVICT = 0x3, 4700 } TCP_CACHE_POLICIES; 4701 typedef enum TCP_CACHE_STORE_POLICIES { 4702 TCP_CACHE_STORE_POLICY_MISS_LRU = 0x0, 4703 TCP_CACHE_STORE_POLICY_MISS_EVICT = 0x1, 4704 } TCP_CACHE_STORE_POLICIES; 4705 typedef enum TCP_WATCH_MODES { 4706 TCP_WATCH_MODE_READ = 0x0, 4707 TCP_WATCH_MODE_NONREAD = 0x1, 4708 TCP_WATCH_MODE_ATOMIC = 0x2, 4709 TCP_WATCH_MODE_ALL = 0x3, 4710 } TCP_WATCH_MODES; 4711 typedef enum VGT_OUT_PRIM_TYPE { 4712 VGT_OUT_POINT = 0x0, 4713 VGT_OUT_LINE = 0x1, 4714 VGT_OUT_TRI = 0x2, 4715 VGT_OUT_RECT_V0 = 0x3, 4716 VGT_OUT_RECT_V1 = 0x4, 4717 VGT_OUT_RECT_V2 = 0x5, 4718 VGT_OUT_RECT_V3 = 0x6, 4719 VGT_OUT_RESERVED = 0x7, 4720 VGT_TE_QUAD = 0x8, 4721 VGT_TE_PRIM_INDEX_LINE = 0x9, 4722 VGT_TE_PRIM_INDEX_TRI = 0xa, 4723 VGT_TE_PRIM_INDEX_QUAD = 0xb, 4724 VGT_OUT_LINE_ADJ = 0xc, 4725 VGT_OUT_TRI_ADJ = 0xd, 4726 VGT_OUT_PATCH = 0xe, 4727 } VGT_OUT_PRIM_TYPE; 4728 typedef enum VGT_DI_PRIM_TYPE { 4729 DI_PT_NONE = 0x0, 4730 DI_PT_POINTLIST = 0x1, 4731 DI_PT_LINELIST = 0x2, 4732 DI_PT_LINESTRIP = 0x3, 4733 DI_PT_TRILIST = 0x4, 4734 DI_PT_TRIFAN = 0x5, 4735 DI_PT_TRISTRIP = 0x6, 4736 DI_PT_UNUSED_0 = 0x7, 4737 DI_PT_UNUSED_1 = 0x8, 4738 DI_PT_PATCH = 0x9, 4739 DI_PT_LINELIST_ADJ = 0xa, 4740 DI_PT_LINESTRIP_ADJ = 0xb, 4741 DI_PT_TRILIST_ADJ = 0xc, 4742 DI_PT_TRISTRIP_ADJ = 0xd, 4743 DI_PT_UNUSED_3 = 0xe, 4744 DI_PT_UNUSED_4 = 0xf, 4745 DI_PT_TRI_WITH_WFLAGS = 0x10, 4746 DI_PT_RECTLIST = 0x11, 4747 DI_PT_LINELOOP = 0x12, 4748 DI_PT_QUADLIST = 0x13, 4749 DI_PT_QUADSTRIP = 0x14, 4750 DI_PT_POLYGON = 0x15, 4751 DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, 4752 DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, 4753 DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, 4754 DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, 4755 DI_PT_2D_FILL_RECT_LIST = 0x1a, 4756 DI_PT_2D_LINE_STRIP = 0x1b, 4757 DI_PT_2D_TRI_STRIP = 0x1c, 4758 } VGT_DI_PRIM_TYPE; 4759 typedef enum VGT_DI_SOURCE_SELECT { 4760 DI_SRC_SEL_DMA = 0x0, 4761 DI_SRC_SEL_IMMEDIATE = 0x1, 4762 DI_SRC_SEL_AUTO_INDEX = 0x2, 4763 DI_SRC_SEL_RESERVED = 0x3, 4764 } VGT_DI_SOURCE_SELECT; 4765 typedef enum VGT_DI_MAJOR_MODE_SELECT { 4766 DI_MAJOR_MODE_0 = 0x0, 4767 DI_MAJOR_MODE_1 = 0x1, 4768 } VGT_DI_MAJOR_MODE_SELECT; 4769 typedef enum VGT_DI_INDEX_SIZE { 4770 DI_INDEX_SIZE_16_BIT = 0x0, 4771 DI_INDEX_SIZE_32_BIT = 0x1, 4772 } VGT_DI_INDEX_SIZE; 4773 typedef enum VGT_EVENT_TYPE { 4774 Reserved_0x00 = 0x0, 4775 SAMPLE_STREAMOUTSTATS1 = 0x1, 4776 SAMPLE_STREAMOUTSTATS2 = 0x2, 4777 SAMPLE_STREAMOUTSTATS3 = 0x3, 4778 CACHE_FLUSH_TS = 0x4, 4779 CONTEXT_DONE = 0x5, 4780 CACHE_FLUSH = 0x6, 4781 CS_PARTIAL_FLUSH = 0x7, 4782 VGT_STREAMOUT_SYNC = 0x8, 4783 Reserved_0x09 = 0x9, 4784 VGT_STREAMOUT_RESET = 0xa, 4785 END_OF_PIPE_INCR_DE = 0xb, 4786 END_OF_PIPE_IB_END = 0xc, 4787 RST_PIX_CNT = 0xd, 4788 Reserved_0x0E = 0xe, 4789 VS_PARTIAL_FLUSH = 0xf, 4790 PS_PARTIAL_FLUSH = 0x10, 4791 FLUSH_HS_OUTPUT = 0x11, 4792 FLUSH_LS_OUTPUT = 0x12, 4793 Reserved_0x13 = 0x13, 4794 CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, 4795 ZPASS_DONE = 0x15, 4796 CACHE_FLUSH_AND_INV_EVENT = 0x16, 4797 PERFCOUNTER_START = 0x17, 4798 PERFCOUNTER_STOP = 0x18, 4799 PIPELINESTAT_START = 0x19, 4800 PIPELINESTAT_STOP = 0x1a, 4801 PERFCOUNTER_SAMPLE = 0x1b, 4802 FLUSH_ES_OUTPUT = 0x1c, 4803 FLUSH_GS_OUTPUT = 0x1d, 4804 SAMPLE_PIPELINESTAT = 0x1e, 4805 SO_VGTSTREAMOUT_FLUSH = 0x1f, 4806 SAMPLE_STREAMOUTSTATS = 0x20, 4807 RESET_VTX_CNT = 0x21, 4808 BLOCK_CONTEXT_DONE = 0x22, 4809 CS_CONTEXT_DONE = 0x23, 4810 VGT_FLUSH = 0x24, 4811 Reserved_0x25 = 0x25, 4812 SQ_NON_EVENT = 0x26, 4813 SC_SEND_DB_VPZ = 0x27, 4814 BOTTOM_OF_PIPE_TS = 0x28, 4815 FLUSH_SX_TS = 0x29, 4816 DB_CACHE_FLUSH_AND_INV = 0x2a, 4817 FLUSH_AND_INV_DB_DATA_TS = 0x2b, 4818 FLUSH_AND_INV_DB_META = 0x2c, 4819 FLUSH_AND_INV_CB_DATA_TS = 0x2d, 4820 FLUSH_AND_INV_CB_META = 0x2e, 4821 CS_DONE = 0x2f, 4822 PS_DONE = 0x30, 4823 FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, 4824 SX_CB_RAT_ACK_REQUEST = 0x32, 4825 THREAD_TRACE_START = 0x33, 4826 THREAD_TRACE_STOP = 0x34, 4827 THREAD_TRACE_MARKER = 0x35, 4828 THREAD_TRACE_FLUSH = 0x36, 4829 THREAD_TRACE_FINISH = 0x37, 4830 PIXEL_PIPE_STAT_CONTROL = 0x38, 4831 PIXEL_PIPE_STAT_DUMP = 0x39, 4832 PIXEL_PIPE_STAT_RESET = 0x3a, 4833 CONTEXT_SUSPEND = 0x3b, 4834 } VGT_EVENT_TYPE; 4835 typedef enum VGT_DMA_SWAP_MODE { 4836 VGT_DMA_SWAP_NONE = 0x0, 4837 VGT_DMA_SWAP_16_BIT = 0x1, 4838 VGT_DMA_SWAP_32_BIT = 0x2, 4839 VGT_DMA_SWAP_WORD = 0x3, 4840 } VGT_DMA_SWAP_MODE; 4841 typedef enum VGT_INDEX_TYPE_MODE { 4842 VGT_INDEX_16 = 0x0, 4843 VGT_INDEX_32 = 0x1, 4844 } VGT_INDEX_TYPE_MODE; 4845 typedef enum VGT_DMA_BUF_TYPE { 4846 VGT_DMA_BUF_MEM = 0x0, 4847 VGT_DMA_BUF_RING = 0x1, 4848 VGT_DMA_BUF_SETUP = 0x2, 4849 } VGT_DMA_BUF_TYPE; 4850 typedef enum VGT_OUTPATH_SELECT { 4851 VGT_OUTPATH_VTX_REUSE = 0x0, 4852 VGT_OUTPATH_TESS_EN = 0x1, 4853 VGT_OUTPATH_PASSTHRU = 0x2, 4854 VGT_OUTPATH_GS_BLOCK = 0x3, 4855 VGT_OUTPATH_HS_BLOCK = 0x4, 4856 } VGT_OUTPATH_SELECT; 4857 typedef enum VGT_GRP_PRIM_TYPE { 4858 VGT_GRP_3D_POINT = 0x0, 4859 VGT_GRP_3D_LINE = 0x1, 4860 VGT_GRP_3D_TRI = 0x2, 4861 VGT_GRP_3D_RECT = 0x3, 4862 VGT_GRP_3D_QUAD = 0x4, 4863 VGT_GRP_2D_COPY_RECT_V0 = 0x5, 4864 VGT_GRP_2D_COPY_RECT_V1 = 0x6, 4865 VGT_GRP_2D_COPY_RECT_V2 = 0x7, 4866 VGT_GRP_2D_COPY_RECT_V3 = 0x8, 4867 VGT_GRP_2D_FILL_RECT = 0x9, 4868 VGT_GRP_2D_LINE = 0xa, 4869 VGT_GRP_2D_TRI = 0xb, 4870 VGT_GRP_PRIM_INDEX_LINE = 0xc, 4871 VGT_GRP_PRIM_INDEX_TRI = 0xd, 4872 VGT_GRP_PRIM_INDEX_QUAD = 0xe, 4873 VGT_GRP_3D_LINE_ADJ = 0xf, 4874 VGT_GRP_3D_TRI_ADJ = 0x10, 4875 VGT_GRP_3D_PATCH = 0x11, 4876 } VGT_GRP_PRIM_TYPE; 4877 typedef enum VGT_GRP_PRIM_ORDER { 4878 VGT_GRP_LIST = 0x0, 4879 VGT_GRP_STRIP = 0x1, 4880 VGT_GRP_FAN = 0x2, 4881 VGT_GRP_LOOP = 0x3, 4882 VGT_GRP_POLYGON = 0x4, 4883 } VGT_GRP_PRIM_ORDER; 4884 typedef enum VGT_GROUP_CONV_SEL { 4885 VGT_GRP_INDEX_16 = 0x0, 4886 VGT_GRP_INDEX_32 = 0x1, 4887 VGT_GRP_UINT_16 = 0x2, 4888 VGT_GRP_UINT_32 = 0x3, 4889 VGT_GRP_SINT_16 = 0x4, 4890 VGT_GRP_SINT_32 = 0x5, 4891 VGT_GRP_FLOAT_32 = 0x6, 4892 VGT_GRP_AUTO_PRIM = 0x7, 4893 VGT_GRP_FIX_1_23_TO_FLOAT = 0x8, 4894 } VGT_GROUP_CONV_SEL; 4895 typedef enum VGT_GS_MODE_TYPE { 4896 GS_OFF = 0x0, 4897 GS_SCENARIO_A = 0x1, 4898 GS_SCENARIO_B = 0x2, 4899 GS_SCENARIO_G = 0x3, 4900 GS_SCENARIO_C = 0x4, 4901 SPRITE_EN = 0x5, 4902 } VGT_GS_MODE_TYPE; 4903 typedef enum VGT_GS_CUT_MODE { 4904 GS_CUT_1024 = 0x0, 4905 GS_CUT_512 = 0x1, 4906 GS_CUT_256 = 0x2, 4907 GS_CUT_128 = 0x3, 4908 } VGT_GS_CUT_MODE; 4909 typedef enum VGT_GS_OUTPRIM_TYPE { 4910 POINTLIST = 0x0, 4911 LINESTRIP = 0x1, 4912 TRISTRIP = 0x2, 4913 } VGT_GS_OUTPRIM_TYPE; 4914 typedef enum VGT_CACHE_INVALID_MODE { 4915 VC_ONLY = 0x0, 4916 TC_ONLY = 0x1, 4917 VC_AND_TC = 0x2, 4918 } VGT_CACHE_INVALID_MODE; 4919 typedef enum VGT_TESS_TYPE { 4920 TESS_ISOLINE = 0x0, 4921 TESS_TRIANGLE = 0x1, 4922 TESS_QUAD = 0x2, 4923 } VGT_TESS_TYPE; 4924 typedef enum VGT_TESS_PARTITION { 4925 PART_INTEGER = 0x0, 4926 PART_POW2 = 0x1, 4927 PART_FRAC_ODD = 0x2, 4928 PART_FRAC_EVEN = 0x3, 4929 } VGT_TESS_PARTITION; 4930 typedef enum VGT_TESS_TOPOLOGY { 4931 OUTPUT_POINT = 0x0, 4932 OUTPUT_LINE = 0x1, 4933 OUTPUT_TRIANGLE_CW = 0x2, 4934 OUTPUT_TRIANGLE_CCW = 0x3, 4935 } VGT_TESS_TOPOLOGY; 4936 typedef enum VGT_RDREQ_POLICY { 4937 VGT_POLICY_LRU = 0x0, 4938 VGT_POLICY_STREAM = 0x1, 4939 VGT_POLICY_BYPASS = 0x2, 4940 VGT_POLICY_RESERVED = 0x3, 4941 } VGT_RDREQ_POLICY; 4942 typedef enum VGT_STAGES_LS_EN { 4943 LS_STAGE_OFF = 0x0, 4944 LS_STAGE_ON = 0x1, 4945 CS_STAGE_ON = 0x2, 4946 RESERVED_LS = 0x3, 4947 } VGT_STAGES_LS_EN; 4948 typedef enum VGT_STAGES_HS_EN { 4949 HS_STAGE_OFF = 0x0, 4950 HS_STAGE_ON = 0x1, 4951 } VGT_STAGES_HS_EN; 4952 typedef enum VGT_STAGES_ES_EN { 4953 ES_STAGE_OFF = 0x0, 4954 ES_STAGE_DS = 0x1, 4955 ES_STAGE_REAL = 0x2, 4956 RESERVED_ES = 0x3, 4957 } VGT_STAGES_ES_EN; 4958 typedef enum VGT_STAGES_GS_EN { 4959 GS_STAGE_OFF = 0x0, 4960 GS_STAGE_ON = 0x1, 4961 } VGT_STAGES_GS_EN; 4962 typedef enum VGT_STAGES_VS_EN { 4963 VS_STAGE_REAL = 0x0, 4964 VS_STAGE_DS = 0x1, 4965 VS_STAGE_COPY_SHADER = 0x2, 4966 RESERVED_VS = 0x3, 4967 } VGT_STAGES_VS_EN; 4968 typedef enum VGT_PERFCOUNT_SELECT { 4969 vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0, 4970 vgt_perf_VGT_SPI_ESVERT_VALID = 0x1, 4971 vgt_perf_VGT_SPI_ESVERT_EOV = 0x2, 4972 vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3, 4973 vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4, 4974 vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5, 4975 vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6, 4976 vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7, 4977 vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8, 4978 vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9, 4979 vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa, 4980 vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb, 4981 vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc, 4982 vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd, 4983 vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe, 4984 vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf, 4985 vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10, 4986 vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11, 4987 vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12, 4988 vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13, 4989 vgt_perf_VGT_SPI_VSVERT_SEND = 0x14, 4990 vgt_perf_VGT_SPI_VSVERT_EOV = 0x15, 4991 vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16, 4992 vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17, 4993 vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18, 4994 vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19, 4995 vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a, 4996 vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b, 4997 vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c, 4998 vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, 4999 vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e, 5000 vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f, 5001 vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20, 5002 vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21, 5003 vgt_perf_VGT_PA_CLIPV_STATIC = 0x22, 5004 vgt_perf_VGT_PA_CLIPP_SEND = 0x23, 5005 vgt_perf_VGT_PA_CLIPP_EOP = 0x24, 5006 vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25, 5007 vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26, 5008 vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27, 5009 vgt_perf_VGT_PA_CLIPP_STALLED = 0x28, 5010 vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29, 5011 vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a, 5012 vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b, 5013 vgt_perf_VGT_PA_CLIPS_SEND = 0x2c, 5014 vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d, 5015 vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e, 5016 vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f, 5017 vgt_perf_VGT_PA_CLIPS_STATIC = 0x30, 5018 vgt_perf_vsvert_ds_send = 0x31, 5019 vgt_perf_vsvert_api_send = 0x32, 5020 vgt_perf_hs_tif_stall = 0x33, 5021 vgt_perf_hs_input_stall = 0x34, 5022 vgt_perf_hs_interface_stall = 0x35, 5023 vgt_perf_hs_tfm_stall = 0x36, 5024 vgt_perf_te11_starved = 0x37, 5025 vgt_perf_gs_event_stall = 0x38, 5026 vgt_perf_vgt_pa_clipp_send_not_event = 0x39, 5027 vgt_perf_vgt_pa_clipp_valid_prim = 0x3a, 5028 vgt_perf_reused_es_indices = 0x3b, 5029 vgt_perf_vs_cache_hits = 0x3c, 5030 vgt_perf_gs_cache_hits = 0x3d, 5031 vgt_perf_ds_cache_hits = 0x3e, 5032 vgt_perf_total_cache_hits = 0x3f, 5033 vgt_perf_vgt_busy = 0x40, 5034 vgt_perf_vgt_gs_busy = 0x41, 5035 vgt_perf_esvert_stalled_es_tbl = 0x42, 5036 vgt_perf_esvert_stalled_gs_tbl = 0x43, 5037 vgt_perf_esvert_stalled_gs_event = 0x44, 5038 vgt_perf_esvert_stalled_gsprim = 0x45, 5039 vgt_perf_gsprim_stalled_es_tbl = 0x46, 5040 vgt_perf_gsprim_stalled_gs_tbl = 0x47, 5041 vgt_perf_gsprim_stalled_gs_event = 0x48, 5042 vgt_perf_gsprim_stalled_esvert = 0x49, 5043 vgt_perf_esthread_stalled_es_rb_full = 0x4a, 5044 vgt_perf_esthread_stalled_spi_bp = 0x4b, 5045 vgt_perf_counters_avail_stalled = 0x4c, 5046 vgt_perf_gs_rb_space_avail_stalled = 0x4d, 5047 vgt_perf_gs_issue_rtr_stalled = 0x4e, 5048 vgt_perf_gsthread_stalled = 0x4f, 5049 vgt_perf_strmout_stalled = 0x50, 5050 vgt_perf_wait_for_es_done_stalled = 0x51, 5051 vgt_perf_cm_stalled_by_gog = 0x52, 5052 vgt_perf_cm_reading_stalled = 0x53, 5053 vgt_perf_cm_stalled_by_gsfetch_done = 0x54, 5054 vgt_perf_gog_vs_tbl_stalled = 0x55, 5055 vgt_perf_gog_out_indx_stalled = 0x56, 5056 vgt_perf_gog_out_prim_stalled = 0x57, 5057 vgt_perf_waveid_stalled = 0x58, 5058 vgt_perf_gog_busy = 0x59, 5059 vgt_perf_reused_vs_indices = 0x5a, 5060 vgt_perf_sclk_reg_vld_event = 0x5b, 5061 vgt_perf_RESERVED0 = 0x5c, 5062 vgt_perf_sclk_core_vld_event = 0x5d, 5063 vgt_perf_RESERVED1 = 0x5e, 5064 vgt_perf_sclk_gs_vld_event = 0x5f, 5065 vgt_perf_VGT_SPI_LSVERT_VALID = 0x60, 5066 vgt_perf_VGT_SPI_LSVERT_EOV = 0x61, 5067 vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62, 5068 vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63, 5069 vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64, 5070 vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65, 5071 vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66, 5072 vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67, 5073 vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68, 5074 vgt_perf_VGT_SPI_HSVERT_VALID = 0x69, 5075 vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a, 5076 vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b, 5077 vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c, 5078 vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d, 5079 vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e, 5080 vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f, 5081 vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70, 5082 vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71, 5083 vgt_perf_ds_prims = 0x72, 5084 vgt_perf_null_tess_patches = 0x73, 5085 vgt_perf_ls_thread_groups = 0x74, 5086 vgt_perf_hs_thread_groups = 0x75, 5087 vgt_perf_es_thread_groups = 0x76, 5088 vgt_perf_vs_thread_groups = 0x77, 5089 vgt_perf_ls_done_latency = 0x78, 5090 vgt_perf_hs_done_latency = 0x79, 5091 vgt_perf_es_done_latency = 0x7a, 5092 vgt_perf_gs_done_latency = 0x7b, 5093 vgt_perf_vgt_hs_busy = 0x7c, 5094 vgt_perf_vgt_te11_busy = 0x7d, 5095 vgt_perf_ls_flush = 0x7e, 5096 vgt_perf_hs_flush = 0x7f, 5097 vgt_perf_es_flush = 0x80, 5098 vgt_perf_gs_flush = 0x81, 5099 vgt_perf_ls_done = 0x82, 5100 vgt_perf_hs_done = 0x83, 5101 vgt_perf_es_done = 0x84, 5102 vgt_perf_gs_done = 0x85, 5103 vgt_perf_vsfetch_done = 0x86, 5104 vgt_perf_RESERVED2 = 0x87, 5105 vgt_perf_es_ring_high_water_mark = 0x88, 5106 vgt_perf_gs_ring_high_water_mark = 0x89, 5107 vgt_perf_vs_table_high_water_mark = 0x8a, 5108 vgt_perf_hs_tgs_active_high_water_mark = 0x8b, 5109 } VGT_PERFCOUNT_SELECT; 5110 typedef enum IA_PERFCOUNT_SELECT { 5111 ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0, 5112 ia_perf_MC_LAT_BIN_0 = 0x1, 5113 ia_perf_MC_LAT_BIN_1 = 0x2, 5114 ia_perf_MC_LAT_BIN_2 = 0x3, 5115 ia_perf_MC_LAT_BIN_3 = 0x4, 5116 ia_perf_MC_LAT_BIN_4 = 0x5, 5117 ia_perf_MC_LAT_BIN_5 = 0x6, 5118 ia_perf_MC_LAT_BIN_6 = 0x7, 5119 ia_perf_MC_LAT_BIN_7 = 0x8, 5120 ia_perf_ia_busy = 0x9, 5121 ia_perf_ia_sclk_reg_vld_event = 0xa, 5122 ia_perf_RESERVED0 = 0xb, 5123 ia_perf_ia_sclk_core_vld_event = 0xc, 5124 ia_perf_RESERVED1 = 0xd, 5125 ia_perf_ia_dma_return = 0xe, 5126 ia_perf_shift_starved_pipe1_event = 0xf, 5127 ia_perf_shift_starved_pipe0_event = 0x10, 5128 ia_perf_ia_stalled = 0x11, 5129 } IA_PERFCOUNT_SELECT; 5130 typedef enum WD_PERFCOUNT_SELECT { 5131 wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0, 5132 wd_perf_RBIU_DR_FIFO_STARVED = 0x1, 5133 wd_perf_RBIU_DR_FIFO_STALLED = 0x2, 5134 wd_perf_RBIU_DI_FIFO_STARVED = 0x3, 5135 wd_perf_RBIU_DI_FIFO_STALLED = 0x4, 5136 wd_perf_wd_busy = 0x5, 5137 wd_perf_wd_sclk_reg_vld_event = 0x6, 5138 wd_perf_wd_sclk_input_vld_event = 0x7, 5139 wd_perf_wd_sclk_core_vld_event = 0x8, 5140 wd_perf_wd_stalled = 0x9, 5141 } WD_PERFCOUNT_SELECT; 5142 typedef enum WD_IA_DRAW_TYPE { 5143 WD_IA_DRAW_TYPE_DI_MM0 = 0x0, 5144 WD_IA_DRAW_TYPE_DI_MM1 = 0x1, 5145 WD_IA_DRAW_TYPE_EVENT_INIT = 0x2, 5146 WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3, 5147 WD_IA_DRAW_TYPE_MIN_INDX = 0x4, 5148 WD_IA_DRAW_TYPE_MAX_INDX = 0x5, 5149 WD_IA_DRAW_TYPE_INDX_OFF = 0x6, 5150 WD_IA_DRAW_TYPE_IMM_DATA = 0x7, 5151 } WD_IA_DRAW_TYPE; 5152 #define GSTHREADID_SIZE 0x2 5153 typedef enum SurfaceEndian { 5154 ENDIAN_NONE = 0x0, 5155 ENDIAN_8IN16 = 0x1, 5156 ENDIAN_8IN32 = 0x2, 5157 ENDIAN_8IN64 = 0x3, 5158 } SurfaceEndian; 5159 typedef enum ArrayMode { 5160 ARRAY_LINEAR_GENERAL = 0x0, 5161 ARRAY_LINEAR_ALIGNED = 0x1, 5162 ARRAY_1D_TILED_THIN1 = 0x2, 5163 ARRAY_1D_TILED_THICK = 0x3, 5164 ARRAY_2D_TILED_THIN1 = 0x4, 5165 ARRAY_PRT_TILED_THIN1 = 0x5, 5166 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 5167 ARRAY_2D_TILED_THICK = 0x7, 5168 ARRAY_2D_TILED_XTHICK = 0x8, 5169 ARRAY_PRT_TILED_THICK = 0x9, 5170 ARRAY_PRT_2D_TILED_THICK = 0xa, 5171 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 5172 ARRAY_3D_TILED_THIN1 = 0xc, 5173 ARRAY_3D_TILED_THICK = 0xd, 5174 ARRAY_3D_TILED_XTHICK = 0xe, 5175 ARRAY_PRT_3D_TILED_THICK = 0xf, 5176 } ArrayMode; 5177 typedef enum PipeTiling { 5178 CONFIG_1_PIPE = 0x0, 5179 CONFIG_2_PIPE = 0x1, 5180 CONFIG_4_PIPE = 0x2, 5181 CONFIG_8_PIPE = 0x3, 5182 } PipeTiling; 5183 typedef enum BankTiling { 5184 CONFIG_4_BANK = 0x0, 5185 CONFIG_8_BANK = 0x1, 5186 } BankTiling; 5187 typedef enum GroupInterleave { 5188 CONFIG_256B_GROUP = 0x0, 5189 CONFIG_512B_GROUP = 0x1, 5190 } GroupInterleave; 5191 typedef enum RowTiling { 5192 CONFIG_1KB_ROW = 0x0, 5193 CONFIG_2KB_ROW = 0x1, 5194 CONFIG_4KB_ROW = 0x2, 5195 CONFIG_8KB_ROW = 0x3, 5196 CONFIG_1KB_ROW_OPT = 0x4, 5197 CONFIG_2KB_ROW_OPT = 0x5, 5198 CONFIG_4KB_ROW_OPT = 0x6, 5199 CONFIG_8KB_ROW_OPT = 0x7, 5200 } RowTiling; 5201 typedef enum BankSwapBytes { 5202 CONFIG_128B_SWAPS = 0x0, 5203 CONFIG_256B_SWAPS = 0x1, 5204 CONFIG_512B_SWAPS = 0x2, 5205 CONFIG_1KB_SWAPS = 0x3, 5206 } BankSwapBytes; 5207 typedef enum SampleSplitBytes { 5208 CONFIG_1KB_SPLIT = 0x0, 5209 CONFIG_2KB_SPLIT = 0x1, 5210 CONFIG_4KB_SPLIT = 0x2, 5211 CONFIG_8KB_SPLIT = 0x3, 5212 } SampleSplitBytes; 5213 typedef enum NumPipes { 5214 ADDR_CONFIG_1_PIPE = 0x0, 5215 ADDR_CONFIG_2_PIPE = 0x1, 5216 ADDR_CONFIG_4_PIPE = 0x2, 5217 ADDR_CONFIG_8_PIPE = 0x3, 5218 ADDR_CONFIG_16_PIPE = 0x4, 5219 } NumPipes; 5220 typedef enum PipeInterleaveSize { 5221 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 5222 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 5223 } PipeInterleaveSize; 5224 typedef enum BankInterleaveSize { 5225 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 5226 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 5227 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 5228 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 5229 } BankInterleaveSize; 5230 typedef enum NumShaderEngines { 5231 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 5232 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 5233 } NumShaderEngines; 5234 typedef enum ShaderEngineTileSize { 5235 ADDR_CONFIG_SE_TILE_16 = 0x0, 5236 ADDR_CONFIG_SE_TILE_32 = 0x1, 5237 } ShaderEngineTileSize; 5238 typedef enum NumGPUs { 5239 ADDR_CONFIG_1_GPU = 0x0, 5240 ADDR_CONFIG_2_GPU = 0x1, 5241 ADDR_CONFIG_4_GPU = 0x2, 5242 } NumGPUs; 5243 typedef enum MultiGPUTileSize { 5244 ADDR_CONFIG_GPU_TILE_16 = 0x0, 5245 ADDR_CONFIG_GPU_TILE_32 = 0x1, 5246 ADDR_CONFIG_GPU_TILE_64 = 0x2, 5247 ADDR_CONFIG_GPU_TILE_128 = 0x3, 5248 } MultiGPUTileSize; 5249 typedef enum RowSize { 5250 ADDR_CONFIG_1KB_ROW = 0x0, 5251 ADDR_CONFIG_2KB_ROW = 0x1, 5252 ADDR_CONFIG_4KB_ROW = 0x2, 5253 } RowSize; 5254 typedef enum NumLowerPipes { 5255 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 5256 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 5257 } NumLowerPipes; 5258 typedef enum DebugBlockId { 5259 DBG_CLIENT_BLKID_RESERVED = 0x0, 5260 DBG_CLIENT_BLKID_dbg = 0x1, 5261 DBG_CLIENT_BLKID_dco0 = 0x2, 5262 DBG_CLIENT_BLKID_wd = 0x3, 5263 DBG_CLIENT_BLKID_vmc = 0x4, 5264 DBG_CLIENT_BLKID_scf2 = 0x5, 5265 DBG_CLIENT_BLKID_spim3 = 0x6, 5266 DBG_CLIENT_BLKID_cb3 = 0x7, 5267 DBG_CLIENT_BLKID_sx0 = 0x8, 5268 DBG_CLIENT_BLKID_cb2 = 0x9, 5269 DBG_CLIENT_BLKID_bci1 = 0xa, 5270 DBG_CLIENT_BLKID_xdma = 0xb, 5271 DBG_CLIENT_BLKID_bci0 = 0xc, 5272 DBG_CLIENT_BLKID_spim0 = 0xd, 5273 DBG_CLIENT_BLKID_mcd0 = 0xe, 5274 DBG_CLIENT_BLKID_mcc0 = 0xf, 5275 DBG_CLIENT_BLKID_cb0 = 0x10, 5276 DBG_CLIENT_BLKID_cb1 = 0x11, 5277 DBG_CLIENT_BLKID_cpc_0 = 0x12, 5278 DBG_CLIENT_BLKID_cpc_1 = 0x13, 5279 DBG_CLIENT_BLKID_cpf = 0x14, 5280 DBG_CLIENT_BLKID_rlc = 0x15, 5281 DBG_CLIENT_BLKID_grbm = 0x16, 5282 DBG_CLIENT_BLKID_bif = 0x17, 5283 DBG_CLIENT_BLKID_scf1 = 0x18, 5284 DBG_CLIENT_BLKID_sam = 0x19, 5285 DBG_CLIENT_BLKID_mcd4 = 0x1a, 5286 DBG_CLIENT_BLKID_mcc4 = 0x1b, 5287 DBG_CLIENT_BLKID_gmcon = 0x1c, 5288 DBG_CLIENT_BLKID_mcb = 0x1d, 5289 DBG_CLIENT_BLKID_vgt0 = 0x1e, 5290 DBG_CLIENT_BLKID_pc0 = 0x1f, 5291 DBG_CLIENT_BLKID_spim1 = 0x20, 5292 DBG_CLIENT_BLKID_bci2 = 0x21, 5293 DBG_CLIENT_BLKID_mcd6 = 0x22, 5294 DBG_CLIENT_BLKID_mcc6 = 0x23, 5295 DBG_CLIENT_BLKID_mcd3 = 0x24, 5296 DBG_CLIENT_BLKID_mcc3 = 0x25, 5297 DBG_CLIENT_BLKID_uvdm_0 = 0x26, 5298 DBG_CLIENT_BLKID_uvdm_1 = 0x27, 5299 DBG_CLIENT_BLKID_uvdm_2 = 0x28, 5300 DBG_CLIENT_BLKID_uvdm_3 = 0x29, 5301 DBG_CLIENT_BLKID_spim2 = 0x2a, 5302 DBG_CLIENT_BLKID_ds = 0x2b, 5303 DBG_CLIENT_BLKID_srbm = 0x2c, 5304 DBG_CLIENT_BLKID_ih = 0x2d, 5305 DBG_CLIENT_BLKID_sem = 0x2e, 5306 DBG_CLIENT_BLKID_sdma_0 = 0x2f, 5307 DBG_CLIENT_BLKID_sdma_1 = 0x30, 5308 DBG_CLIENT_BLKID_hdp = 0x31, 5309 DBG_CLIENT_BLKID_acp_0 = 0x32, 5310 DBG_CLIENT_BLKID_acp_1 = 0x33, 5311 DBG_CLIENT_BLKID_vceb_0 = 0x34, 5312 DBG_CLIENT_BLKID_vceb_1 = 0x35, 5313 DBG_CLIENT_BLKID_vceb_2 = 0x36, 5314 DBG_CLIENT_BLKID_mcd2 = 0x37, 5315 DBG_CLIENT_BLKID_mcc2 = 0x38, 5316 DBG_CLIENT_BLKID_scf3 = 0x39, 5317 DBG_CLIENT_BLKID_bci3 = 0x3a, 5318 DBG_CLIENT_BLKID_mcd5 = 0x3b, 5319 DBG_CLIENT_BLKID_mcc5 = 0x3c, 5320 DBG_CLIENT_BLKID_vgt2 = 0x3d, 5321 DBG_CLIENT_BLKID_pc2 = 0x3e, 5322 DBG_CLIENT_BLKID_smu_0 = 0x3f, 5323 DBG_CLIENT_BLKID_smu_1 = 0x40, 5324 DBG_CLIENT_BLKID_smu_2 = 0x41, 5325 DBG_CLIENT_BLKID_vcea_0 = 0x42, 5326 DBG_CLIENT_BLKID_vcea_1 = 0x43, 5327 DBG_CLIENT_BLKID_vcea_2 = 0x44, 5328 DBG_CLIENT_BLKID_vcea_3 = 0x45, 5329 DBG_CLIENT_BLKID_vcea_4 = 0x46, 5330 DBG_CLIENT_BLKID_vcea_5 = 0x47, 5331 DBG_CLIENT_BLKID_vcea_6 = 0x48, 5332 DBG_CLIENT_BLKID_scf0 = 0x49, 5333 DBG_CLIENT_BLKID_vgt1 = 0x4a, 5334 DBG_CLIENT_BLKID_pc1 = 0x4b, 5335 DBG_CLIENT_BLKID_gdc_0 = 0x4c, 5336 DBG_CLIENT_BLKID_gdc_1 = 0x4d, 5337 DBG_CLIENT_BLKID_gdc_2 = 0x4e, 5338 DBG_CLIENT_BLKID_gdc_3 = 0x4f, 5339 DBG_CLIENT_BLKID_gdc_4 = 0x50, 5340 DBG_CLIENT_BLKID_gdc_5 = 0x51, 5341 DBG_CLIENT_BLKID_gdc_6 = 0x52, 5342 DBG_CLIENT_BLKID_gdc_7 = 0x53, 5343 DBG_CLIENT_BLKID_gdc_8 = 0x54, 5344 DBG_CLIENT_BLKID_gdc_9 = 0x55, 5345 DBG_CLIENT_BLKID_gdc_10 = 0x56, 5346 DBG_CLIENT_BLKID_gdc_11 = 0x57, 5347 DBG_CLIENT_BLKID_gdc_12 = 0x58, 5348 DBG_CLIENT_BLKID_gdc_13 = 0x59, 5349 DBG_CLIENT_BLKID_gdc_14 = 0x5a, 5350 DBG_CLIENT_BLKID_gdc_15 = 0x5b, 5351 DBG_CLIENT_BLKID_gdc_16 = 0x5c, 5352 DBG_CLIENT_BLKID_gdc_17 = 0x5d, 5353 DBG_CLIENT_BLKID_gdc_18 = 0x5e, 5354 DBG_CLIENT_BLKID_gdc_19 = 0x5f, 5355 DBG_CLIENT_BLKID_gdc_20 = 0x60, 5356 DBG_CLIENT_BLKID_gdc_21 = 0x61, 5357 DBG_CLIENT_BLKID_gdc_22 = 0x62, 5358 DBG_CLIENT_BLKID_vgt3 = 0x63, 5359 DBG_CLIENT_BLKID_pc3 = 0x64, 5360 DBG_CLIENT_BLKID_uvdu_0 = 0x65, 5361 DBG_CLIENT_BLKID_uvdu_1 = 0x66, 5362 DBG_CLIENT_BLKID_uvdu_2 = 0x67, 5363 DBG_CLIENT_BLKID_uvdu_3 = 0x68, 5364 DBG_CLIENT_BLKID_uvdu_4 = 0x69, 5365 DBG_CLIENT_BLKID_uvdu_5 = 0x6a, 5366 DBG_CLIENT_BLKID_uvdu_6 = 0x6b, 5367 DBG_CLIENT_BLKID_mcd7 = 0x6c, 5368 DBG_CLIENT_BLKID_mcc7 = 0x6d, 5369 DBG_CLIENT_BLKID_cpg_0 = 0x6e, 5370 DBG_CLIENT_BLKID_cpg_1 = 0x6f, 5371 DBG_CLIENT_BLKID_gck = 0x70, 5372 DBG_CLIENT_BLKID_mcd1 = 0x71, 5373 DBG_CLIENT_BLKID_mcc1 = 0x72, 5374 DBG_CLIENT_BLKID_cb101 = 0x73, 5375 DBG_CLIENT_BLKID_cb103 = 0x74, 5376 DBG_CLIENT_BLKID_sx10 = 0x75, 5377 DBG_CLIENT_BLKID_cb102 = 0x76, 5378 DBG_CLIENT_BLKID_cb002 = 0x77, 5379 DBG_CLIENT_BLKID_cb100 = 0x78, 5380 DBG_CLIENT_BLKID_cb000 = 0x79, 5381 DBG_CLIENT_BLKID_pa00 = 0x7a, 5382 DBG_CLIENT_BLKID_pa10 = 0x7b, 5383 DBG_CLIENT_BLKID_ia0 = 0x7c, 5384 DBG_CLIENT_BLKID_ia1 = 0x7d, 5385 DBG_CLIENT_BLKID_tmonw00 = 0x7e, 5386 DBG_CLIENT_BLKID_cb001 = 0x7f, 5387 DBG_CLIENT_BLKID_cb003 = 0x80, 5388 DBG_CLIENT_BLKID_sx00 = 0x81, 5389 DBG_CLIENT_BLKID_sx20 = 0x82, 5390 DBG_CLIENT_BLKID_cb203 = 0x83, 5391 DBG_CLIENT_BLKID_cb201 = 0x84, 5392 DBG_CLIENT_BLKID_cb302 = 0x85, 5393 DBG_CLIENT_BLKID_cb202 = 0x86, 5394 DBG_CLIENT_BLKID_cb300 = 0x87, 5395 DBG_CLIENT_BLKID_cb200 = 0x88, 5396 DBG_CLIENT_BLKID_pa01 = 0x89, 5397 DBG_CLIENT_BLKID_pa11 = 0x8a, 5398 DBG_CLIENT_BLKID_sx30 = 0x8b, 5399 DBG_CLIENT_BLKID_cb303 = 0x8c, 5400 DBG_CLIENT_BLKID_cb301 = 0x8d, 5401 DBG_CLIENT_BLKID_dco = 0x8e, 5402 DBG_CLIENT_BLKID_scb0 = 0x8f, 5403 DBG_CLIENT_BLKID_scb1 = 0x90, 5404 DBG_CLIENT_BLKID_scb2 = 0x91, 5405 DBG_CLIENT_BLKID_scb3 = 0x92, 5406 DBG_CLIENT_BLKID_tmonw01 = 0x93, 5407 DBG_CLIENT_BLKID_RESERVED_LAST = 0x94, 5408 } DebugBlockId; 5409 typedef enum DebugBlockId_OLD { 5410 DBG_BLOCK_ID_RESERVED = 0x0, 5411 DBG_BLOCK_ID_DBG = 0x1, 5412 DBG_BLOCK_ID_VMC = 0x2, 5413 DBG_BLOCK_ID_PDMA = 0x3, 5414 DBG_BLOCK_ID_CG = 0x4, 5415 DBG_BLOCK_ID_SRBM = 0x5, 5416 DBG_BLOCK_ID_GRBM = 0x6, 5417 DBG_BLOCK_ID_RLC = 0x7, 5418 DBG_BLOCK_ID_CSC = 0x8, 5419 DBG_BLOCK_ID_SEM = 0x9, 5420 DBG_BLOCK_ID_IH = 0xa, 5421 DBG_BLOCK_ID_SC = 0xb, 5422 DBG_BLOCK_ID_SQ = 0xc, 5423 DBG_BLOCK_ID_AVP = 0xd, 5424 DBG_BLOCK_ID_GMCON = 0xe, 5425 DBG_BLOCK_ID_SMU = 0xf, 5426 DBG_BLOCK_ID_DMA0 = 0x10, 5427 DBG_BLOCK_ID_DMA1 = 0x11, 5428 DBG_BLOCK_ID_SPIM = 0x12, 5429 DBG_BLOCK_ID_GDS = 0x13, 5430 DBG_BLOCK_ID_SPIS = 0x14, 5431 DBG_BLOCK_ID_UNUSED0 = 0x15, 5432 DBG_BLOCK_ID_PA0 = 0x16, 5433 DBG_BLOCK_ID_PA1 = 0x17, 5434 DBG_BLOCK_ID_CP0 = 0x18, 5435 DBG_BLOCK_ID_CP1 = 0x19, 5436 DBG_BLOCK_ID_CP2 = 0x1a, 5437 DBG_BLOCK_ID_UNUSED1 = 0x1b, 5438 DBG_BLOCK_ID_UVDU = 0x1c, 5439 DBG_BLOCK_ID_UVDM = 0x1d, 5440 DBG_BLOCK_ID_VCE = 0x1e, 5441 DBG_BLOCK_ID_UNUSED2 = 0x1f, 5442 DBG_BLOCK_ID_VGT0 = 0x20, 5443 DBG_BLOCK_ID_VGT1 = 0x21, 5444 DBG_BLOCK_ID_IA = 0x22, 5445 DBG_BLOCK_ID_UNUSED3 = 0x23, 5446 DBG_BLOCK_ID_SCT0 = 0x24, 5447 DBG_BLOCK_ID_SCT1 = 0x25, 5448 DBG_BLOCK_ID_SPM0 = 0x26, 5449 DBG_BLOCK_ID_SPM1 = 0x27, 5450 DBG_BLOCK_ID_TCAA = 0x28, 5451 DBG_BLOCK_ID_TCAB = 0x29, 5452 DBG_BLOCK_ID_TCCA = 0x2a, 5453 DBG_BLOCK_ID_TCCB = 0x2b, 5454 DBG_BLOCK_ID_MCC0 = 0x2c, 5455 DBG_BLOCK_ID_MCC1 = 0x2d, 5456 DBG_BLOCK_ID_MCC2 = 0x2e, 5457 DBG_BLOCK_ID_MCC3 = 0x2f, 5458 DBG_BLOCK_ID_SX0 = 0x30, 5459 DBG_BLOCK_ID_SX1 = 0x31, 5460 DBG_BLOCK_ID_SX2 = 0x32, 5461 DBG_BLOCK_ID_SX3 = 0x33, 5462 DBG_BLOCK_ID_UNUSED4 = 0x34, 5463 DBG_BLOCK_ID_UNUSED5 = 0x35, 5464 DBG_BLOCK_ID_UNUSED6 = 0x36, 5465 DBG_BLOCK_ID_UNUSED7 = 0x37, 5466 DBG_BLOCK_ID_PC0 = 0x38, 5467 DBG_BLOCK_ID_PC1 = 0x39, 5468 DBG_BLOCK_ID_UNUSED8 = 0x3a, 5469 DBG_BLOCK_ID_UNUSED9 = 0x3b, 5470 DBG_BLOCK_ID_UNUSED10 = 0x3c, 5471 DBG_BLOCK_ID_UNUSED11 = 0x3d, 5472 DBG_BLOCK_ID_MCB = 0x3e, 5473 DBG_BLOCK_ID_UNUSED12 = 0x3f, 5474 DBG_BLOCK_ID_SCB0 = 0x40, 5475 DBG_BLOCK_ID_SCB1 = 0x41, 5476 DBG_BLOCK_ID_UNUSED13 = 0x42, 5477 DBG_BLOCK_ID_UNUSED14 = 0x43, 5478 DBG_BLOCK_ID_SCF0 = 0x44, 5479 DBG_BLOCK_ID_SCF1 = 0x45, 5480 DBG_BLOCK_ID_UNUSED15 = 0x46, 5481 DBG_BLOCK_ID_UNUSED16 = 0x47, 5482 DBG_BLOCK_ID_BCI0 = 0x48, 5483 DBG_BLOCK_ID_BCI1 = 0x49, 5484 DBG_BLOCK_ID_BCI2 = 0x4a, 5485 DBG_BLOCK_ID_BCI3 = 0x4b, 5486 DBG_BLOCK_ID_UNUSED17 = 0x4c, 5487 DBG_BLOCK_ID_UNUSED18 = 0x4d, 5488 DBG_BLOCK_ID_UNUSED19 = 0x4e, 5489 DBG_BLOCK_ID_UNUSED20 = 0x4f, 5490 DBG_BLOCK_ID_CB00 = 0x50, 5491 DBG_BLOCK_ID_CB01 = 0x51, 5492 DBG_BLOCK_ID_CB02 = 0x52, 5493 DBG_BLOCK_ID_CB03 = 0x53, 5494 DBG_BLOCK_ID_CB04 = 0x54, 5495 DBG_BLOCK_ID_UNUSED21 = 0x55, 5496 DBG_BLOCK_ID_UNUSED22 = 0x56, 5497 DBG_BLOCK_ID_UNUSED23 = 0x57, 5498 DBG_BLOCK_ID_CB10 = 0x58, 5499 DBG_BLOCK_ID_CB11 = 0x59, 5500 DBG_BLOCK_ID_CB12 = 0x5a, 5501 DBG_BLOCK_ID_CB13 = 0x5b, 5502 DBG_BLOCK_ID_CB14 = 0x5c, 5503 DBG_BLOCK_ID_UNUSED24 = 0x5d, 5504 DBG_BLOCK_ID_UNUSED25 = 0x5e, 5505 DBG_BLOCK_ID_UNUSED26 = 0x5f, 5506 DBG_BLOCK_ID_TCP0 = 0x60, 5507 DBG_BLOCK_ID_TCP1 = 0x61, 5508 DBG_BLOCK_ID_TCP2 = 0x62, 5509 DBG_BLOCK_ID_TCP3 = 0x63, 5510 DBG_BLOCK_ID_TCP4 = 0x64, 5511 DBG_BLOCK_ID_TCP5 = 0x65, 5512 DBG_BLOCK_ID_TCP6 = 0x66, 5513 DBG_BLOCK_ID_TCP7 = 0x67, 5514 DBG_BLOCK_ID_TCP8 = 0x68, 5515 DBG_BLOCK_ID_TCP9 = 0x69, 5516 DBG_BLOCK_ID_TCP10 = 0x6a, 5517 DBG_BLOCK_ID_TCP11 = 0x6b, 5518 DBG_BLOCK_ID_TCP12 = 0x6c, 5519 DBG_BLOCK_ID_TCP13 = 0x6d, 5520 DBG_BLOCK_ID_TCP14 = 0x6e, 5521 DBG_BLOCK_ID_TCP15 = 0x6f, 5522 DBG_BLOCK_ID_TCP16 = 0x70, 5523 DBG_BLOCK_ID_TCP17 = 0x71, 5524 DBG_BLOCK_ID_TCP18 = 0x72, 5525 DBG_BLOCK_ID_TCP19 = 0x73, 5526 DBG_BLOCK_ID_TCP20 = 0x74, 5527 DBG_BLOCK_ID_TCP21 = 0x75, 5528 DBG_BLOCK_ID_TCP22 = 0x76, 5529 DBG_BLOCK_ID_TCP23 = 0x77, 5530 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 5531 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 5532 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 5533 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 5534 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 5535 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 5536 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 5537 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 5538 DBG_BLOCK_ID_DB00 = 0x80, 5539 DBG_BLOCK_ID_DB01 = 0x81, 5540 DBG_BLOCK_ID_DB02 = 0x82, 5541 DBG_BLOCK_ID_DB03 = 0x83, 5542 DBG_BLOCK_ID_DB04 = 0x84, 5543 DBG_BLOCK_ID_UNUSED27 = 0x85, 5544 DBG_BLOCK_ID_UNUSED28 = 0x86, 5545 DBG_BLOCK_ID_UNUSED29 = 0x87, 5546 DBG_BLOCK_ID_DB10 = 0x88, 5547 DBG_BLOCK_ID_DB11 = 0x89, 5548 DBG_BLOCK_ID_DB12 = 0x8a, 5549 DBG_BLOCK_ID_DB13 = 0x8b, 5550 DBG_BLOCK_ID_DB14 = 0x8c, 5551 DBG_BLOCK_ID_UNUSED30 = 0x8d, 5552 DBG_BLOCK_ID_UNUSED31 = 0x8e, 5553 DBG_BLOCK_ID_UNUSED32 = 0x8f, 5554 DBG_BLOCK_ID_TCC0 = 0x90, 5555 DBG_BLOCK_ID_TCC1 = 0x91, 5556 DBG_BLOCK_ID_TCC2 = 0x92, 5557 DBG_BLOCK_ID_TCC3 = 0x93, 5558 DBG_BLOCK_ID_TCC4 = 0x94, 5559 DBG_BLOCK_ID_TCC5 = 0x95, 5560 DBG_BLOCK_ID_TCC6 = 0x96, 5561 DBG_BLOCK_ID_TCC7 = 0x97, 5562 DBG_BLOCK_ID_SPS00 = 0x98, 5563 DBG_BLOCK_ID_SPS01 = 0x99, 5564 DBG_BLOCK_ID_SPS02 = 0x9a, 5565 DBG_BLOCK_ID_SPS10 = 0x9b, 5566 DBG_BLOCK_ID_SPS11 = 0x9c, 5567 DBG_BLOCK_ID_SPS12 = 0x9d, 5568 DBG_BLOCK_ID_UNUSED33 = 0x9e, 5569 DBG_BLOCK_ID_UNUSED34 = 0x9f, 5570 DBG_BLOCK_ID_TA00 = 0xa0, 5571 DBG_BLOCK_ID_TA01 = 0xa1, 5572 DBG_BLOCK_ID_TA02 = 0xa2, 5573 DBG_BLOCK_ID_TA03 = 0xa3, 5574 DBG_BLOCK_ID_TA04 = 0xa4, 5575 DBG_BLOCK_ID_TA05 = 0xa5, 5576 DBG_BLOCK_ID_TA06 = 0xa6, 5577 DBG_BLOCK_ID_TA07 = 0xa7, 5578 DBG_BLOCK_ID_TA08 = 0xa8, 5579 DBG_BLOCK_ID_TA09 = 0xa9, 5580 DBG_BLOCK_ID_TA0A = 0xaa, 5581 DBG_BLOCK_ID_TA0B = 0xab, 5582 DBG_BLOCK_ID_UNUSED35 = 0xac, 5583 DBG_BLOCK_ID_UNUSED36 = 0xad, 5584 DBG_BLOCK_ID_UNUSED37 = 0xae, 5585 DBG_BLOCK_ID_UNUSED38 = 0xaf, 5586 DBG_BLOCK_ID_TA10 = 0xb0, 5587 DBG_BLOCK_ID_TA11 = 0xb1, 5588 DBG_BLOCK_ID_TA12 = 0xb2, 5589 DBG_BLOCK_ID_TA13 = 0xb3, 5590 DBG_BLOCK_ID_TA14 = 0xb4, 5591 DBG_BLOCK_ID_TA15 = 0xb5, 5592 DBG_BLOCK_ID_TA16 = 0xb6, 5593 DBG_BLOCK_ID_TA17 = 0xb7, 5594 DBG_BLOCK_ID_TA18 = 0xb8, 5595 DBG_BLOCK_ID_TA19 = 0xb9, 5596 DBG_BLOCK_ID_TA1A = 0xba, 5597 DBG_BLOCK_ID_TA1B = 0xbb, 5598 DBG_BLOCK_ID_UNUSED39 = 0xbc, 5599 DBG_BLOCK_ID_UNUSED40 = 0xbd, 5600 DBG_BLOCK_ID_UNUSED41 = 0xbe, 5601 DBG_BLOCK_ID_UNUSED42 = 0xbf, 5602 DBG_BLOCK_ID_TD00 = 0xc0, 5603 DBG_BLOCK_ID_TD01 = 0xc1, 5604 DBG_BLOCK_ID_TD02 = 0xc2, 5605 DBG_BLOCK_ID_TD03 = 0xc3, 5606 DBG_BLOCK_ID_TD04 = 0xc4, 5607 DBG_BLOCK_ID_TD05 = 0xc5, 5608 DBG_BLOCK_ID_TD06 = 0xc6, 5609 DBG_BLOCK_ID_TD07 = 0xc7, 5610 DBG_BLOCK_ID_TD08 = 0xc8, 5611 DBG_BLOCK_ID_TD09 = 0xc9, 5612 DBG_BLOCK_ID_TD0A = 0xca, 5613 DBG_BLOCK_ID_TD0B = 0xcb, 5614 DBG_BLOCK_ID_UNUSED43 = 0xcc, 5615 DBG_BLOCK_ID_UNUSED44 = 0xcd, 5616 DBG_BLOCK_ID_UNUSED45 = 0xce, 5617 DBG_BLOCK_ID_UNUSED46 = 0xcf, 5618 DBG_BLOCK_ID_TD10 = 0xd0, 5619 DBG_BLOCK_ID_TD11 = 0xd1, 5620 DBG_BLOCK_ID_TD12 = 0xd2, 5621 DBG_BLOCK_ID_TD13 = 0xd3, 5622 DBG_BLOCK_ID_TD14 = 0xd4, 5623 DBG_BLOCK_ID_TD15 = 0xd5, 5624 DBG_BLOCK_ID_TD16 = 0xd6, 5625 DBG_BLOCK_ID_TD17 = 0xd7, 5626 DBG_BLOCK_ID_TD18 = 0xd8, 5627 DBG_BLOCK_ID_TD19 = 0xd9, 5628 DBG_BLOCK_ID_TD1A = 0xda, 5629 DBG_BLOCK_ID_TD1B = 0xdb, 5630 DBG_BLOCK_ID_UNUSED47 = 0xdc, 5631 DBG_BLOCK_ID_UNUSED48 = 0xdd, 5632 DBG_BLOCK_ID_UNUSED49 = 0xde, 5633 DBG_BLOCK_ID_UNUSED50 = 0xdf, 5634 DBG_BLOCK_ID_MCD0 = 0xe0, 5635 DBG_BLOCK_ID_MCD1 = 0xe1, 5636 DBG_BLOCK_ID_MCD2 = 0xe2, 5637 DBG_BLOCK_ID_MCD3 = 0xe3, 5638 DBG_BLOCK_ID_MCD4 = 0xe4, 5639 DBG_BLOCK_ID_MCD5 = 0xe5, 5640 DBG_BLOCK_ID_UNUSED51 = 0xe6, 5641 DBG_BLOCK_ID_UNUSED52 = 0xe7, 5642 } DebugBlockId_OLD; 5643 typedef enum DebugBlockId_BY2 { 5644 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 5645 DBG_BLOCK_ID_VMC_BY2 = 0x1, 5646 DBG_BLOCK_ID_CG_BY2 = 0x2, 5647 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 5648 DBG_BLOCK_ID_CSC_BY2 = 0x4, 5649 DBG_BLOCK_ID_IH_BY2 = 0x5, 5650 DBG_BLOCK_ID_SQ_BY2 = 0x6, 5651 DBG_BLOCK_ID_GMCON_BY2 = 0x7, 5652 DBG_BLOCK_ID_DMA0_BY2 = 0x8, 5653 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 5654 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 5655 DBG_BLOCK_ID_PA0_BY2 = 0xb, 5656 DBG_BLOCK_ID_CP0_BY2 = 0xc, 5657 DBG_BLOCK_ID_CP2_BY2 = 0xd, 5658 DBG_BLOCK_ID_UVDU_BY2 = 0xe, 5659 DBG_BLOCK_ID_VCE_BY2 = 0xf, 5660 DBG_BLOCK_ID_VGT0_BY2 = 0x10, 5661 DBG_BLOCK_ID_IA_BY2 = 0x11, 5662 DBG_BLOCK_ID_SCT0_BY2 = 0x12, 5663 DBG_BLOCK_ID_SPM0_BY2 = 0x13, 5664 DBG_BLOCK_ID_TCAA_BY2 = 0x14, 5665 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 5666 DBG_BLOCK_ID_MCC0_BY2 = 0x16, 5667 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 5668 DBG_BLOCK_ID_SX0_BY2 = 0x18, 5669 DBG_BLOCK_ID_SX2_BY2 = 0x19, 5670 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 5671 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 5672 DBG_BLOCK_ID_PC0_BY2 = 0x1c, 5673 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 5674 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 5675 DBG_BLOCK_ID_MCB_BY2 = 0x1f, 5676 DBG_BLOCK_ID_SCB0_BY2 = 0x20, 5677 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 5678 DBG_BLOCK_ID_SCF0_BY2 = 0x22, 5679 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 5680 DBG_BLOCK_ID_BCI0_BY2 = 0x24, 5681 DBG_BLOCK_ID_BCI2_BY2 = 0x25, 5682 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 5683 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 5684 DBG_BLOCK_ID_CB00_BY2 = 0x28, 5685 DBG_BLOCK_ID_CB02_BY2 = 0x29, 5686 DBG_BLOCK_ID_CB04_BY2 = 0x2a, 5687 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 5688 DBG_BLOCK_ID_CB10_BY2 = 0x2c, 5689 DBG_BLOCK_ID_CB12_BY2 = 0x2d, 5690 DBG_BLOCK_ID_CB14_BY2 = 0x2e, 5691 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 5692 DBG_BLOCK_ID_TCP0_BY2 = 0x30, 5693 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 5694 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 5695 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 5696 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 5697 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 5698 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 5699 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 5700 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 5701 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 5702 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 5703 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 5704 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 5705 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 5706 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 5707 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 5708 DBG_BLOCK_ID_DB00_BY2 = 0x40, 5709 DBG_BLOCK_ID_DB02_BY2 = 0x41, 5710 DBG_BLOCK_ID_DB04_BY2 = 0x42, 5711 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 5712 DBG_BLOCK_ID_DB10_BY2 = 0x44, 5713 DBG_BLOCK_ID_DB12_BY2 = 0x45, 5714 DBG_BLOCK_ID_DB14_BY2 = 0x46, 5715 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 5716 DBG_BLOCK_ID_TCC0_BY2 = 0x48, 5717 DBG_BLOCK_ID_TCC2_BY2 = 0x49, 5718 DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 5719 DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 5720 DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 5721 DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 5722 DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 5723 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 5724 DBG_BLOCK_ID_TA00_BY2 = 0x50, 5725 DBG_BLOCK_ID_TA02_BY2 = 0x51, 5726 DBG_BLOCK_ID_TA04_BY2 = 0x52, 5727 DBG_BLOCK_ID_TA06_BY2 = 0x53, 5728 DBG_BLOCK_ID_TA08_BY2 = 0x54, 5729 DBG_BLOCK_ID_TA0A_BY2 = 0x55, 5730 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 5731 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 5732 DBG_BLOCK_ID_TA10_BY2 = 0x58, 5733 DBG_BLOCK_ID_TA12_BY2 = 0x59, 5734 DBG_BLOCK_ID_TA14_BY2 = 0x5a, 5735 DBG_BLOCK_ID_TA16_BY2 = 0x5b, 5736 DBG_BLOCK_ID_TA18_BY2 = 0x5c, 5737 DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 5738 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 5739 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 5740 DBG_BLOCK_ID_TD00_BY2 = 0x60, 5741 DBG_BLOCK_ID_TD02_BY2 = 0x61, 5742 DBG_BLOCK_ID_TD04_BY2 = 0x62, 5743 DBG_BLOCK_ID_TD06_BY2 = 0x63, 5744 DBG_BLOCK_ID_TD08_BY2 = 0x64, 5745 DBG_BLOCK_ID_TD0A_BY2 = 0x65, 5746 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 5747 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 5748 DBG_BLOCK_ID_TD10_BY2 = 0x68, 5749 DBG_BLOCK_ID_TD12_BY2 = 0x69, 5750 DBG_BLOCK_ID_TD14_BY2 = 0x6a, 5751 DBG_BLOCK_ID_TD16_BY2 = 0x6b, 5752 DBG_BLOCK_ID_TD18_BY2 = 0x6c, 5753 DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 5754 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 5755 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 5756 DBG_BLOCK_ID_MCD0_BY2 = 0x70, 5757 DBG_BLOCK_ID_MCD2_BY2 = 0x71, 5758 DBG_BLOCK_ID_MCD4_BY2 = 0x72, 5759 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 5760 } DebugBlockId_BY2; 5761 typedef enum DebugBlockId_BY4 { 5762 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 5763 DBG_BLOCK_ID_CG_BY4 = 0x1, 5764 DBG_BLOCK_ID_CSC_BY4 = 0x2, 5765 DBG_BLOCK_ID_SQ_BY4 = 0x3, 5766 DBG_BLOCK_ID_DMA0_BY4 = 0x4, 5767 DBG_BLOCK_ID_SPIS_BY4 = 0x5, 5768 DBG_BLOCK_ID_CP0_BY4 = 0x6, 5769 DBG_BLOCK_ID_UVDU_BY4 = 0x7, 5770 DBG_BLOCK_ID_VGT0_BY4 = 0x8, 5771 DBG_BLOCK_ID_SCT0_BY4 = 0x9, 5772 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 5773 DBG_BLOCK_ID_MCC0_BY4 = 0xb, 5774 DBG_BLOCK_ID_SX0_BY4 = 0xc, 5775 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 5776 DBG_BLOCK_ID_PC0_BY4 = 0xe, 5777 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 5778 DBG_BLOCK_ID_SCB0_BY4 = 0x10, 5779 DBG_BLOCK_ID_SCF0_BY4 = 0x11, 5780 DBG_BLOCK_ID_BCI0_BY4 = 0x12, 5781 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 5782 DBG_BLOCK_ID_CB00_BY4 = 0x14, 5783 DBG_BLOCK_ID_CB04_BY4 = 0x15, 5784 DBG_BLOCK_ID_CB10_BY4 = 0x16, 5785 DBG_BLOCK_ID_CB14_BY4 = 0x17, 5786 DBG_BLOCK_ID_TCP0_BY4 = 0x18, 5787 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 5788 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 5789 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 5790 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 5791 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 5792 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 5793 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 5794 DBG_BLOCK_ID_DB_BY4 = 0x20, 5795 DBG_BLOCK_ID_DB04_BY4 = 0x21, 5796 DBG_BLOCK_ID_DB10_BY4 = 0x22, 5797 DBG_BLOCK_ID_DB14_BY4 = 0x23, 5798 DBG_BLOCK_ID_TCC0_BY4 = 0x24, 5799 DBG_BLOCK_ID_TCC4_BY4 = 0x25, 5800 DBG_BLOCK_ID_SPS00_BY4 = 0x26, 5801 DBG_BLOCK_ID_SPS11_BY4 = 0x27, 5802 DBG_BLOCK_ID_TA00_BY4 = 0x28, 5803 DBG_BLOCK_ID_TA04_BY4 = 0x29, 5804 DBG_BLOCK_ID_TA08_BY4 = 0x2a, 5805 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 5806 DBG_BLOCK_ID_TA10_BY4 = 0x2c, 5807 DBG_BLOCK_ID_TA14_BY4 = 0x2d, 5808 DBG_BLOCK_ID_TA18_BY4 = 0x2e, 5809 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 5810 DBG_BLOCK_ID_TD00_BY4 = 0x30, 5811 DBG_BLOCK_ID_TD04_BY4 = 0x31, 5812 DBG_BLOCK_ID_TD08_BY4 = 0x32, 5813 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 5814 DBG_BLOCK_ID_TD10_BY4 = 0x34, 5815 DBG_BLOCK_ID_TD14_BY4 = 0x35, 5816 DBG_BLOCK_ID_TD18_BY4 = 0x36, 5817 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 5818 DBG_BLOCK_ID_MCD0_BY4 = 0x38, 5819 DBG_BLOCK_ID_MCD4_BY4 = 0x39, 5820 } DebugBlockId_BY4; 5821 typedef enum DebugBlockId_BY8 { 5822 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 5823 DBG_BLOCK_ID_CSC_BY8 = 0x1, 5824 DBG_BLOCK_ID_DMA0_BY8 = 0x2, 5825 DBG_BLOCK_ID_CP0_BY8 = 0x3, 5826 DBG_BLOCK_ID_VGT0_BY8 = 0x4, 5827 DBG_BLOCK_ID_TCAA_BY8 = 0x5, 5828 DBG_BLOCK_ID_SX0_BY8 = 0x6, 5829 DBG_BLOCK_ID_PC0_BY8 = 0x7, 5830 DBG_BLOCK_ID_SCB0_BY8 = 0x8, 5831 DBG_BLOCK_ID_BCI0_BY8 = 0x9, 5832 DBG_BLOCK_ID_CB00_BY8 = 0xa, 5833 DBG_BLOCK_ID_CB10_BY8 = 0xb, 5834 DBG_BLOCK_ID_TCP0_BY8 = 0xc, 5835 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 5836 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 5837 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 5838 DBG_BLOCK_ID_DB00_BY8 = 0x10, 5839 DBG_BLOCK_ID_DB10_BY8 = 0x11, 5840 DBG_BLOCK_ID_TCC0_BY8 = 0x12, 5841 DBG_BLOCK_ID_SPS00_BY8 = 0x13, 5842 DBG_BLOCK_ID_TA00_BY8 = 0x14, 5843 DBG_BLOCK_ID_TA08_BY8 = 0x15, 5844 DBG_BLOCK_ID_TA10_BY8 = 0x16, 5845 DBG_BLOCK_ID_TA18_BY8 = 0x17, 5846 DBG_BLOCK_ID_TD00_BY8 = 0x18, 5847 DBG_BLOCK_ID_TD08_BY8 = 0x19, 5848 DBG_BLOCK_ID_TD10_BY8 = 0x1a, 5849 DBG_BLOCK_ID_TD18_BY8 = 0x1b, 5850 DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 5851 } DebugBlockId_BY8; 5852 typedef enum DebugBlockId_BY16 { 5853 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 5854 DBG_BLOCK_ID_DMA0_BY16 = 0x1, 5855 DBG_BLOCK_ID_VGT0_BY16 = 0x2, 5856 DBG_BLOCK_ID_SX0_BY16 = 0x3, 5857 DBG_BLOCK_ID_SCB0_BY16 = 0x4, 5858 DBG_BLOCK_ID_CB00_BY16 = 0x5, 5859 DBG_BLOCK_ID_TCP0_BY16 = 0x6, 5860 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 5861 DBG_BLOCK_ID_DB00_BY16 = 0x8, 5862 DBG_BLOCK_ID_TCC0_BY16 = 0x9, 5863 DBG_BLOCK_ID_TA00_BY16 = 0xa, 5864 DBG_BLOCK_ID_TA10_BY16 = 0xb, 5865 DBG_BLOCK_ID_TD00_BY16 = 0xc, 5866 DBG_BLOCK_ID_TD10_BY16 = 0xd, 5867 DBG_BLOCK_ID_MCD0_BY16 = 0xe, 5868 } DebugBlockId_BY16; 5869 typedef enum CompareRef { 5870 REF_NEVER = 0x0, 5871 REF_LESS = 0x1, 5872 REF_EQUAL = 0x2, 5873 REF_LEQUAL = 0x3, 5874 REF_GREATER = 0x4, 5875 REF_NOTEQUAL = 0x5, 5876 REF_GEQUAL = 0x6, 5877 REF_ALWAYS = 0x7, 5878 } CompareRef; 5879 typedef enum ReadSize { 5880 READ_256_BITS = 0x0, 5881 READ_512_BITS = 0x1, 5882 } ReadSize; 5883 typedef enum DepthFormat { 5884 DEPTH_INVALID = 0x0, 5885 DEPTH_16 = 0x1, 5886 DEPTH_X8_24 = 0x2, 5887 DEPTH_8_24 = 0x3, 5888 DEPTH_X8_24_FLOAT = 0x4, 5889 DEPTH_8_24_FLOAT = 0x5, 5890 DEPTH_32_FLOAT = 0x6, 5891 DEPTH_X24_8_32_FLOAT = 0x7, 5892 } DepthFormat; 5893 typedef enum ZFormat { 5894 Z_INVALID = 0x0, 5895 Z_16 = 0x1, 5896 Z_24 = 0x2, 5897 Z_32_FLOAT = 0x3, 5898 } ZFormat; 5899 typedef enum StencilFormat { 5900 STENCIL_INVALID = 0x0, 5901 STENCIL_8 = 0x1, 5902 } StencilFormat; 5903 typedef enum CmaskMode { 5904 CMASK_CLEAR_NONE = 0x0, 5905 CMASK_CLEAR_ONE = 0x1, 5906 CMASK_CLEAR_ALL = 0x2, 5907 CMASK_ANY_EXPANDED = 0x3, 5908 CMASK_ALPHA0_FRAG1 = 0x4, 5909 CMASK_ALPHA0_FRAG2 = 0x5, 5910 CMASK_ALPHA0_FRAG4 = 0x6, 5911 CMASK_ALPHA0_FRAGS = 0x7, 5912 CMASK_ALPHA1_FRAG1 = 0x8, 5913 CMASK_ALPHA1_FRAG2 = 0x9, 5914 CMASK_ALPHA1_FRAG4 = 0xa, 5915 CMASK_ALPHA1_FRAGS = 0xb, 5916 CMASK_ALPHAX_FRAG1 = 0xc, 5917 CMASK_ALPHAX_FRAG2 = 0xd, 5918 CMASK_ALPHAX_FRAG4 = 0xe, 5919 CMASK_ALPHAX_FRAGS = 0xf, 5920 } CmaskMode; 5921 typedef enum QuadExportFormat { 5922 EXPORT_UNUSED = 0x0, 5923 EXPORT_32_R = 0x1, 5924 EXPORT_32_GR = 0x2, 5925 EXPORT_32_AR = 0x3, 5926 EXPORT_FP16_ABGR = 0x4, 5927 EXPORT_UNSIGNED16_ABGR = 0x5, 5928 EXPORT_SIGNED16_ABGR = 0x6, 5929 EXPORT_32_ABGR = 0x7, 5930 } QuadExportFormat; 5931 typedef enum QuadExportFormatOld { 5932 EXPORT_4P_32BPC_ABGR = 0x0, 5933 EXPORT_4P_16BPC_ABGR = 0x1, 5934 EXPORT_4P_32BPC_GR = 0x2, 5935 EXPORT_4P_32BPC_AR = 0x3, 5936 EXPORT_2P_32BPC_ABGR = 0x4, 5937 EXPORT_8P_32BPC_R = 0x5, 5938 } QuadExportFormatOld; 5939 typedef enum ColorFormat { 5940 COLOR_INVALID = 0x0, 5941 COLOR_8 = 0x1, 5942 COLOR_16 = 0x2, 5943 COLOR_8_8 = 0x3, 5944 COLOR_32 = 0x4, 5945 COLOR_16_16 = 0x5, 5946 COLOR_10_11_11 = 0x6, 5947 COLOR_11_11_10 = 0x7, 5948 COLOR_10_10_10_2 = 0x8, 5949 COLOR_2_10_10_10 = 0x9, 5950 COLOR_8_8_8_8 = 0xa, 5951 COLOR_32_32 = 0xb, 5952 COLOR_16_16_16_16 = 0xc, 5953 COLOR_RESERVED_13 = 0xd, 5954 COLOR_32_32_32_32 = 0xe, 5955 COLOR_RESERVED_15 = 0xf, 5956 COLOR_5_6_5 = 0x10, 5957 COLOR_1_5_5_5 = 0x11, 5958 COLOR_5_5_5_1 = 0x12, 5959 COLOR_4_4_4_4 = 0x13, 5960 COLOR_8_24 = 0x14, 5961 COLOR_24_8 = 0x15, 5962 COLOR_X24_8_32_FLOAT = 0x16, 5963 COLOR_RESERVED_23 = 0x17, 5964 } ColorFormat; 5965 typedef enum SurfaceFormat { 5966 FMT_INVALID = 0x0, 5967 FMT_8 = 0x1, 5968 FMT_16 = 0x2, 5969 FMT_8_8 = 0x3, 5970 FMT_32 = 0x4, 5971 FMT_16_16 = 0x5, 5972 FMT_10_11_11 = 0x6, 5973 FMT_11_11_10 = 0x7, 5974 FMT_10_10_10_2 = 0x8, 5975 FMT_2_10_10_10 = 0x9, 5976 FMT_8_8_8_8 = 0xa, 5977 FMT_32_32 = 0xb, 5978 FMT_16_16_16_16 = 0xc, 5979 FMT_32_32_32 = 0xd, 5980 FMT_32_32_32_32 = 0xe, 5981 FMT_RESERVED_4 = 0xf, 5982 FMT_5_6_5 = 0x10, 5983 FMT_1_5_5_5 = 0x11, 5984 FMT_5_5_5_1 = 0x12, 5985 FMT_4_4_4_4 = 0x13, 5986 FMT_8_24 = 0x14, 5987 FMT_24_8 = 0x15, 5988 FMT_X24_8_32_FLOAT = 0x16, 5989 FMT_RESERVED_33 = 0x17, 5990 FMT_11_11_10_FLOAT = 0x18, 5991 FMT_16_FLOAT = 0x19, 5992 FMT_32_FLOAT = 0x1a, 5993 FMT_16_16_FLOAT = 0x1b, 5994 FMT_8_24_FLOAT = 0x1c, 5995 FMT_24_8_FLOAT = 0x1d, 5996 FMT_32_32_FLOAT = 0x1e, 5997 FMT_10_11_11_FLOAT = 0x1f, 5998 FMT_16_16_16_16_FLOAT = 0x20, 5999 FMT_3_3_2 = 0x21, 6000 FMT_6_5_5 = 0x22, 6001 FMT_32_32_32_32_FLOAT = 0x23, 6002 FMT_RESERVED_36 = 0x24, 6003 FMT_1 = 0x25, 6004 FMT_1_REVERSED = 0x26, 6005 FMT_GB_GR = 0x27, 6006 FMT_BG_RG = 0x28, 6007 FMT_32_AS_8 = 0x29, 6008 FMT_32_AS_8_8 = 0x2a, 6009 FMT_5_9_9_9_SHAREDEXP = 0x2b, 6010 FMT_8_8_8 = 0x2c, 6011 FMT_16_16_16 = 0x2d, 6012 FMT_16_16_16_FLOAT = 0x2e, 6013 FMT_4_4 = 0x2f, 6014 FMT_32_32_32_FLOAT = 0x30, 6015 FMT_BC1 = 0x31, 6016 FMT_BC2 = 0x32, 6017 FMT_BC3 = 0x33, 6018 FMT_BC4 = 0x34, 6019 FMT_BC5 = 0x35, 6020 FMT_BC6 = 0x36, 6021 FMT_BC7 = 0x37, 6022 FMT_32_AS_32_32_32_32 = 0x38, 6023 FMT_APC3 = 0x39, 6024 FMT_APC4 = 0x3a, 6025 FMT_APC5 = 0x3b, 6026 FMT_APC6 = 0x3c, 6027 FMT_APC7 = 0x3d, 6028 FMT_CTX1 = 0x3e, 6029 FMT_RESERVED_63 = 0x3f, 6030 } SurfaceFormat; 6031 typedef enum BUF_DATA_FORMAT { 6032 BUF_DATA_FORMAT_INVALID = 0x0, 6033 BUF_DATA_FORMAT_8 = 0x1, 6034 BUF_DATA_FORMAT_16 = 0x2, 6035 BUF_DATA_FORMAT_8_8 = 0x3, 6036 BUF_DATA_FORMAT_32 = 0x4, 6037 BUF_DATA_FORMAT_16_16 = 0x5, 6038 BUF_DATA_FORMAT_10_11_11 = 0x6, 6039 BUF_DATA_FORMAT_11_11_10 = 0x7, 6040 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 6041 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 6042 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 6043 BUF_DATA_FORMAT_32_32 = 0xb, 6044 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 6045 BUF_DATA_FORMAT_32_32_32 = 0xd, 6046 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 6047 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 6048 } BUF_DATA_FORMAT; 6049 typedef enum IMG_DATA_FORMAT { 6050 IMG_DATA_FORMAT_INVALID = 0x0, 6051 IMG_DATA_FORMAT_8 = 0x1, 6052 IMG_DATA_FORMAT_16 = 0x2, 6053 IMG_DATA_FORMAT_8_8 = 0x3, 6054 IMG_DATA_FORMAT_32 = 0x4, 6055 IMG_DATA_FORMAT_16_16 = 0x5, 6056 IMG_DATA_FORMAT_10_11_11 = 0x6, 6057 IMG_DATA_FORMAT_11_11_10 = 0x7, 6058 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 6059 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 6060 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 6061 IMG_DATA_FORMAT_32_32 = 0xb, 6062 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 6063 IMG_DATA_FORMAT_32_32_32 = 0xd, 6064 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 6065 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 6066 IMG_DATA_FORMAT_5_6_5 = 0x10, 6067 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 6068 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 6069 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 6070 IMG_DATA_FORMAT_8_24 = 0x14, 6071 IMG_DATA_FORMAT_24_8 = 0x15, 6072 IMG_DATA_FORMAT_X24_8_32 = 0x16, 6073 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 6074 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 6075 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 6076 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 6077 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 6078 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 6079 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 6080 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 6081 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 6082 IMG_DATA_FORMAT_GB_GR = 0x20, 6083 IMG_DATA_FORMAT_BG_RG = 0x21, 6084 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 6085 IMG_DATA_FORMAT_BC1 = 0x23, 6086 IMG_DATA_FORMAT_BC2 = 0x24, 6087 IMG_DATA_FORMAT_BC3 = 0x25, 6088 IMG_DATA_FORMAT_BC4 = 0x26, 6089 IMG_DATA_FORMAT_BC5 = 0x27, 6090 IMG_DATA_FORMAT_BC6 = 0x28, 6091 IMG_DATA_FORMAT_BC7 = 0x29, 6092 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 6093 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 6094 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 6095 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 6096 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 6097 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 6098 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 6099 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 6100 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 6101 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 6102 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 6103 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 6104 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 6105 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 6106 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 6107 IMG_DATA_FORMAT_4_4 = 0x39, 6108 IMG_DATA_FORMAT_6_5_5 = 0x3a, 6109 IMG_DATA_FORMAT_1 = 0x3b, 6110 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 6111 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 6112 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 6113 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 6114 } IMG_DATA_FORMAT; 6115 typedef enum BUF_NUM_FORMAT { 6116 BUF_NUM_FORMAT_UNORM = 0x0, 6117 BUF_NUM_FORMAT_SNORM = 0x1, 6118 BUF_NUM_FORMAT_USCALED = 0x2, 6119 BUF_NUM_FORMAT_SSCALED = 0x3, 6120 BUF_NUM_FORMAT_UINT = 0x4, 6121 BUF_NUM_FORMAT_SINT = 0x5, 6122 BUF_NUM_FORMAT_SNORM_OGL = 0x6, 6123 BUF_NUM_FORMAT_FLOAT = 0x7, 6124 } BUF_NUM_FORMAT; 6125 typedef enum IMG_NUM_FORMAT { 6126 IMG_NUM_FORMAT_UNORM = 0x0, 6127 IMG_NUM_FORMAT_SNORM = 0x1, 6128 IMG_NUM_FORMAT_USCALED = 0x2, 6129 IMG_NUM_FORMAT_SSCALED = 0x3, 6130 IMG_NUM_FORMAT_UINT = 0x4, 6131 IMG_NUM_FORMAT_SINT = 0x5, 6132 IMG_NUM_FORMAT_SNORM_OGL = 0x6, 6133 IMG_NUM_FORMAT_FLOAT = 0x7, 6134 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 6135 IMG_NUM_FORMAT_SRGB = 0x9, 6136 IMG_NUM_FORMAT_UBNORM = 0xa, 6137 IMG_NUM_FORMAT_UBNORM_OGL = 0xb, 6138 IMG_NUM_FORMAT_UBINT = 0xc, 6139 IMG_NUM_FORMAT_UBSCALED = 0xd, 6140 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 6141 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 6142 } IMG_NUM_FORMAT; 6143 typedef enum TileType { 6144 ARRAY_COLOR_TILE = 0x0, 6145 ARRAY_DEPTH_TILE = 0x1, 6146 } TileType; 6147 typedef enum NonDispTilingOrder { 6148 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 6149 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 6150 } NonDispTilingOrder; 6151 typedef enum MicroTileMode { 6152 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 6153 ADDR_SURF_THIN_MICRO_TILING = 0x1, 6154 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 6155 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 6156 ADDR_SURF_THICK_MICRO_TILING = 0x4, 6157 } MicroTileMode; 6158 typedef enum TileSplit { 6159 ADDR_SURF_TILE_SPLIT_64B = 0x0, 6160 ADDR_SURF_TILE_SPLIT_128B = 0x1, 6161 ADDR_SURF_TILE_SPLIT_256B = 0x2, 6162 ADDR_SURF_TILE_SPLIT_512B = 0x3, 6163 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 6164 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 6165 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 6166 } TileSplit; 6167 typedef enum SampleSplit { 6168 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 6169 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 6170 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 6171 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 6172 } SampleSplit; 6173 typedef enum PipeConfig { 6174 ADDR_SURF_P2 = 0x0, 6175 ADDR_SURF_P2_RESERVED0 = 0x1, 6176 ADDR_SURF_P2_RESERVED1 = 0x2, 6177 ADDR_SURF_P2_RESERVED2 = 0x3, 6178 ADDR_SURF_P4_8x16 = 0x4, 6179 ADDR_SURF_P4_16x16 = 0x5, 6180 ADDR_SURF_P4_16x32 = 0x6, 6181 ADDR_SURF_P4_32x32 = 0x7, 6182 ADDR_SURF_P8_16x16_8x16 = 0x8, 6183 ADDR_SURF_P8_16x32_8x16 = 0x9, 6184 ADDR_SURF_P8_32x32_8x16 = 0xa, 6185 ADDR_SURF_P8_16x32_16x16 = 0xb, 6186 ADDR_SURF_P8_32x32_16x16 = 0xc, 6187 ADDR_SURF_P8_32x32_16x32 = 0xd, 6188 ADDR_SURF_P8_32x64_32x32 = 0xe, 6189 ADDR_SURF_P8_RESERVED0 = 0xf, 6190 ADDR_SURF_P16_32x32_8x16 = 0x10, 6191 ADDR_SURF_P16_32x32_16x16 = 0x11, 6192 } PipeConfig; 6193 typedef enum NumBanks { 6194 ADDR_SURF_2_BANK = 0x0, 6195 ADDR_SURF_4_BANK = 0x1, 6196 ADDR_SURF_8_BANK = 0x2, 6197 ADDR_SURF_16_BANK = 0x3, 6198 } NumBanks; 6199 typedef enum BankWidth { 6200 ADDR_SURF_BANK_WIDTH_1 = 0x0, 6201 ADDR_SURF_BANK_WIDTH_2 = 0x1, 6202 ADDR_SURF_BANK_WIDTH_4 = 0x2, 6203 ADDR_SURF_BANK_WIDTH_8 = 0x3, 6204 } BankWidth; 6205 typedef enum BankHeight { 6206 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 6207 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 6208 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 6209 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 6210 } BankHeight; 6211 typedef enum BankWidthHeight { 6212 ADDR_SURF_BANK_WH_1 = 0x0, 6213 ADDR_SURF_BANK_WH_2 = 0x1, 6214 ADDR_SURF_BANK_WH_4 = 0x2, 6215 ADDR_SURF_BANK_WH_8 = 0x3, 6216 } BankWidthHeight; 6217 typedef enum MacroTileAspect { 6218 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 6219 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 6220 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 6221 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 6222 } MacroTileAspect; 6223 typedef enum TCC_CACHE_POLICIES { 6224 TCC_CACHE_POLICY_LRU = 0x0, 6225 TCC_CACHE_POLICY_STREAM = 0x1, 6226 TCC_CACHE_POLICY_BYPASS = 0x2, 6227 } TCC_CACHE_POLICIES; 6228 typedef enum MTYPE { 6229 MTYPE_NC_NV = 0x0, 6230 MTYPE_NC = 0x1, 6231 MTYPE_CC = 0x2, 6232 MTYPE_UC = 0x3, 6233 } MTYPE; 6234 typedef enum PERFMON_COUNTER_MODE { 6235 PERFMON_COUNTER_MODE_ACCUM = 0x0, 6236 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 6237 PERFMON_COUNTER_MODE_MAX = 0x2, 6238 PERFMON_COUNTER_MODE_DIRTY = 0x3, 6239 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 6240 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 6241 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 6242 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 6243 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 6244 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 6245 PERFMON_COUNTER_MODE_RESERVED = 0xf, 6246 } PERFMON_COUNTER_MODE; 6247 typedef enum PERFMON_SPM_MODE { 6248 PERFMON_SPM_MODE_OFF = 0x0, 6249 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 6250 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 6251 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 6252 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 6253 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 6254 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 6255 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 6256 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 6257 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 6258 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 6259 } PERFMON_SPM_MODE; 6260 typedef enum SurfaceTiling { 6261 ARRAY_LINEAR = 0x0, 6262 ARRAY_TILED = 0x1, 6263 } SurfaceTiling; 6264 typedef enum SurfaceArray { 6265 ARRAY_1D = 0x0, 6266 ARRAY_2D = 0x1, 6267 ARRAY_3D = 0x2, 6268 ARRAY_3D_SLICE = 0x3, 6269 } SurfaceArray; 6270 typedef enum ColorArray { 6271 ARRAY_2D_ALT_COLOR = 0x0, 6272 ARRAY_2D_COLOR = 0x1, 6273 ARRAY_3D_SLICE_COLOR = 0x3, 6274 } ColorArray; 6275 typedef enum DepthArray { 6276 ARRAY_2D_ALT_DEPTH = 0x0, 6277 ARRAY_2D_DEPTH = 0x1, 6278 } DepthArray; 6279 6280 #endif /* GFX_7_2_ENUM_H */ 6281