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Searched refs:SPLL_REF_DIV_MASK (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/radeon/
Drv740d.h31 #define SPLL_REF_DIV_MASK (0x3f << 4) macro
Drv730d.h32 #define SPLL_REF_DIV_MASK (0x3f << 4) macro
Drs780d.h30 # define SPLL_REF_DIV_MASK (7 << 2) macro
Drv740_dpm.c146 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); in rv740_populate_sclk_value()
Drs780_dpm.c988 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; in rs780_dpm_debugfs_print_current_performance_level()
1010 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; in rs780_dpm_get_current_sclk()
Drv730_dpm.c76 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK); in rv730_populate_sclk_value()
Drv770d.h95 #define SPLL_REF_DIV_MASK (0x3f << 4) macro
Dnid.h543 #define SPLL_REF_DIV_MASK (0x3f << 4) macro
Dsid.h90 #define SPLL_REF_DIV_MASK (0x3f << 4) macro
Dcikd.h253 #define SPLL_REF_DIV_MASK (0x3f << 5) macro
Devergreend.h79 #define SPLL_REF_DIV_MASK (0x3f << 4) macro
Dr600d.h1274 # define SPLL_REF_DIV_MASK (7 << 2) macro
Drv770_dpm.c527 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK); in rv770_populate_sclk_value()
Dni_dpm.c2029 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); in ni_calculate_sclk_params()
Dsi_dpm.c4749 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); in si_calculate_sclk_params()
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dsid.h91 #define SPLL_REF_DIV_MASK (0x3f << 4) macro
/linux-6.12.1/drivers/gpu/drm/amd/pm/legacy-dpm/
Dsi_dpm.c5295 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); in si_calculate_sclk_params()