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Searched refs:SPLL_CTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_pch_refclk.c398 u32 ctl = intel_de_read(dev_priv, SPLL_CTL); in spll_uses_pch_ssc()
Dintel_dpll_mgr.c706 intel_de_write(i915, SPLL_CTL, hw_state->spll); in hsw_ddi_spll_enable()
707 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_enable()
732 intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0); in hsw_ddi_spll_disable()
733 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_disable()
778 val = intel_de_read(i915, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
Dintel_display_power.c1189 intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, in assert_can_disable_lcpll()
/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Dhandlers.c483 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { in bdw_vgpu_get_dp_bitrate()
495 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); in bdw_vgpu_get_dp_bitrate()
/linux-6.12.1/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c487 MMIO_D(SPLL_CTL); in iterate_generic_mmio()
Di915_reg.h3949 #define SPLL_CTL _MMIO(0x46020) macro