Searched refs:SOR_LANE_SEQ_CTL (Results 1 – 2 of 2) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/tegra/ |
| D | sor.h | 156 #define SOR_LANE_SEQ_CTL 0x21 macro
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| D | sor.c | 679 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
684 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
711 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
716 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
1568 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
2319 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2328 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2331 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
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