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Searched refs:SOC15_REG_ENTRY_STR (Results 1 – 20 of 20) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dsdma_v7_0.c61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),
[all …]
Dsdma_v6_0.c61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),
[all …]
Dsdma_v5_2.c64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
[all …]
Dsdma_v5_0.c63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
[all …]
Dvcn_v5_0_0.c41 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
42 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
43 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
44 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
45 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
46 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
47 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
48 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
[all …]
Dgfx_v12_0.c67 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
72 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
74 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
75 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
[all …]
Dvcn_v4_0_5.c56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
[all …]
Dsdma_v4_4_2.c50 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG),
51 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG),
52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG),
53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG),
54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM),
55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI),
56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH),
57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS),
58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS),
59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0),
[all …]
Dsdma_v4_0.c76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
[all …]
Dvcn_v4_0_3.c49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
[all …]
Dgfx_v11_0.c102 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
103 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
104 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
[all …]
Dgfx_v9_0.c154 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
155 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
156 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
157 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
158 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
159 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
160 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
161 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
162 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
163 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
[all …]
Dgfx_v9_4_3.c68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
[all …]
Dvcn_v1_0.c49 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
50 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
51 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
52 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
53 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
54 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
55 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
56 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
57 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
[all …]
Dvcn_v2_0.c57 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
[all …]
Dvcn_v4_0.c56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
[all …]
Dvcn_v2_5.c59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
[all …]
Dgfx_v10_0.c280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
[all …]
Dvcn_v3_0.c64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
[all …]
Dsoc15.h91 #define SOC15_REG_ENTRY_STR(ip, inst, reg) \ macro