Searched refs:SMU_DCEFCLK (Results 1 – 10 of 10) sorted by relevance
222 case SMU_DCEFCLK: in renoir_get_dpm_clk_limited()567 case SMU_DCEFCLK: in renoir_print_clk_levels()590 case SMU_DCEFCLK: in renoir_print_clk_levels()
296 SMU_DCEFCLK, enumerator
710 SMU_DCEFCLK, in smu_v13_0_7_set_default_dpm_table()1232 case SMU_DCEFCLK: in smu_v13_0_7_print_clk_levels()1248 case SMU_DCEFCLK: in smu_v13_0_7_print_clk_levels()1969 case SMU_DCEFCLK: in smu_v13_0_7_force_clk_levels()
712 SMU_DCEFCLK, in smu_v13_0_0_set_default_dpm_table()1243 case SMU_DCEFCLK: in smu_v13_0_0_print_clk_levels()1259 case SMU_DCEFCLK: in smu_v13_0_0_print_clk_levels()1980 case SMU_DCEFCLK: in smu_v13_0_0_force_clk_levels()
923 SMU_DCEFCLK); in smu_v13_0_init_max_sustainable_clocks()1092 clk_select = SMU_DCEFCLK; in smu_v13_0_display_clock_voltage_request()
646 SMU_DCEFCLK, in smu_v14_0_2_set_default_dpm_table()1112 case SMU_DCEFCLK: in smu_v14_0_2_print_clk_levels()1128 case SMU_DCEFCLK: in smu_v14_0_2_print_clk_levels()1462 case SMU_DCEFCLK: in smu_v14_0_2_force_clk_levels()
1067 SMU_DCEFCLK, in navi10_set_default_dpm_table()1284 case SMU_DCEFCLK: in navi10_emit_clk_levels()1495 case SMU_DCEFCLK: in navi10_print_clk_levels()1696 case SMU_DCEFCLK: in navi10_force_clk_levels()1807 case SMU_DCEFCLK: in navi10_get_clock_by_type_with_latency()
865 SMU_DCEFCLK); in smu_v11_0_init_max_sustainable_clocks()1062 clk_select = SMU_DCEFCLK; in smu_v11_0_display_clock_voltage_request()
1084 SMU_DCEFCLK, in sienna_cichlid_set_default_dpm_table()1306 case SMU_DCEFCLK: in sienna_cichlid_print_clk_levels()1476 case SMU_DCEFCLK: in sienna_cichlid_force_clk_levels()
2467 clk_type = SMU_DCEFCLK; break; in smu_force_ppclk_levels()2850 clk_type = SMU_DCEFCLK; break; in smu_convert_to_smuclk()3206 clk_type = SMU_DCEFCLK; in smu_get_clock_by_type_with_latency()