1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _smuio_14_0_2_SH_MASK_HEADER 24 #define _smuio_14_0_2_SH_MASK_HEADER 25 26 27 // addressBlock: smuio_smuio_tsc_SmuSmuioDec 28 //PWROK_REFCLK_GAP_CYCLES 29 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 30 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 31 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL 32 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L 33 //GOLDEN_TSC_INCREMENT_UPPER 34 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 35 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL 36 //GOLDEN_TSC_INCREMENT_LOWER 37 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 38 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL 39 //GOLDEN_TSC_COUNT_UPPER 40 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 41 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL 42 //GOLDEN_TSC_COUNT_LOWER 43 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 44 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL 45 //SOC_GOLDEN_TSC_SHADOW_UPPER 46 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0 47 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL 48 //SOC_GOLDEN_TSC_SHADOW_LOWER 49 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0 50 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL 51 //SOC_GAP_PWROK 52 #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 53 #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L 54 55 56 // addressBlock: smuio_smuio_swtimer_SmuSmuioDec 57 //PWR_VIRT_RESET_REQ 58 #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 59 #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f 60 #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL 61 #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L 62 //PWR_DISP_TIMER_CONTROL 63 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 64 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 65 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 66 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 67 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 68 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 69 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 70 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 71 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 72 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 73 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 74 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 75 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 76 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 77 //PWR_DISP_TIMER_DEBUG 78 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 79 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 80 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 81 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 82 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 83 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 84 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 85 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 86 //PWR_DISP_TIMER2_CONTROL 87 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 88 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 89 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 90 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 91 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 92 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 93 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 94 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 95 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 96 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 97 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 98 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 99 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 100 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 101 //PWR_DISP_TIMER2_DEBUG 102 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 103 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 104 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 105 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 106 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 107 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 108 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 109 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 110 //PWR_DISP_TIMER_GLOBAL_CONTROL 111 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 112 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 113 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL 114 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L 115 //PWR_IH_CONTROL 116 #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 117 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 118 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 119 #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f 120 #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL 121 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L 122 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L 123 #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L 124 125 126 // addressBlock: smuio_smuio_misc_SmuSmuioDec 127 //SMUIO_MCM_CONFIG 128 #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 129 #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 130 #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x8 131 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0xc 132 #define SMUIO_MCM_CONFIG__DIE_CONFIG__SHIFT 0xd 133 #define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10 134 #define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11 135 #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L 136 #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL 137 #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000300L 138 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00001000L 139 #define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L 140 #define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L 141 //IP_DISCOVERY_VERSION 142 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 143 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL 144 //SCRATCH_REGISTER0 145 #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 146 #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL 147 //SCRATCH_REGISTER1 148 #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 149 #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL 150 //SCRATCH_REGISTER2 151 #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 152 #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL 153 //SCRATCH_REGISTER3 154 #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 155 #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL 156 //SCRATCH_REGISTER4 157 #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 158 #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL 159 //SCRATCH_REGISTER5 160 #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 161 #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL 162 //SCRATCH_REGISTER6 163 #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 164 #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL 165 //SCRATCH_REGISTER7 166 #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 167 #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL 168 169 170 // addressBlock: smuio_smuio_i2c_SmuSmuioDec 171 //CKSVII2C_IC_CON 172 #define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 173 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 174 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 175 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 176 #define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 177 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 178 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 179 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 180 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 181 #define CKSVII2C_IC_CON__BUS_CLEAR_FEATURE_CTRL__SHIFT 0xb 182 #define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L 183 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L 184 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L 185 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L 186 #define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L 187 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L 188 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L 189 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L 190 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 191 //CKSVII2C_IC_TAR 192 #define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 193 #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa 194 #define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb 195 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc 196 #define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL 197 #define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L 198 #define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L 199 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L 200 //CKSVII2C_IC_SAR 201 #define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 202 #define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL 203 //CKSVII2C_IC_HS_MADDR 204 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 205 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L 206 //CKSVII2C_IC_DATA_CMD 207 #define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 208 #define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 209 #define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 210 #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa 211 #define CKSVII2C_IC_DATA_CMD__FIRST_DATA_BYTE__SHIFT 0xb 212 #define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL 213 #define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L 214 #define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L 215 #define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L 216 //CKSVII2C_IC_SS_SCL_HCNT 217 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 218 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL 219 //CKSVII2C_IC_SS_SCL_LCNT 220 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 221 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL 222 //CKSVII2C_IC_FS_SCL_HCNT 223 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 224 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL 225 //CKSVII2C_IC_FS_SCL_LCNT 226 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 227 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL 228 //CKSVII2C_IC_HS_SCL_HCNT 229 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 230 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL 231 //CKSVII2C_IC_HS_SCL_LCNT 232 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 233 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL 234 //CKSVII2C_IC_INTR_STAT 235 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 236 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 237 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 238 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 239 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 240 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 241 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 242 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 243 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 244 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 245 #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa 246 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb 247 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc 248 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd 249 #define CKSVII2C_IC_INTR_STAT__R_SCL_STUCK_AT_LOW__SHIFT 0xe 250 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L 251 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L 252 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L 253 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L 254 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L 255 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L 256 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L 257 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L 258 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L 259 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L 260 #define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L 261 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L 262 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L 263 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L 264 //CKSVII2C_IC_INTR_MASK 265 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 266 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 267 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 268 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 269 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 270 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 271 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 272 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 273 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 274 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 275 #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa 276 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb 277 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc 278 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd 279 #define CKSVII2C_IC_INTR_MASK__M_SCL_STUCK_AT_LOW__SHIFT 0xe 280 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L 281 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L 282 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L 283 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L 284 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L 285 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L 286 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L 287 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L 288 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L 289 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L 290 #define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L 291 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L 292 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L 293 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L 294 //CKSVII2C_IC_RAW_INTR_STAT 295 //CKSVII2C_IC_RX_TL 296 #define CKSVII2C_IC_RX_TL__RX_TL__SHIFT 0x0 297 //CKSVII2C_IC_TX_TL 298 #define CKSVII2C_IC_TX_TL__TX_TL__SHIFT 0x0 299 //CKSVII2C_IC_CLR_INTR 300 //CKSVII2C_IC_CLR_RX_UNDER 301 //CKSVII2C_IC_CLR_RX_OVER 302 //CKSVII2C_IC_CLR_TX_OVER 303 //CKSVII2C_IC_CLR_RD_REQ 304 //CKSVII2C_IC_CLR_TX_ABRT 305 //CKSVII2C_IC_CLR_RX_DONE 306 //CKSVII2C_IC_CLR_ACTIVITY 307 //CKSVII2C_IC_CLR_STOP_DET 308 //CKSVII2C_IC_CLR_START_DET 309 //CKSVII2C_IC_CLR_GEN_CALL 310 //CKSVII2C_IC_ENABLE 311 #define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 312 #define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 313 #define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK__SHIFT 0x2 314 #define CKSVII2C_IC_ENABLE__SDA_STUCK_RECOVERY_ENABLE__SHIFT 0x3 315 #define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L 316 #define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L 317 //CKSVII2C_IC_STATUS 318 #define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 319 #define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 320 #define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 321 #define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 322 #define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 323 #define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 324 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 325 #define CKSVII2C_IC_STATUS__MST_HOLD_TX_FIFO_EMPTY__SHIFT 0x7 326 #define CKSVII2C_IC_STATUS__MST_HOLD_RX_FIFO_FULL__SHIFT 0x8 327 #define CKSVII2C_IC_STATUS__SLV_HOLD_TX_FIFO_EMPTY__SHIFT 0x9 328 #define CKSVII2C_IC_STATUS__SLV_HOLD_RX_FIFO_FULL__SHIFT 0xa 329 #define CKSVII2C_IC_STATUS__SDA_STUCK_NOT_RECOVERED__SHIFT 0xb 330 #define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L 331 #define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L 332 #define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L 333 #define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L 334 #define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L 335 #define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L 336 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L 337 //CKSVII2C_IC_TXFLR 338 #define CKSVII2C_IC_TXFLR__TXFLR__SHIFT 0x0 339 //CKSVII2C_IC_RXFLR 340 #define CKSVII2C_IC_RXFLR__RXFLR__SHIFT 0x0 341 //CKSVII2C_IC_SDA_HOLD 342 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD__SHIFT 0x0 343 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD__SHIFT 0x10 344 //CKSVII2C_IC_TX_ABRT_SOURCE 345 //CKSVII2C_IC_SLV_DATA_NACK_ONLY 346 //CKSVII2C_IC_DMA_CR 347 //CKSVII2C_IC_DMA_TDLR 348 //CKSVII2C_IC_DMA_RDLR 349 //CKSVII2C_IC_SDA_SETUP 350 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 351 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL 352 //CKSVII2C_IC_ACK_GENERAL_CALL 353 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT 0x0 354 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK 0x00000001L 355 //CKSVII2C_IC_ENABLE_STATUS 356 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 357 #define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY__SHIFT 0x1 358 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST__SHIFT 0x2 359 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L 360 //CKSVII2C_IC_FS_SPKLEN 361 #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT 0x0 362 #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK 0x000000FFL 363 //CKSVII2C_IC_HS_SPKLEN 364 #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT 0x0 365 #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK 0x000000FFL 366 //CKSVII2C_IC_CLR_RESTART_DET 367 //CKSVII2C_IC_COMP_PARAM_1 368 #define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH__SHIFT 0x0 369 #define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE__SHIFT 0x2 370 #define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES__SHIFT 0x4 371 #define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT 0x5 372 #define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA__SHIFT 0x6 373 #define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS__SHIFT 0x7 374 #define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH__SHIFT 0x8 375 #define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH__SHIFT 0x10 376 //CKSVII2C_IC_COMP_VERSION 377 #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT 0x0 378 #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK 0xFFFFFFFFL 379 //CKSVII2C_IC_COMP_TYPE 380 #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0 381 #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL 382 //CKSVII2C1_IC_CON 383 #define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0 384 #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1 385 #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3 386 #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4 387 #define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5 388 #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6 389 #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7 390 #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8 391 #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9 392 #define CKSVII2C1_IC_CON__BUS_CLEAR_FEATURE_CTRL1__SHIFT 0xb 393 #define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L 394 #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L 395 #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L 396 #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L 397 #define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L 398 #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L 399 #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L 400 #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L 401 #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 402 //CKSVII2C1_IC_TAR 403 #define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0 404 #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa 405 #define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb 406 #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc 407 #define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL 408 #define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L 409 #define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L 410 #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L 411 //CKSVII2C1_IC_SAR 412 #define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0 413 #define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL 414 //CKSVII2C1_IC_HS_MADDR 415 #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0 416 #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L 417 //CKSVII2C1_IC_DATA_CMD 418 #define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0 419 #define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8 420 #define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9 421 #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa 422 #define CKSVII2C1_IC_DATA_CMD__FIRST1_DATA_BYTE__SHIFT 0xb 423 #define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL 424 #define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L 425 #define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L 426 #define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L 427 //CKSVII2C1_IC_SS_SCL_HCNT 428 #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0 429 #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL 430 //CKSVII2C1_IC_SS_SCL_LCNT 431 #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0 432 #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL 433 //CKSVII2C1_IC_FS_SCL_HCNT 434 #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0 435 #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL 436 //CKSVII2C1_IC_FS_SCL_LCNT 437 #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0 438 #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL 439 //CKSVII2C1_IC_HS_SCL_HCNT 440 #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0 441 #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL 442 //CKSVII2C1_IC_HS_SCL_LCNT 443 #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0 444 #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL 445 //CKSVII2C1_IC_INTR_STAT 446 #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0 447 #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1 448 #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2 449 #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3 450 #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4 451 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5 452 #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6 453 #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7 454 #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8 455 #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9 456 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa 457 #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb 458 #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc 459 #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd 460 #define CKSVII2C1_IC_INTR_STAT__R1_SCL_STUCK_AT_LOW__SHIFT 0xe 461 #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L 462 #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L 463 #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L 464 #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L 465 #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L 466 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L 467 #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L 468 #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L 469 #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L 470 #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L 471 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L 472 #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L 473 #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L 474 #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L 475 //CKSVII2C1_IC_INTR_MASK 476 #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0 477 #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1 478 #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2 479 #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3 480 #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4 481 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5 482 #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6 483 #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7 484 #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8 485 #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9 486 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa 487 #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb 488 #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc 489 #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd 490 #define CKSVII2C1_IC_INTR_MASK__M1_SCL_STUCK_AT_LOW__SHIFT 0xe 491 #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L 492 #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L 493 #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L 494 #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L 495 #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L 496 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L 497 #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L 498 #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L 499 #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L 500 #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L 501 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L 502 #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L 503 #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L 504 #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L 505 //CKSVII2C1_IC_RAW_INTR_STAT 506 //CKSVII2C1_IC_RX_TL 507 #define CKSVII2C1_IC_RX_TL__RX1_TL__SHIFT 0x0 508 //CKSVII2C1_IC_TX_TL 509 #define CKSVII2C1_IC_TX_TL__TX1_TL__SHIFT 0x0 510 //CKSVII2C1_IC_CLR_INTR 511 //CKSVII2C1_IC_CLR_RX_UNDER 512 //CKSVII2C1_IC_CLR_RX_OVER 513 //CKSVII2C1_IC_CLR_TX_OVER 514 //CKSVII2C1_IC_CLR_RD_REQ 515 //CKSVII2C1_IC_CLR_TX_ABRT 516 //CKSVII2C1_IC_CLR_RX_DONE 517 //CKSVII2C1_IC_CLR_ACTIVITY 518 //CKSVII2C1_IC_CLR_STOP_DET 519 //CKSVII2C1_IC_CLR_START_DET 520 //CKSVII2C1_IC_CLR_GEN_CALL 521 //CKSVII2C1_IC_ENABLE 522 #define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0 523 #define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1 524 #define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK__SHIFT 0x2 525 #define CKSVII2C1_IC_ENABLE__SDA1_STUCK_RECOVERY_ENABLE__SHIFT 0x3 526 #define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L 527 #define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L 528 //CKSVII2C1_IC_STATUS 529 #define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0 530 #define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1 531 #define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2 532 #define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3 533 #define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4 534 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5 535 #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6 536 #define CKSVII2C1_IC_STATUS__MST1_HOLD_TX_FIFO_EMPTY__SHIFT 0x7 537 #define CKSVII2C1_IC_STATUS__MST1_HOLD_RX_FIFO_FULL__SHIFT 0x8 538 #define CKSVII2C1_IC_STATUS__SLV1_HOLD_TX_FIFO_EMPTY__SHIFT 0x9 539 #define CKSVII2C1_IC_STATUS__SLV1_HOLD_RX_FIFO_FULL__SHIFT 0xa 540 #define CKSVII2C1_IC_STATUS__SDA1_STUCK_NOT_RECOVERED__SHIFT 0xb 541 #define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L 542 #define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L 543 #define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L 544 #define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L 545 #define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L 546 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L 547 #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L 548 //CKSVII2C1_IC_TXFLR 549 #define CKSVII2C1_IC_TXFLR__TXFLR1__SHIFT 0x0 550 //CKSVII2C1_IC_RXFLR 551 #define CKSVII2C1_IC_RXFLR__RXFLR1__SHIFT 0x0 552 //CKSVII2C1_IC_SDA_HOLD 553 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD__SHIFT 0x0 554 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD__SHIFT 0x10 555 //CKSVII2C1_IC_TX_ABRT_SOURCE 556 //CKSVII2C1_IC_SLV_DATA_NACK_ONLY 557 //CKSVII2C1_IC_DMA_CR 558 //CKSVII2C1_IC_DMA_TDLR 559 //CKSVII2C1_IC_DMA_RDLR 560 //CKSVII2C1_IC_SDA_SETUP 561 #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0 562 #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL 563 //CKSVII2C1_IC_ACK_GENERAL_CALL 564 #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT 0x0 565 #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK 0x00000001L 566 //CKSVII2C1_IC_ENABLE_STATUS 567 #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0 568 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY__SHIFT 0x1 569 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST__SHIFT 0x2 570 #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L 571 //CKSVII2C1_IC_FS_SPKLEN 572 #define CKSVII2C1_IC_FS_SPKLEN__FS1_SPKLEN__SHIFT 0x0 573 //CKSVII2C1_IC_HS_SPKLEN 574 #define CKSVII2C1_IC_HS_SPKLEN__HS1_SPKLEN__SHIFT 0x0 575 //CKSVII2C1_IC_CLR_RESTART_DET 576 //CKSVII2C1_IC_COMP_PARAM_1 577 #define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH__SHIFT 0x0 578 #define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE__SHIFT 0x2 579 #define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES__SHIFT 0x4 580 #define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT 0x5 581 #define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA__SHIFT 0x6 582 #define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS__SHIFT 0x7 583 #define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH__SHIFT 0x8 584 #define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH__SHIFT 0x10 585 //CKSVII2C1_IC_COMP_VERSION 586 #define CKSVII2C1_IC_COMP_VERSION__COMP1_VERSION__SHIFT 0x0 587 //CKSVII2C1_IC_COMP_TYPE 588 #define CKSVII2C1_IC_COMP_TYPE__COMP1_TYPE__SHIFT 0x0 589 //SMUIO_PWRMGT 590 #define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0 591 #define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4 592 #define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L 593 #define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L 594 595 596 // addressBlock: smuio_smuio_rom_SmuSmuioDec 597 //ROM_CNTL 598 #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0 599 #define ROM_CNTL__READ_MODE__SHIFT 0x1 600 #define ROM_CNTL__READ_MODE_OVERRIDE__SHIFT 0x3 601 #define ROM_CNTL__SPI_TIMING_RELAX_SCK__SHIFT 0x4 602 #define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE__SHIFT 0x5 603 #define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE__SHIFT 0x6 604 #define ROM_CNTL__DUMMY_CYCLE_NUM__SHIFT 0x8 605 #define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x13 606 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x14 607 #define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x15 608 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x16 609 #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x17 610 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c 611 #define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE__SHIFT 0x1d 612 #define ROM_CNTL__PAD_SAMPLE_MODE__SHIFT 0x1e 613 #define ROM_CNTL__PAD_SAMPLE_MODE_OVERRIDE__SHIFT 0x1f 614 #define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L 615 #define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00080000L 616 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00100000L 617 #define ROM_CNTL__SPI_FAST_MODE_MASK 0x00200000L 618 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00400000L 619 #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F800000L 620 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L 621 //PAGE_MIRROR_CNTL 622 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 623 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 624 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 625 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x1c 626 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x01FFFFFFL 627 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L 628 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L 629 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x10000000L 630 //ROM_STATUS 631 #define ROM_STATUS__ROM_BUSY__SHIFT 0x0 632 #define ROM_STATUS__ROM_BUSY_MASK 0x00000001L 633 //CGTT_ROM_CLK_CTRL0 634 #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 635 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 636 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 637 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 638 #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 639 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 640 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 641 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 642 //ROM_INDEX 643 #define ROM_INDEX__ROM_INDEX__SHIFT 0x0 644 #define ROM_INDEX__ROM_INDEX_MASK 0x01FFFFFFL 645 //ROM_DATA 646 #define ROM_DATA__ROM_DATA__SHIFT 0x0 647 #define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL 648 //ROM_START 649 #define ROM_START__ROM_START__SHIFT 0x0 650 #define ROM_START__ROM_START_MASK 0x01FFFFFFL 651 //ROM_SW_CNTL 652 #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 653 #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 654 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x13 655 #define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL 656 #define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00070000L 657 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00080000L 658 //ROM_SW_STATUS 659 #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 660 #define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L 661 //ROM_SW_COMMAND 662 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 663 #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 664 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL 665 #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L 666 //ROM_SW_DATA_1 667 #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 668 #define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL 669 //ROM_SW_DATA_2 670 #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 671 #define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL 672 //ROM_SW_DATA_3 673 #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 674 #define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL 675 //ROM_SW_DATA_4 676 #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 677 #define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL 678 //ROM_SW_DATA_5 679 #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 680 #define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL 681 //ROM_SW_DATA_6 682 #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 683 #define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL 684 //ROM_SW_DATA_7 685 #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 686 #define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL 687 //ROM_SW_DATA_8 688 #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 689 #define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL 690 //ROM_SW_DATA_9 691 #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 692 #define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL 693 //ROM_SW_DATA_10 694 #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 695 #define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL 696 //ROM_SW_DATA_11 697 #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 698 #define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL 699 //ROM_SW_DATA_12 700 #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 701 #define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL 702 //ROM_SW_DATA_13 703 #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 704 #define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL 705 //ROM_SW_DATA_14 706 #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 707 #define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL 708 //ROM_SW_DATA_15 709 #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 710 #define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL 711 //ROM_SW_DATA_16 712 #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 713 #define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL 714 //ROM_SW_DATA_17 715 #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 716 #define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL 717 //ROM_SW_DATA_18 718 #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 719 #define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL 720 //ROM_SW_DATA_19 721 #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 722 #define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL 723 //ROM_SW_DATA_20 724 #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 725 #define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL 726 //ROM_SW_DATA_21 727 #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 728 #define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL 729 //ROM_SW_DATA_22 730 #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 731 #define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL 732 //ROM_SW_DATA_23 733 #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 734 #define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL 735 //ROM_SW_DATA_24 736 #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 737 #define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL 738 //ROM_SW_DATA_25 739 #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 740 #define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL 741 //ROM_SW_DATA_26 742 #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 743 #define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL 744 //ROM_SW_DATA_27 745 #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 746 #define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL 747 //ROM_SW_DATA_28 748 #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 749 #define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL 750 //ROM_SW_DATA_29 751 #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 752 #define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL 753 //ROM_SW_DATA_30 754 #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 755 #define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL 756 //ROM_SW_DATA_31 757 #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 758 #define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL 759 //ROM_SW_DATA_32 760 #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 761 #define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL 762 //ROM_SW_DATA_33 763 #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 764 #define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL 765 //ROM_SW_DATA_34 766 #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 767 #define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL 768 //ROM_SW_DATA_35 769 #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 770 #define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL 771 //ROM_SW_DATA_36 772 #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 773 #define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL 774 //ROM_SW_DATA_37 775 #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 776 #define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL 777 //ROM_SW_DATA_38 778 #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 779 #define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL 780 //ROM_SW_DATA_39 781 #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 782 #define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL 783 //ROM_SW_DATA_40 784 #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 785 #define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL 786 //ROM_SW_DATA_41 787 #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 788 #define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL 789 //ROM_SW_DATA_42 790 #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 791 #define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL 792 //ROM_SW_DATA_43 793 #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 794 #define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL 795 //ROM_SW_DATA_44 796 #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 797 #define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL 798 //ROM_SW_DATA_45 799 #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 800 #define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL 801 //ROM_SW_DATA_46 802 #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 803 #define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL 804 //ROM_SW_DATA_47 805 #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 806 #define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL 807 //ROM_SW_DATA_48 808 #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 809 #define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL 810 //ROM_SW_DATA_49 811 #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 812 #define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL 813 //ROM_SW_DATA_50 814 #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 815 #define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL 816 //ROM_SW_DATA_51 817 #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 818 #define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL 819 //ROM_SW_DATA_52 820 #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 821 #define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL 822 //ROM_SW_DATA_53 823 #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 824 #define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL 825 //ROM_SW_DATA_54 826 #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 827 #define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL 828 //ROM_SW_DATA_55 829 #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 830 #define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL 831 //ROM_SW_DATA_56 832 #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 833 #define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL 834 //ROM_SW_DATA_57 835 #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 836 #define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL 837 //ROM_SW_DATA_58 838 #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 839 #define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL 840 //ROM_SW_DATA_59 841 #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 842 #define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL 843 //ROM_SW_DATA_60 844 #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 845 #define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL 846 //ROM_SW_DATA_61 847 #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 848 #define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL 849 //ROM_SW_DATA_62 850 #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 851 #define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL 852 //ROM_SW_DATA_63 853 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 854 #define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL 855 //ROM_SW_DATA_64 856 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 857 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL 858 859 860 // addressBlock: smuio_smuio_gpio_SmuSmuioDec 861 //SMU_GPIOPAD_SW_INT_STAT 862 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 863 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 864 //SMU_GPIOPAD_MASK 865 #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 866 #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL 867 //SMU_GPIOPAD_A 868 #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 869 #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL 870 //SMU_GPIOPAD_TXIMPSEL 871 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 872 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL 873 //SMU_GPIOPAD_EN 874 #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 875 #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL 876 //SMU_GPIOPAD_Y 877 #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 878 #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL 879 //SMU_GPIOPAD_RXEN 880 #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 881 #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL 882 //SMU_GPIOPAD_RCVR_SEL0 883 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 884 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL 885 //SMU_GPIOPAD_RCVR_SEL1 886 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 887 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL 888 //SMU_GPIOPAD_PU_EN 889 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 890 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL 891 //SMU_GPIOPAD_PD_EN 892 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 893 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL 894 //SMU_GPIOPAD_PINSTRAPS 895 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 896 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 897 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 898 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 899 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 900 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 901 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 902 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 903 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 904 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 905 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 906 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 907 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 908 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 909 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 910 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 911 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 912 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 913 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 914 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 915 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 916 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 917 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 918 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 919 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 920 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 921 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 922 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 923 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 924 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 925 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 926 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 927 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 928 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 929 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 930 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 931 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 932 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 933 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 934 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 935 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 936 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 937 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 938 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 939 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 940 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 941 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 942 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 943 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 944 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 945 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 946 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 947 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 948 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 949 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 950 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 951 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 952 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 953 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 954 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 955 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 956 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 957 //DFT_PINSTRAPS 958 #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 959 #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000000FFL 960 //SMU_GPIOPAD_INT_STAT_EN 961 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 962 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 963 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL 964 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 965 //SMU_GPIOPAD_INT_STAT 966 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 967 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 968 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL 969 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 970 //SMU_GPIOPAD_INT_STAT_AK 971 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 972 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 973 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 974 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 975 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 976 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 977 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 978 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 979 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 980 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 981 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 982 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 983 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 984 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 985 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 986 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 987 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 988 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 989 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 990 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 991 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 992 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 993 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 994 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 995 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 996 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 997 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 998 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 999 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 1000 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 1001 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 1002 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 1003 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 1004 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 1005 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 1006 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 1007 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 1008 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 1009 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 1010 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 1011 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 1012 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 1013 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 1014 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 1015 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 1016 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 1017 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 1018 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 1019 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 1020 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 1021 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 1022 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 1023 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 1024 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 1025 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 1026 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 1027 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 1028 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 1029 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 1030 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 1031 //SMU_GPIOPAD_INT_EN 1032 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 1033 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 1034 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL 1035 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 1036 //SMU_GPIOPAD_INT_TYPE 1037 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 1038 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 1039 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL 1040 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 1041 //SMU_GPIOPAD_INT_POLARITY 1042 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 1043 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 1044 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL 1045 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 1046 //SMUIO_PCC_GPIO_SELECT 1047 #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 1048 #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL 1049 //SMU_GPIOPAD_S0 1050 #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 1051 #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL 1052 //SMU_GPIOPAD_S1 1053 #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 1054 #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL 1055 //SMU_GPIOPAD_SCHMEN 1056 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 1057 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL 1058 //SMU_GPIOPAD_SCL_EN 1059 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 1060 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL 1061 //SMU_GPIOPAD_SDA_EN 1062 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 1063 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL 1064 //SMUIO_GPIO_INT0_SELECT 1065 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 1066 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL 1067 //SMUIO_GPIO_INT1_SELECT 1068 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 1069 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL 1070 //SMUIO_GPIO_INT2_SELECT 1071 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 1072 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL 1073 //SMUIO_GPIO_INT3_SELECT 1074 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 1075 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL 1076 //SMU_GPIOPAD_MP_INT0_STAT 1077 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 1078 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL 1079 //SMU_GPIOPAD_MP_INT1_STAT 1080 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 1081 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL 1082 //SMU_GPIOPAD_MP_INT2_STAT 1083 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 1084 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL 1085 //SMU_GPIOPAD_MP_INT3_STAT 1086 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 1087 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL 1088 //SMIO_INDEX 1089 #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 1090 #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L 1091 //S0_VID_SMIO_CNTL 1092 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 1093 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL 1094 //S1_VID_SMIO_CNTL 1095 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 1096 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL 1097 //OPEN_DRAIN_SELECT 1098 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 1099 #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f 1100 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL 1101 #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L 1102 //SMIO_ENABLE 1103 #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 1104 #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL 1105 1106 #endif 1107