Searched refs:SISLANDS_LEAKAGE_INDEX0 (Results 1 – 4 of 4) sorted by relevance
125 #define SISLANDS_LEAKAGE_INDEX0 0xff01 macro
3176 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()3178 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()3181 SISLANDS_LEAKAGE_INDEX0 + i; in si_get_leakage_vddc()3203 if (index < SISLANDS_LEAKAGE_INDEX0) in si_get_leakage_voltage_from_leakage_index()
93 #define SISLANDS_LEAKAGE_INDEX0 0xff01 macro
3693 …ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 +… in si_get_leakage_vddc()3695 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()3698 SISLANDS_LEAKAGE_INDEX0 + i; in si_get_leakage_vddc()3720 if (index < SISLANDS_LEAKAGE_INDEX0) in si_get_leakage_voltage_from_leakage_index()