1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* Copyright(c) 2015-17 Intel Corporation. */ 3 4 #ifndef __SDW_INTEL_H 5 #define __SDW_INTEL_H 6 7 #include <linux/irqreturn.h> 8 #include <linux/soundwire/sdw.h> 9 10 /********************************************************************* 11 * cAVS and ACE1.x definitions 12 *********************************************************************/ 13 14 #define SDW_SHIM_BASE 0x2C000 15 #define SDW_ALH_BASE 0x2C800 16 #define SDW_SHIM_BASE_ACE 0x38000 17 #define SDW_ALH_BASE_ACE 0x24000 18 #define SDW_LINK_BASE 0x30000 19 #define SDW_LINK_SIZE 0x10000 20 21 /* Intel SHIM Registers Definition */ 22 /* LCAP */ 23 #define SDW_SHIM_LCAP 0x0 24 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0) 25 #define SDW_SHIM_LCAP_MLCS_MASK BIT(8) 26 27 /* LCTL */ 28 #define SDW_SHIM_LCTL 0x4 29 30 #define SDW_SHIM_LCTL_SPA BIT(0) 31 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0) 32 #define SDW_SHIM_LCTL_CPA BIT(8) 33 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8) 34 #define SDW_SHIM_LCTL_MLCS_MASK GENMASK(29, 27) 35 #define SDW_SHIM_MLCS_XTAL_CLK 0x0 36 #define SDW_SHIM_MLCS_CARDINAL_CLK 0x1 37 #define SDW_SHIM_MLCS_AUDIO_PLL_CLK 0x2 38 39 /* SYNC */ 40 #define SDW_SHIM_SYNC 0xC 41 42 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1) 43 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576 (24576 / SDW_CADENCE_GSYNC_KHZ - 1) 44 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1) 45 #define SDW_SHIM_SYNC_SYNCPRD_VAL_96 (96000 / SDW_CADENCE_GSYNC_KHZ - 1) 46 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) 47 #define SDW_SHIM_SYNC_SYNCCPU BIT(15) 48 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) 49 #define SDW_SHIM_SYNC_CMDSYNC BIT(16) 50 #define SDW_SHIM_SYNC_SYNCGO BIT(24) 51 52 /* Control stream capabililities and channel mask */ 53 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 54 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 55 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 56 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 57 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 58 59 /* PCM Stream capabilities */ 60 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 61 62 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) 63 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) 64 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) 65 66 /* PCM Stream Channel Map */ 67 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 68 69 /* PCM Stream Channel Count */ 70 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 71 72 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) 73 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) 74 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) 75 #define SDW_SHIM_PCMSYCM_DIR BIT(15) 76 77 /* IO control */ 78 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 79 80 #define SDW_SHIM_IOCTL_MIF BIT(0) 81 #define SDW_SHIM_IOCTL_CO BIT(1) 82 #define SDW_SHIM_IOCTL_COE BIT(2) 83 #define SDW_SHIM_IOCTL_DO BIT(3) 84 #define SDW_SHIM_IOCTL_DOE BIT(4) 85 #define SDW_SHIM_IOCTL_BKE BIT(5) 86 #define SDW_SHIM_IOCTL_WPDD BIT(6) 87 #define SDW_SHIM_IOCTL_CIBD BIT(8) 88 #define SDW_SHIM_IOCTL_DIBD BIT(9) 89 90 /* Wake Enable*/ 91 #define SDW_SHIM_WAKEEN 0x190 92 93 #define SDW_SHIM_WAKEEN_ENABLE BIT(0) 94 95 /* Wake Status */ 96 #define SDW_SHIM_WAKESTS 0x192 97 98 #define SDW_SHIM_WAKESTS_STATUS BIT(0) 99 100 /* AC Timing control */ 101 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 102 103 #define SDW_SHIM_CTMCTL_DACTQE BIT(0) 104 #define SDW_SHIM_CTMCTL_DODS BIT(1) 105 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) 106 107 /* Intel ALH Register definitions */ 108 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) 109 #define SDW_ALH_NUM_STREAMS 64 110 111 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 112 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) 113 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) 114 115 /********************************************************************* 116 * ACE2.x definitions for SHIM registers - only accessible when the 117 * HDAudio extended link LCTL.SPA/CPA = 1. 118 *********************************************************************/ 119 /* x variable is link index */ 120 #define SDW_SHIM2_GENERIC_BASE(x) (0x00030000 + 0x8000 * (x)) 121 #define SDW_IP_BASE(x) (0x00030100 + 0x8000 * (x)) 122 #define SDW_SHIM2_VS_BASE(x) (0x00036000 + 0x8000 * (x)) 123 124 /* SHIM2 Generic Registers */ 125 /* Read-only capabilities */ 126 #define SDW_SHIM2_LECAP 0x00 127 #define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */ 128 #define SDW_SHIM2_LECAP_MLC GENMASK(3, 1) /* Number of Lanes */ 129 130 /* PCM Stream capabilities */ 131 #define SDW_SHIM2_PCMSCAP 0x10 132 #define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */ 133 #define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */ 134 #define SDW_SHIM2_PCMSCAP_BSS GENMASK(12, 8) /* Bidirectional streams */ 135 136 /* Read-only PCM Stream Channel Count, y variable is stream */ 137 #define SDW_SHIM2_PCMSYCHC(y) (0x14 + (0x4 * (y))) 138 #define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */ 139 140 /* PCM Stream Channel Map */ 141 #define SDW_SHIM2_PCMSYCHM(y) (0x16 + (0x4 * (y))) 142 #define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */ 143 #define SDW_SHIM2_PCMSYCHM_HCHAN GENMASK(7, 4) /* Lowest channel used by the FIFO port */ 144 #define SDW_SHIM2_PCMSYCHM_STRM GENMASK(13, 8) /* HDaudio stream tag */ 145 #define SDW_SHIM2_PCMSYCHM_DIR BIT(15) /* HDaudio stream direction */ 146 147 /* SHIM2 vendor-specific registers */ 148 #define SDW_SHIM2_INTEL_VS_LVSCTL 0x04 149 #define SDW_SHIM2_INTEL_VS_LVSCTL_FCG BIT(26) 150 #define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS GENMASK(29, 27) 151 #define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD BIT(30) 152 #define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD BIT(31) 153 154 #define SDW_SHIM2_MLCS_XTAL_CLK 0x0 155 #define SDW_SHIM2_MLCS_CARDINAL_CLK 0x1 156 #define SDW_SHIM2_MLCS_AUDIO_PLL_CLK 0x2 157 #define SDW_SHIM2_MLCS_MCLK_INPUT_CLK 0x3 158 #define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4 159 160 #define SDW_SHIM2_INTEL_VS_WAKEEN 0x08 161 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0) 162 163 #define SDW_SHIM2_INTEL_VS_WAKESTS 0x0A 164 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0) 165 166 #define SDW_SHIM2_INTEL_VS_IOCTL 0x0C 167 #define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0) 168 #define SDW_SHIM2_INTEL_VS_IOCTL_CO BIT(1) 169 #define SDW_SHIM2_INTEL_VS_IOCTL_COE BIT(2) 170 #define SDW_SHIM2_INTEL_VS_IOCTL_DO BIT(3) 171 #define SDW_SHIM2_INTEL_VS_IOCTL_DOE BIT(4) 172 #define SDW_SHIM2_INTEL_VS_IOCTL_BKE BIT(5) 173 #define SDW_SHIM2_INTEL_VS_IOCTL_WPDD BIT(6) 174 #define SDW_SHIM2_INTEL_VS_IOCTL_ODC BIT(7) 175 #define SDW_SHIM2_INTEL_VS_IOCTL_CIBD BIT(8) 176 #define SDW_SHIM2_INTEL_VS_IOCTL_DIBD BIT(9) 177 #define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD BIT(10) 178 179 #define SDW_SHIM2_INTEL_VS_ACTMCTL 0x0E 180 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0) 181 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS BIT(1) 182 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2) 183 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3) 184 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5) 185 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS BIT(6) 186 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS GENMASK(11, 7) 187 #define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2 GENMASK(13, 12) 188 #define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2 BIT(14) 189 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE BIT(15) 190 191 /** 192 * struct sdw_intel_stream_params_data: configuration passed during 193 * the @params_stream callback, e.g. for interaction with DSP 194 * firmware. 195 */ 196 struct sdw_intel_stream_params_data { 197 struct snd_pcm_substream *substream; 198 struct snd_soc_dai *dai; 199 struct snd_pcm_hw_params *hw_params; 200 int link_id; 201 int alh_stream_id; 202 }; 203 204 /** 205 * struct sdw_intel_stream_free_data: configuration passed during 206 * the @free_stream callback, e.g. for interaction with DSP 207 * firmware. 208 */ 209 struct sdw_intel_stream_free_data { 210 struct snd_pcm_substream *substream; 211 struct snd_soc_dai *dai; 212 int link_id; 213 }; 214 215 /** 216 * struct sdw_intel_ops: Intel audio driver callback ops 217 * 218 */ 219 struct sdw_intel_ops { 220 int (*params_stream)(struct device *dev, 221 struct sdw_intel_stream_params_data *params_data); 222 int (*free_stream)(struct device *dev, 223 struct sdw_intel_stream_free_data *free_data); 224 int (*trigger)(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai); 225 }; 226 227 /** 228 * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables 229 * @handle: ACPI controller handle 230 * @count: link count found with "sdw-master-count" or "sdw-manager-list" property 231 * @link_mask: bit-wise mask listing links enabled by BIOS menu 232 * 233 * this structure could be expanded to e.g. provide all the _ADR 234 * information in case the link_mask is not sufficient to identify 235 * platform capabilities. 236 */ 237 struct sdw_intel_acpi_info { 238 acpi_handle handle; 239 int count; 240 u32 link_mask; 241 }; 242 243 struct sdw_intel_link_dev; 244 245 /* Intel clock-stop/pm_runtime quirk definitions */ 246 247 /* 248 * Force the clock to remain on during pm_runtime suspend. This might 249 * be needed if Slave devices do not have an alternate clock source or 250 * if the latency requirements are very strict. 251 */ 252 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0) 253 254 /* 255 * Stop the bus during pm_runtime suspend. If set, a complete bus 256 * reset and re-enumeration will be performed when the bus 257 * restarts. This mode shall not be used if Slave devices can generate 258 * in-band wakes. 259 */ 260 #define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1) 261 262 /* 263 * Stop the bus during pm_suspend if Slaves are not wake capable 264 * (e.g. speaker amplifiers). The clock-stop mode is typically 265 * slightly higher power than when the IP is completely powered-off. 266 */ 267 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2) 268 269 /* 270 * Require a bus reset (and complete re-enumeration) when exiting 271 * clock stop modes. This may be needed if the controller power was 272 * turned off and all context lost. This quirk shall not be used if a 273 * Slave device needs to remain enumerated and keep its context, 274 * e.g. to provide the reasons for the wake, report acoustic events or 275 * pass a history buffer. 276 */ 277 #define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3) 278 279 struct hdac_bus; 280 281 /** 282 * struct sdw_intel_ctx - context allocated by the controller 283 * driver probe 284 * @count: link count 285 * @mmio_base: mmio base of SoundWire registers, only used to check 286 * hardware capabilities after all power dependencies are settled. 287 * @link_mask: bit-wise mask listing SoundWire links reported by the 288 * Controller 289 * @num_slaves: total number of devices exposed across all enabled links 290 * @handle: ACPI parent handle 291 * @ldev: information for each link (controller-specific and kept 292 * opaque here) 293 * @ids: array of slave_id, representing Slaves exposed across all enabled 294 * links 295 * @link_list: list to handle interrupts across all links 296 * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers. 297 * @shim_mask: flags to track initialization of SHIM shared registers 298 * @shim_base: sdw shim base. 299 * @alh_base: sdw alh base. 300 */ 301 struct sdw_intel_ctx { 302 int count; 303 void __iomem *mmio_base; 304 u32 link_mask; 305 int num_slaves; 306 acpi_handle handle; 307 struct sdw_intel_link_dev **ldev; 308 struct sdw_extended_slave_id *ids; 309 struct list_head link_list; 310 struct mutex shim_lock; /* lock for access to shared SHIM registers */ 311 u32 shim_mask; 312 u32 shim_base; 313 u32 alh_base; 314 }; 315 316 /** 317 * struct sdw_intel_res - Soundwire Intel global resource structure, 318 * typically populated by the DSP driver 319 * 320 * @hw_ops: abstraction for platform ops 321 * @count: link count 322 * @mmio_base: mmio base of SoundWire registers 323 * @irq: interrupt number 324 * @handle: ACPI parent handle 325 * @parent: parent device 326 * @ops: callback ops 327 * @dev: device implementing hwparams and free callbacks 328 * @link_mask: bit-wise mask listing links selected by the DSP driver 329 * This mask may be a subset of the one reported by the controller since 330 * machine-specific quirks are handled in the DSP driver. 331 * @clock_stop_quirks: mask array of possible behaviors requested by the 332 * DSP driver. The quirks are common for all links for now. 333 * @shim_base: sdw shim base. 334 * @alh_base: sdw alh base. 335 * @ext: extended HDaudio link support 336 * @hbus: hdac_bus pointer, needed for power management 337 * @eml_lock: mutex protecting shared registers in the HDaudio multi-link 338 * space 339 */ 340 struct sdw_intel_res { 341 const struct sdw_intel_hw_ops *hw_ops; 342 int count; 343 void __iomem *mmio_base; 344 int irq; 345 acpi_handle handle; 346 struct device *parent; 347 const struct sdw_intel_ops *ops; 348 struct device *dev; 349 u32 link_mask; 350 u32 clock_stop_quirks; 351 u32 shim_base; 352 u32 alh_base; 353 bool ext; 354 struct hdac_bus *hbus; 355 struct mutex *eml_lock; 356 }; 357 358 /* 359 * On Intel platforms, the SoundWire IP has dependencies on power 360 * rails shared with the DSP, and the initialization steps are split 361 * in three. First an ACPI scan to check what the firmware describes 362 * in DSDT tables, then an allocation step (with no hardware 363 * configuration but with all the relevant devices created) and last 364 * the actual hardware configuration. The final stage is a global 365 * interrupt enable which is controlled by the DSP driver. Splitting 366 * these phases helps simplify the boot flow and make early decisions 367 * on e.g. which machine driver to select (I2S mode, HDaudio or 368 * SoundWire). 369 */ 370 int sdw_intel_acpi_scan(acpi_handle *parent_handle, 371 struct sdw_intel_acpi_info *info); 372 373 void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx); 374 375 struct sdw_intel_ctx * 376 sdw_intel_probe(struct sdw_intel_res *res); 377 378 int sdw_intel_startup(struct sdw_intel_ctx *ctx); 379 380 void sdw_intel_exit(struct sdw_intel_ctx *ctx); 381 382 irqreturn_t sdw_intel_thread(int irq, void *dev_id); 383 384 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1) 385 386 struct sdw_intel; 387 388 /* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms. 389 * @debugfs_init: initialize all debugfs capabilities 390 * @debugfs_exit: close and cleanup debugfs capabilities 391 * @get_link_count: fetch link count from hardware registers 392 * @register_dai: read all PDI information and register DAIs 393 * @check_clock_stop: throw error message if clock is not stopped. 394 * @start_bus: normal start 395 * @start_bus_after_reset: start after reset 396 * @start_bus_after_clock_stop: start after mode0 clock stop 397 * @stop_bus: stop all bus 398 * @link_power_up: power-up using chip-specific helpers 399 * @link_power_down: power-down with chip-specific helpers 400 * @shim_check_wake: check if a wake was received 401 * @shim_wake: enable/disable in-band wake management 402 * @pre_bank_switch: helper for bus management 403 * @post_bank_switch: helper for bus management 404 * @sync_arm: helper for multi-link synchronization 405 * @sync_go_unlocked: helper for multi-link synchronization - 406 * shim_lock is assumed to be locked at higher level 407 * @sync_go: helper for multi-link synchronization 408 * @sync_check_cmdsync_unlocked: helper for multi-link synchronization 409 * and bank switch - shim_lock is assumed to be locked at higher level 410 * @program_sdi: helper for codec command/control based on dev_num 411 */ 412 struct sdw_intel_hw_ops { 413 void (*debugfs_init)(struct sdw_intel *sdw); 414 void (*debugfs_exit)(struct sdw_intel *sdw); 415 416 int (*get_link_count)(struct sdw_intel *sdw); 417 418 int (*register_dai)(struct sdw_intel *sdw); 419 420 void (*check_clock_stop)(struct sdw_intel *sdw); 421 int (*start_bus)(struct sdw_intel *sdw); 422 int (*start_bus_after_reset)(struct sdw_intel *sdw); 423 int (*start_bus_after_clock_stop)(struct sdw_intel *sdw); 424 int (*stop_bus)(struct sdw_intel *sdw, bool clock_stop); 425 426 int (*link_power_up)(struct sdw_intel *sdw); 427 int (*link_power_down)(struct sdw_intel *sdw); 428 429 int (*shim_check_wake)(struct sdw_intel *sdw); 430 void (*shim_wake)(struct sdw_intel *sdw, bool wake_enable); 431 432 int (*pre_bank_switch)(struct sdw_intel *sdw); 433 int (*post_bank_switch)(struct sdw_intel *sdw); 434 435 void (*sync_arm)(struct sdw_intel *sdw); 436 int (*sync_go_unlocked)(struct sdw_intel *sdw); 437 int (*sync_go)(struct sdw_intel *sdw); 438 bool (*sync_check_cmdsync_unlocked)(struct sdw_intel *sdw); 439 440 void (*program_sdi)(struct sdw_intel *sdw, int dev_num); 441 }; 442 443 extern const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops; 444 extern const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops; 445 446 /* 447 * IDA min selected to allow for 5 unconstrained devices per link, 448 * and 6 system-unique Device Numbers for wake-capable devices. 449 */ 450 451 #define SDW_INTEL_DEV_NUM_IDA_MIN 6 452 453 /* 454 * Max number of links supported in hardware 455 */ 456 #define SDW_INTEL_MAX_LINKS 5 457 458 #endif 459