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Searched refs:SDMA1 (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dsdma_v4_0.c150 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
151 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
152 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
153 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
154 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
155 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
156 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
157 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
159 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
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Damdgpu_amdkfd_gfx_v12.c89 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
Damdgpu_amdkfd_arcturus.c85 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
Dsoc24.c122 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
Damdgpu_amdkfd_gfx_v11.c138 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
Dsoc21.c264 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
Dnv.c343 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
Damdgpu_amdkfd_gfx_v10.c173 SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
Dsdma_v2_4.c280 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
Damdgpu_amdkfd_gfx_v9.c198 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
Dsoc15.c366 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
Dsdma_v3_0.c456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
/linux-6.12.1/drivers/gpu/drm/radeon/
Dcik_sdma.c179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
Dcikd.h861 #define SDMA1 (1 << 11) macro