Searched refs:Reset (Results 1 – 25 of 278) sorted by relevance
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6 bool "Reset Controller Support"9 Generic Reset Controller support.19 tristate "Altera Arria10 System Resource Reset"26 bool "AR71xx Reset Driver" if COMPILE_TEST33 bool "AXS10x Reset Driver" if COMPILE_TEST39 bool "BCM6345 Reset Controller"46 tristate "Berlin Reset Driver"93 bool "Synopsys HSDK Reset Driver"100 tristate "i.MX7/8 Reset Driver"109 tristate "i.MX8MP AudioMix Reset Driver"[all …]
44 in1_reset_history Reset input voltage history.50 in2_reset_history Reset output voltage history.55 temp1_reset_history Reset temperature history.60 curr1_reset_history Reset input current history.66 curr2_reset_history Reset output current history.
51 reset_count RO Reset count of the SoC53 reset_reason RO Reset reason for the last reset
281 in1_reset_history Reset input voltage history.318 in[N]_reset_history Reset output voltage history.371 temp[N]_reset_history Reset temperature history.409 curr1_reset_history Reset input current history.448 curr[N]_reset_history Reset output current history.
4 Reset controller API10 Reset controllers are central units that control the reset signals to multiple29 Reset line34 Reset control44 Reset controller49 Reset consumer146 Reset control arrays155 Reset controller driver interface178 Reset consumer API181 Reset consumers can control a reset line using an opaque reset control handle,[all …]
1 NXP LPC1850 Reset Generation Unit (RGU)18 Reset Peripheral64 Reset provider example:73 Reset consumer example:
1 Xilinx Zynq Reset Manager14 The Zynq Reset Manager needs to be a childnode of the SLCR.24 Reset outputs:
1 TI SysCon Reset Controller12 A SysCon Reset Controller node defines a device that uses a syscon node16 SysCon Reset Controller Node49 SysCon Reset Consumer Nodes
1 = Reset Signal Device Tree Bindings =4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole32 = Reset providers =45 = Reset consumers =
1 STMicroelectronics STM32 Peripheral Reset Controller
1 STMicroelectronics STM32MP1 Peripheral Reset Controller
3 tristate "Hi3660 Reset Driver"10 tristate "Hi6220 Reset Driver"
7 bool "StarFive JH7100 Reset Driver"15 bool "StarFive JH7110 Reset Driver"
13 bool "Arm Generic Diagnostic Dump and Reset Device Interface"16 Arm Generic Diagnostic Dump and Reset Device Interface (AGDI) is
5 Reading returns the current Degradation of Signal Reset Maximum19 Reading returns the current Degradation of Signal Reset Minimum
32 Write to this node to issue "Reset" for Link Layer Validation58 Write to this node to issue "Warm Reset" for Link Layer Validation
48 * "CtlResCt" : Controller Reset Count49 * "CtlResTm" : Controller Reset Elapsed Time
35 bool "Loongson-2K1000 Reset Controller"38 Loongson-2K1000 Reset Controller driver.
26 - Permanently enable the eMMC H/W Reset feature.27 - Permanently disable the eMMC H/W Reset feature.
223 Reset enumerator362 next_state = Reset; in do_name()433 next_state = Reset; in do_symlink()445 [Reset] = do_reset,474 state = Reset; in flush_buffer()534 if (state != Reset) in unpack_to_rootfs()
20 a10sr_rst Reset Controller30 Arria10 Peripheral PHY Reset
3 bool "Tegra BPMP Reset Driver" if COMPILE_TEST
5 bool "STIH407 Reset Driver" if COMPILE_TEST
7 SoC. Each watchdog timer event input is connected to the Reset Mux8 block. The Reset Mux block can be configured to cause reset or not.
19 Supports the Power Reset Clock interface (PRCI) IP block found in