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Searched refs:R_BCM1480_IMR_MAILBOX_0_CLR_CPU (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/arch/mips/sibyte/bcm1480/
Dsmp.c33 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
34 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
35 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
36 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
Dirq.c279 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); in arch_init_irq()
/linux-6.12.1/arch/mips/include/asm/sibyte/
Dbcm1480_regs.h377 #define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 macro