| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | si.c | 5189 orig = data = RREG32(RLC_CNTL); in si_halt_rlc()
5193 WREG32(RLC_CNTL, data); in si_halt_rlc()
5205 tmp = RREG32(RLC_CNTL); in si_update_rlc()
5207 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5801 WREG32(RLC_CNTL, 0); in si_rlc_stop()
5810 WREG32(RLC_CNTL, RLC_ENABLE); in si_rlc_start()
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| D | r600.c | 1704 WREG32(RLC_CNTL, 0); in r600_gpu_soft_reset()
1836 WREG32(RLC_CNTL, 0); in r600_gpu_pci_config_reset()
3543 WREG32(RLC_CNTL, 0); in r600_rlc_stop()
3548 WREG32(RLC_CNTL, RLC_ENABLE); in r600_rlc_start()
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| D | sid.h | 1300 #define RLC_CNTL 0xC300 macro
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| D | cik.c | 5810 tmp = RREG32(RLC_CNTL); in cik_update_rlc()
5812 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
5819 orig = data = RREG32(RLC_CNTL); in cik_halt_rlc()
5825 WREG32(RLC_CNTL, data); in cik_halt_rlc()
5877 WREG32(RLC_CNTL, 0); in cik_rlc_stop()
5893 WREG32(RLC_CNTL, RLC_ENABLE); in cik_rlc_start()
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| D | cikd.h | 1393 #define RLC_CNTL 0xC300 macro
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| D | evergreend.h | 384 #define RLC_CNTL 0x3f00 macro
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| D | r600d.h | 685 #define RLC_CNTL 0x3f00 macro
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| D | evergreen.c | 4377 WREG32(RLC_CNTL, mask); in evergreen_rlc_start()
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | sid.h | 1328 #define RLC_CNTL 0x30C0 macro
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| D | gfx_v12_0.c | 1781 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v12_0_rlc_stop()
1822 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v12_0_rlc_start()
3746 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v12_0_is_rlc_enabled()
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| D | gfx_v11_0.c | 2068 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v11_0_rlc_stop()
2109 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
5046 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v11_0_is_rlc_enabled()
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| D | gfx_v9_4_3.c | 1490 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_stop()
1526 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_start()
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| D | gfx_v8_0.c | 4049 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
4066 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v8_0_rlc_start()
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| D | gfx_v9_0.c | 3063 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v9_0_rlc_stop()
3082 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v9_0_rlc_start()
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| D | gfx_v10_0.c | 5318 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v10_0_rlc_stop()
5361 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v10_0_rlc_start()
7751 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v10_0_is_rlc_enabled()
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