Searched refs:RING_HWS_PGA (Results 1 – 13 of 13) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/xe/ |
| D | xe_execlist.c | 79 xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base), in __start_lrc()
81 xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base)); in __start_lrc()
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| D | xe_hw_engine.c | 331 xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0), in xe_hw_engine_enable_ring()
935 snapshot->reg.ring_hws_pga = xe_hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)); in xe_hw_engine_snapshot_capture()
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| D | xe_guc_ads.c | 584 { .reg = RING_HWS_PGA(hwe->mmio_base), }, in guc_mmio_regset_write()
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| /linux-6.12.1/drivers/gpu/drm/xe/regs/ |
| D | xe_engine_regs.h | 74 #define RING_HWS_PGA(base) XE_REG((base) + 0x80) macro
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| /linux-6.12.1/drivers/gpu/drm/i915/gt/ |
| D | intel_engine_regs.h | 66 #define RING_HWS_PGA(base) _MMIO((base) + 0x80) macro
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| D | intel_ring_submission.c | 109 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
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| D | intel_execlists_submission.c | 2948 RING_HWS_PGA, in enable_execlists()
2950 ENGINE_POSTING_READ(engine, RING_HWS_PGA); in enable_execlists()
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| /linux-6.12.1/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_ads.c | 392 ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false); in guc_mmio_regset_init()
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| D | intel_guc_capture.c | 73 { RING_HWS_PGA(0), 0, 0, "HWS" }, \
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| D | intel_guc_submission.c | 4342 RING_HWS_PGA, in setup_hwsp()
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | intel_gvt_mmio_table.c | 821 MMIO_RING_D(RING_HWS_PGA); in iterate_bdw_plus_mmio()
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| D | i915_gpu_error.c | 1329 mmio = RING_HWS_PGA(engine->mmio_base); in engine_record_registers()
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| /linux-6.12.1/drivers/gpu/drm/i915/gvt/ |
| D | handlers.c | 2542 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); in init_bdw_mmio_info()
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