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Searched refs:RING_CTL (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_ring_submission.c182 ENGINE_WRITE_FW(engine, RING_CTL, 0); in stop_ring()
183 ENGINE_POSTING_READ(engine, RING_CTL); in stop_ring()
237 ENGINE_WRITE_FW(engine, RING_CTL, in xcs_resume()
242 RING_CTL(engine->mmio_base), in xcs_resume()
266 ENGINE_READ(engine, RING_CTL), in xcs_resume()
267 ENGINE_READ(engine, RING_CTL) & RING_VALID, in xcs_resume()
335 ENGINE_READ_FW(engine, RING_CTL), in reset_prepare()
344 ENGINE_READ_FW(engine, RING_CTL), in reset_prepare()
Dintel_engine_regs.h19 #define RING_CTL(base) _MMIO((base) + 0x3c) macro
Dintel_gt.c146 intel_uncore_write(uncore, RING_CTL(base), 0); in init_unused_ring()
Dintel_engine_cs.c2099 ENGINE_READ(engine, RING_CTL), in intel_engine_print_registers()
2100 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); in intel_engine_print_registers()
Dselftest_lrc.c309 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
Dintel_execlists_submission.c1979 ENGINE_READ(engine, RING_CTL), in process_csb()
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_engine_regs.h54 #define RING_CTL(base) XE_REG((base) + 0x3c) macro
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_hw_engine.c950 snapshot->reg.ring_ctl = xe_hw_engine_mmio_read32(hwe, RING_CTL(0)); in xe_hw_engine_snapshot_capture()
/linux-6.12.1/drivers/gpu/drm/i915/
Di915_pmu.c365 val = ENGINE_READ_FW(engine, RING_CTL); in engine_sample()
Dintel_gvt_mmio_table.c86 MMIO_RING_D(RING_CTL); in iterate_generic_mmio()
Di915_gpu_error.c1300 ee->ctl = ENGINE_READ(engine, RING_CTL); in engine_record_registers()
/linux-6.12.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_capture.c70 { RING_CTL(0), 0, 0, "CTL" }, \
/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Dhandlers.c2224 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()