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Searched refs:RG_P0_TO_P1_WIDTH (Results 1 – 1 of 1) sorted by relevance

/linux-6.12.1/drivers/phy/ralink/
Dphy-mt7621-pci.c22 #define RG_P0_TO_P1_WIDTH 0x100 macro
110 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH, in mt7621_bypass_pipe_rst()
112 mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH, in mt7621_bypass_pipe_rst()
138 mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH, in mt7621_set_phy_for_ssc()
229 mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH, in mt7621_pci_phy_power_on()
245 mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH, in mt7621_pci_phy_power_off()