Searched refs:RG_HDMITXPLL_RESERVE_BIT1_0 (Results 1 – 2 of 2) sorted by relevance
76 #define RG_HDMITXPLL_RESERVE_BIT1_0 GENMASK(1, 0) macro
180 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2); in mtk_hdmi_pll_set_hw()