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Searched refs:REG_TEST_FLD (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/accel/ivpu/
Divpu_hw_btrs.c138 if (!REG_TEST_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, VALID, fuse)) { in read_tile_config_fuse()
573 return REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, val) && in ivpu_hw_btrs_is_idle()
574 REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, val); in ivpu_hw_btrs_is_idle()
578 return REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, val) && in ivpu_hw_btrs_is_idle()
579 REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, val); in ivpu_hw_btrs_is_idle()
600 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status)) in ivpu_hw_btrs_irq_handler_mtl()
604 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, status)) { in ivpu_hw_btrs_irq_handler_mtl()
610 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, status)) { in ivpu_hw_btrs_irq_handler_mtl()
646 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, status)) { in ivpu_hw_btrs_irq_handler_lnl()
652 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status)) in ivpu_hw_btrs_irq_handler_lnl()
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Divpu_hw_ip.c1009 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg)) in diagnose_failure_37xx()
1012 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg)) in diagnose_failure_37xx()
1015 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg)) in diagnose_failure_37xx()
1026 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg)) in diagnose_failure_40xx()
1029 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg)) in diagnose_failure_40xx()
1032 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg)) in diagnose_failure_40xx()
1081 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
1084 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
1087 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
1090 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
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Divpu_mmu.c945 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_ABT, active)) in ivpu_mmu_irq_gerr_handler()
948 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_PRIQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
951 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_EVTQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
954 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_CMDQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
957 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
960 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
963 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, CMDQ, active)) in ivpu_mmu_irq_gerr_handler()
Divpu_hw_reg_io.h45 #define REG_TEST_FLD(REG, FLD, val) \ macro