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Searched refs:REG_SET_FLD (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/accel/ivpu/
Divpu_hw_ip.c78 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in host_ss_rst_clr()
79 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in host_ss_rst_clr()
80 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in host_ss_rst_clr()
236 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); in idle_gen_drive_37xx()
248 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
297 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); in pwr_island_trickle_drive_37xx()
309 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); in pwr_island_trickle_drive_40xx()
324 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); in pwr_island_drive_37xx()
339 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); in pwr_island_drive_40xx()
375 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in pwr_island_isolation_drive_37xx()
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Divpu_hw_btrs.c245 val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val); in wp_request_mtl()
269 val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val); in wp_request_lnl()
386 val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val); in d0i3_drive_mtl()
411 val = REG_SET_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val); in d0i3_drive_lnl()
492 val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, val); in ip_reset_mtl()
516 val = REG_SET_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, val); in ip_reset_lnl()
544 val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val); in ivpu_hw_btrs_profiling_freq_reg_set_lnl()
559 val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, DISABLE_CLK_RELINQUISH, val); in ivpu_hw_btrs_clock_relinquish_disable_lnl()
Divpu_hw_reg_io.h41 #define REG_SET_FLD(REG, FLD, val) \ macro