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Searched refs:REG_SET_4 (Results 1 – 25 of 29) sorted by relevance

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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
Ddcn20_dpp_cm.c660 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp20_program_shaper_luta_settings()
667 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp20_program_shaper_luta_settings()
674 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp20_program_shaper_luta_settings()
681 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp20_program_shaper_luta_settings()
688 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp20_program_shaper_luta_settings()
695 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp20_program_shaper_luta_settings()
702 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp20_program_shaper_luta_settings()
709 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp20_program_shaper_luta_settings()
716 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp20_program_shaper_luta_settings()
723 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, in dpp20_program_shaper_luta_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
Ddcn32_mpc.c373 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
380 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
387 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
394 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
401 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
408 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
415 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
422 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
430 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
437 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
Ddcn30_dpp.c925 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp3_program_shaper_luta_settings()
932 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp3_program_shaper_luta_settings()
939 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp3_program_shaper_luta_settings()
946 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp3_program_shaper_luta_settings()
953 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp3_program_shaper_luta_settings()
960 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp3_program_shaper_luta_settings()
967 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp3_program_shaper_luta_settings()
974 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp3_program_shaper_luta_settings()
981 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp3_program_shaper_luta_settings()
988 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, in dpp3_program_shaper_luta_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
Ddcn30_mpc.c499 REG_SET_4(SHAPER_RAMA_REGION_0_1[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
506 REG_SET_4(SHAPER_RAMA_REGION_2_3[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
513 REG_SET_4(SHAPER_RAMA_REGION_4_5[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
520 REG_SET_4(SHAPER_RAMA_REGION_6_7[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
527 REG_SET_4(SHAPER_RAMA_REGION_8_9[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
534 REG_SET_4(SHAPER_RAMA_REGION_10_11[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
541 REG_SET_4(SHAPER_RAMA_REGION_12_13[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
548 REG_SET_4(SHAPER_RAMA_REGION_14_15[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
556 REG_SET_4(SHAPER_RAMA_REGION_16_17[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
563 REG_SET_4(SHAPER_RAMA_REGION_18_19[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
Ddcn31_hpo_dp_stream_encoder.c378 REG_SET_4(DP_SYM32_ENC_VID_MSA0, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
384 REG_SET_4(DP_SYM32_ENC_VID_MSA1, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
390 REG_SET_4(DP_SYM32_ENC_VID_MSA2, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
396 REG_SET_4(DP_SYM32_ENC_VID_MSA3, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
402 REG_SET_4(DP_SYM32_ENC_VID_MSA4, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
408 REG_SET_4(DP_SYM32_ENC_VID_MSA5, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
414 REG_SET_4(DP_SYM32_ENC_VID_MSA6, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
420 REG_SET_4(DP_SYM32_ENC_VID_MSA7, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
426 REG_SET_4(DP_SYM32_ENC_VID_MSA8, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/
Ddcn30_dio_stream_encoder.c221 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
231 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
241 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
251 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
261 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
271 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
281 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn20/
Ddcn20_stream_encoder.c170 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
180 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
190 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
200 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
247 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc2_update_gsp7_128_info_packet()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
Ddcn401_dsc.c251 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, in dsc_write_to_registers()
264 REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0, in dsc_write_to_registers()
333 REG_SET_4(DSCC_PPS_CONFIG12, 0, in dsc_write_to_registers()
339 REG_SET_4(DSCC_PPS_CONFIG13, 0, in dsc_write_to_registers()
345 REG_SET_4(DSCC_PPS_CONFIG14, 0, in dsc_write_to_registers()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.c249 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in program_multi_taps_filter()
1501 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, in regamma_config_regions_and_segments()
1508 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, in regamma_config_regions_and_segments()
1515 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, in regamma_config_regions_and_segments()
1522 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, in regamma_config_regions_and_segments()
1529 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, in regamma_config_regions_and_segments()
1536 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, in regamma_config_regions_and_segments()
1543 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, in regamma_config_regions_and_segments()
1550 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, in regamma_config_regions_and_segments()
Ddce_stream_encoder.c106 REG_SET_4(AFMT_GENERIC_HDR, 0, in dce110_update_generic_info_packet()
484 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in dce110_stream_encoder_dp_set_stream_attribute()
Ddce_i2c_hw.c224 value = REG_SET_4(DC_I2C_DATA, 0, in process_transaction()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
Ddcn20_dsc.c611 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, in dsc_write_to_registers()
624 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, in dsc_write_to_registers()
693 REG_SET_4(DSCC_PPS_CONFIG12, 0, in dsc_write_to_registers()
699 REG_SET_4(DSCC_PPS_CONFIG13, 0, in dsc_write_to_registers()
705 REG_SET_4(DSCC_PPS_CONFIG14, 0, in dsc_write_to_registers()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_vpg.c88 REG_SET_4(VPG_GENERIC_PACKET_DATA, 0, in vpg3_update_generic_info_packet()
Ddcn30_cm_common.c92 REG_SET_4(reg_region_cur, 0, in cm_helper_program_gamcor_xfer_func()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
Ddcn201_hubp.c74 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp201_program_requestor()
/linux-6.12.1/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.h76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
Ddcn401_dpp_dscl.c266 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in dpp401_dscl_set_scaler_filter()
711 REG_SET_4(DSCL_EASF_V_BF_FINAL_MAX_MIN, 0, in dpp401_dscl_program_easf_v()
816 REG_SET_4(DSCL_EASF_H_BF_FINAL_MAX_MIN, 0, in dpp401_dscl_program_easf_h()
1175 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp401_dscl_set_scaler_manual_scale()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/
Ddcn10_stream_encoder.c96 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_update_generic_info_packet()
447 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in enc1_stream_encoder_dp_set_stream_attribute()
825 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_stream_encoder_send_immediate_sdp_message()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
Ddcn10_dpp_dscl.c264 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in dpp1_dscl_set_scaler_filter()
688 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_manual_scale()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn401/
Ddcn401_optc.c128 REG_SET_4(OPTC_DATA_SOURCE_SELECT, 0, in optc401_set_odm_combine()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dwb_scl.c709 REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0, in wbscl_set_scaler_filter()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn10/
Ddcn10_optc.c807 REG_SET_4(OTG_TRIGA_CNTL, 0, in optc1_enable_crtc_reset()
1210 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, in optc1_set_test_pattern()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn401/
Ddcn401_dio_stream_encoder.c688 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in enc401_stream_encoder_dp_set_stream_attribute()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_cm_common.c135 REG_SET_4(reg_region_cur, 0, in cm_helper_program_xfer_func()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
Ddcn401_hubp.c177 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp401_program_requestor()

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