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Searched refs:REG_SET_2 (Results 1 – 25 of 67) sorted by relevance

123

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
Ddcn401_dpp_dscl.c204 REG_SET_2(LB_DATA_FORMAT, 0, in dpp401_dscl_set_lb()
212 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp401_dscl_set_lb()
382 REG_SET_2(SCL_MODE, scl_mode, in dpp401_dscl_set_scl_filter()
544 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp401_dscl_set_manual_ratio_init()
548 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, in dpp401_dscl_set_manual_ratio_init()
552 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in dpp401_dscl_set_manual_ratio_init()
557 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, in dpp401_dscl_set_manual_ratio_init()
562 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, in dpp401_dscl_set_manual_ratio_init()
567 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, in dpp401_dscl_set_manual_ratio_init()
590 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp401_dscl_set_manual_ratio_init()
[all …]
Ddcn401_dpp.c75 REG_SET_2(FORMAT_CONTROL, 0, in dpp401_dpp_setup()
190 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp401_dpp_setup()
195 REG_SET_2(PRE_DEALPHA, 0, in dpp401_dpp_setup()
198 REG_SET_2(PRE_REALPHA, 0, in dpp401_dpp_setup()
/linux-6.12.1/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn30.c105 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn30_backdoor_load()
114 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn30_backdoor_load()
140 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
155 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
166 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
172 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
183 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
189 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
199 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
Ddmub_dcn20.c172 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn20_backdoor_load()
181 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn20_backdoor_load()
209 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
224 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
236 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
242 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
253 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
259 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
269 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
Ddmub_dcn35.c186 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn35_backdoor_load()
195 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn35_backdoor_load()
214 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn35_backdoor_load_zfb_mode()
221 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn35_backdoor_load_zfb_mode()
242 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn35_setup_windows()
251 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn35_setup_windows()
260 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn35_setup_windows()
266 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn35_setup_windows()
276 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn35_setup_windows()
284 REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0, in dmub_dcn35_setup_windows()
Ddmub_dcn401.c141 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn401_backdoor_load()
150 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn401_backdoor_load()
171 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn401_backdoor_load_zfb_mode()
180 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn401_backdoor_load_zfb_mode()
203 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn401_setup_windows()
212 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn401_setup_windows()
221 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn401_setup_windows()
227 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn401_setup_windows()
237 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn401_setup_windows()
245 REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0, in dmub_dcn401_setup_windows()
Ddmub_dcn32.c167 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn32_backdoor_load()
176 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn32_backdoor_load()
197 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn32_backdoor_load_zfb_mode()
206 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn32_backdoor_load_zfb_mode()
229 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn32_setup_windows()
238 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn32_setup_windows()
247 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn32_setup_windows()
253 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn32_setup_windows()
263 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn32_setup_windows()
Ddmub_dcn31.c168 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn31_backdoor_load()
177 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn31_backdoor_load()
200 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows()
209 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows()
218 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows()
224 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows()
234 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/opp/dcn20/
Ddcn20_opp.c93 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator()
98 REG_SET_2(DPG_OFFSET_SEGMENT, 0, in opp2_set_disp_pattern_generator()
172 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_set_disp_pattern_generator()
175 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_set_disp_pattern_generator()
178 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_set_disp_pattern_generator()
283 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator()
300 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_program_dpg_dimensions()
313 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_dpg_set_blank_color()
316 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_dpg_set_blank_color()
319 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_dpg_set_blank_color()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_opp.c367 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
375 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
380 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
385 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
391 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
396 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, in dce110_opp_set_clamping()
400 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, in dce110_opp_set_clamping()
404 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, in dce110_opp_set_clamping()
427 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping()
435 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping()
[all …]
Ddce_transform.c131 REG_SET_2(SCL_TAP_CONTROL, 0, in setup_scaling_configuration()
164 REG_SET_2(SCL_TAP_CONTROL, 0, in dce60_setup_scaling_configuration()
199 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, in program_overscan()
202 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, in program_overscan()
266 REG_SET_2(VIEWPORT_START, 0, in program_viewport()
270 REG_SET_2(VIEWPORT_SIZE, 0, in program_viewport()
350 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in program_scl_ratios_inits()
354 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in program_scl_ratios_inits()
374 REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0, in dce60_program_scl_ratios_inits()
379 REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0, in dce60_program_scl_ratios_inits()
[all …]
Ddce_ipp.c55 REG_SET_2(CUR_POSITION, 0, in dce_ipp_cursor_set_position()
59 REG_SET_2(CUR_HOT_SPOT, 0, in dce_ipp_cursor_set_position()
117 REG_SET_2(CUR_SIZE, 0, in dce_ipp_cursor_set_attributes()
147 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, in dce_ipp_program_prescale()
151 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, in dce_ipp_program_prescale()
155 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, in dce_ipp_program_prescale()
242 REG_SET_2(DEGAMMA_CONTROL, 0, in dce60_ipp_set_degamma()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
Ddcn10_dpp_dscl.c202 REG_SET_2(LB_DATA_FORMAT, 0, in dpp1_dscl_set_lb()
210 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb()
368 REG_SET_2(SCL_MODE, scl_mode, in dpp1_dscl_set_scl_filter()
533 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
539 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, in dpp1_dscl_set_manual_ratio_init()
545 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
554 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, in dpp1_dscl_set_manual_ratio_init()
561 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, in dpp1_dscl_set_manual_ratio_init()
570 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, in dpp1_dscl_set_manual_ratio_init()
590 REG_SET_2(RECOUT_START, 0, in dpp1_dscl_set_recout()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
Ddcn401_hubp.c208 REG_SET_2(BLANK_OFFSET_0, 0, in hubp401_program_deadline()
218 REG_SET_2(DST_AFTER_SCALER, 0, in hubp401_program_deadline()
243 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp401_program_deadline()
265 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp401_program_deadline()
317 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp401_setup_interdependent()
324 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp401_setup_interdependent()
328 REG_SET_2(FLIP_PARAMETERS_0, 0, in hubp401_setup_interdependent()
341 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp401_setup_interdependent()
354 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp401_setup_interdependent()
594 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, in hubp401_set_viewport()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
Ddcn10_hubp.c594 REG_SET_2(BLANK_OFFSET_0, 0, in hubp1_program_deadline()
604 REG_SET_2(DST_AFTER_SCALER, 0, in hubp1_program_deadline()
629 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp1_program_deadline()
651 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp1_program_deadline()
696 REG_SET_2(PREFETCH_SETTINS, 0, in hubp1_setup_interdependent()
703 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp1_setup_interdependent()
713 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp1_setup_interdependent()
726 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp1_setup_interdependent()
774 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_system_aperture_settings()
814 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_context0_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/
Ddcn21_hubbub.c157 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub21_program_urgent_watermarks()
202 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub21_program_urgent_watermarks()
247 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub21_program_urgent_watermarks()
292 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub21_program_urgent_watermarks()
353 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks()
370 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks()
388 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks()
405 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks()
423 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks()
440 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
Ddcn30_dpp.c199 REG_SET_2(PRE_DEGAM, 0, in dpp3_set_pre_degam()
225 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
344 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp3_cnv_setup()
349 REG_SET_2(PRE_DEALPHA, 0, in dpp3_cnv_setup()
352 REG_SET_2(PRE_REALPHA, 0, in dpp3_cnv_setup()
902 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp3_program_shaper_luta_settings()
905 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp3_program_shaper_luta_settings()
908 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp3_program_shaper_luta_settings()
912 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp3_program_shaper_luta_settings()
916 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp3_program_shaper_luta_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
Ddcn20_dpp_cm.c637 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
640 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
643 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
647 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
651 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
655 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
787 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
790 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, in dpp20_program_shaper_lutb_settings()
793 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, in dpp20_program_shaper_lutb_settings()
797 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
Ddcn32_mpc.c352 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
355 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
358 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
362 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
365 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
368 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
502 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
505 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
508 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
512 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/
Ddcn30_dio_stream_encoder.c226 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
236 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
246 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
256 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
266 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
276 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
286 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
291 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
Ddcn401_dsc.c233 REG_SET_2(DSCCIF_CONFIG0, 0, in dsc_write_to_registers()
289 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
293 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
300 REG_SET_2(DSCC_PPS_CONFIG5, 0, in dsc_write_to_registers()
309 REG_SET_2(DSCC_PPS_CONFIG7, 0, in dsc_write_to_registers()
313 REG_SET_2(DSCC_PPS_CONFIG8, 0, in dsc_write_to_registers()
317 REG_SET_2(DSCC_PPS_CONFIG9, 0, in dsc_write_to_registers()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
Ddcn30_mpc.c478 REG_SET_2(SHAPER_RAMA_START_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
481 REG_SET_2(SHAPER_RAMA_START_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
484 REG_SET_2(SHAPER_RAMA_START_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
488 REG_SET_2(SHAPER_RAMA_END_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
491 REG_SET_2(SHAPER_RAMA_END_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
494 REG_SET_2(SHAPER_RAMA_END_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
627 REG_SET_2(SHAPER_RAMB_START_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
630 REG_SET_2(SHAPER_RAMB_START_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
633 REG_SET_2(SHAPER_RAMB_START_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
637 REG_SET_2(SHAPER_RAMB_END_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_cm_common.c56 REG_SET_2(cur_csc_reg, 0, in cm_helper_program_color_matrices()
93 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_xfer_func()
96 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_xfer_func()
99 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_xfer_func()
112 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_xfer_func()
118 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_xfer_func()
124 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_xfer_func()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
Ddcn21_hubp.c195 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, in hubp21_set_viewport()
199 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, in hubp21_set_viewport()
204 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, in hubp21_set_viewport()
208 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, in hubp21_set_viewport()
213 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, in hubp21_set_viewport()
217 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, in hubp21_set_viewport()
221 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, in hubp21_set_viewport()
225 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, in hubp21_set_viewport()
248 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp21_set_vm_system_aperture_settings()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_cm_common.c51 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_gamcor_xfer_func()
54 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_gamcor_xfer_func()
57 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_gamcor_xfer_func()
75 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_gamcor_xfer_func()
78 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_gamcor_xfer_func()
81 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_gamcor_xfer_func()

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