Searched refs:REG_GENMASK8 (Results 1 – 3 of 3) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_cx0_phy_regs.h | 206 #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
207 #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
208 #define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)
213 #define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
217 #define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5)
230 #define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0)
252 #define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
308 #define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
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| D | intel_cx0_phy.c | 2879 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2881 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
2884 disables &= ~REG_GENMASK8(1, 0); in intel_cx0_program_phy_lane()
2885 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); in intel_cx0_program_phy_lane()
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | i915_reg_defs.h | 77 #define REG_GENMASK8(__high, __low) \ macro
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