Searched refs:REG_CSR_2L_TXPLL_REFIN_DIV (Results 1 – 2 of 2) sorted by relevance
647 airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_TXPLL_REFIN_DIV, in airoha_pcie_phy_txpll()656 airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_REFIN_DIV, in airoha_pcie_phy_txpll()678 airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_TXPLL_REFIN_DIV, in airoha_pcie_phy_txpll()703 airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_TXPLL_REFIN_DIV, in airoha_pcie_phy_txpll()
120 #define REG_CSR_2L_TXPLL_REFIN_DIV 0x006c macro