Searched refs:REG_CSR_2L_RX0_PHYCK_DIV (Results 1 – 2 of 2) sorted by relevance
204 #define REG_CSR_2L_RX0_PHYCK_DIV 0x0100 macro
493 airoha_phy_csr_2l_update_field(pcie_phy, REG_CSR_2L_RX0_PHYCK_DIV, in airoha_pcie_phy_init_rx()944 airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_RX0_PHYCK_DIV, in airoha_pcie_phy_set_rxflow()