| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 932 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
1104 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
2019 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); in vcn_v2_0_start_sriov()
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| D | uvd_v5_0.c | 422 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
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| D | vcn_v2_5.c | 968 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
1160 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1379 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
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| D | vcn_v3_0.c | 1090 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start_dpg_mode()
1277 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start()
1463 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); in vcn_v3_0_start_sriov()
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| D | uvd_v7_0.c | 918 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); in uvd_v7_0_sriov_start()
1085 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v7_0_start()
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| D | vcn_v1_0.c | 953 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode()
1111 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
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| D | uvd_v6_0.c | 838 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
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| D | sid.h | 1275 #define RB_BUFSZ(x) ((x) << 0) macro
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| D | gfx_v11_0.c | 3549 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3589 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3959 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_gfx_mqd_init()
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| D | gfx_v12_0.c | 2595 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_cp_gfx_resume()
2895 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_gfx_mqd_init()
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| D | gfx_v10_0.c | 6365 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6408 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6667 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_gfx_mqd_init()
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| D | gfx_v8_0.c | 4249 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
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| D | gfx_v9_0.c | 3337 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | rv770d.h | 350 #define RB_BUFSZ(x) ((x) << 0) macro
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| D | nid.h | 485 #define RB_BUFSZ(x) ((x) << 0) macro
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| D | sid.h | 1247 #define RB_BUFSZ(x) ((x) << 0) macro
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| D | cikd.h | 1303 #define RB_BUFSZ(x) ((x) << 0) macro
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| D | rv770.c | 1102 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in rv770_cp_load_microcode()
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| D | evergreend.h | 477 #define RB_BUFSZ(x) ((x) << 0) macro
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| D | r600d.h | 196 #define RB_BUFSZ(x) ((x) << 0) macro
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| D | r600.c | 2658 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in r600_cp_load_microcode()
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| D | evergreen.c | 2977 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in evergreen_cp_load_microcode()
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