| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 933 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_0_start_dpg_mode()
1105 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_0_start()
2020 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_0_start_sriov()
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| D | uvd_v5_0.c | 423 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v5_0_start()
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| D | vcn_v2_5.c | 969 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_5_start_dpg_mode()
1161 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_5_start()
1380 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_5_sriov_start()
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| D | vcn_v3_0.c | 1091 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start_dpg_mode()
1278 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start()
1464 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start_sriov()
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| D | vcn_v1_0.c | 954 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v1_0_start_spg_mode()
1112 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v1_0_start_dpg_mode()
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| D | uvd_v6_0.c | 839 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v6_0_start()
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| D | sid.h | 1276 #define RB_BLKSZ(x) ((x) << 8) macro
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| D | uvd_v7_0.c | 1086 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v7_0_start()
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| D | gfx_v11_0.c | 3550 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3590 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3960 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_gfx_mqd_init()
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| D | gfx_v12_0.c | 2596 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_cp_gfx_resume()
2896 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_gfx_mqd_init()
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| D | gfx_v10_0.c | 6366 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6409 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6668 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_gfx_mqd_init()
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| D | gfx_v8_0.c | 4250 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
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| D | gfx_v9_0.c | 3338 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | rv770d.h | 351 #define RB_BLKSZ(x) ((x) << 8) macro
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| D | nid.h | 486 #define RB_BLKSZ(x) ((x) << 8) macro
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| D | sid.h | 1248 #define RB_BLKSZ(x) ((x) << 8) macro
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| D | cikd.h | 1304 #define RB_BLKSZ(x) ((x) << 8) macro
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| D | rv770.c | 1102 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in rv770_cp_load_microcode()
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| D | evergreend.h | 478 #define RB_BLKSZ(x) ((x) << 8) macro
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| D | r600d.h | 197 #define RB_BLKSZ(x) ((x) << 8) macro
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| D | r600.c | 2658 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in r600_cp_load_microcode()
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| D | evergreen.c | 2977 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in evergreen_cp_load_microcode()
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