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Searched refs:RAP (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/net/ethernet/amd/
Dariadne.c247 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ in ariadne_interrupt()
382 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ in ariadne_interrupt()
387 lance->RAP, lance->RDP); in ariadne_interrupt()
403 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ in ariadne_open()
407 lance->RAP = CSR88; /* Chip ID */ in ariadne_open()
409 lance->RAP = CSR89; /* Chip ID */ in ariadne_open()
427 lance->RAP = CSR3; /* Interrupt Masks and Deferral Control */ in ariadne_open()
429 lance->RAP = CSR4; /* Test and Features Control */ in ariadne_open()
433 lance->RAP = CSR8; /* Logical Address Filter, LADRF[15:0] */ in ariadne_open()
435 lance->RAP = CSR9; /* Logical Address Filter, LADRF[31:16] */ in ariadne_open()
[all …]
Dsunlance.c273 #define RAP 0x02UL /* register address port */ macro
278 sbus_writew(LE_CSR0, __base + RAP); \
304 sbus_writew(LE_CSR1, lp->lregs + RAP); in load_csrs()
306 sbus_writew(LE_CSR2, lp->lregs + RAP); in load_csrs()
308 sbus_writew(LE_CSR3, lp->lregs + RAP); in load_csrs()
312 sbus_writew(LE_CSR0, lp->lregs + RAP); in load_csrs()
470 sbus_writew(LE_CSR0, lp->lregs + RAP); in init_restart_lance()
816 sbus_writew(LE_CSR0, lp->lregs + RAP); in lance_interrupt()
Dariadne.h47 volatile u_short RAP; /* Register Address Port */ member
/linux-6.12.1/Documentation/admin-guide/hw-vuln/
Dcross-thread-rsb.rst46 In affected processors, the return address predictor (RAP) is partitioned
48 16-entry RAP, but in 1T mode, the active thread uses a 32-entry RAP. Upon
49 transition between 1T/2T mode, the RAP contents are not modified but the RAP
69 context switch fills the RAP entries (referred to as the RSB in Linux) with safe
Dsrso.rst9 Buffer (BTB) and Return Address Predictor (RAP) in this case - and then
16 not actually a CALL) can create an entry in the RAP which may be used
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_kms.c1591 TA_FW_NAME(RAP), in amdgpu_debugfs_firmware_info_show()