Searched refs:R9A08G045_CLK_I (Results 1 – 3 of 3) sorted by relevance
11 #define R9A08G045_CLK_I 0 macro
159 DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8,
27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;