Searched refs:R9A07G043_CLK_I (Results 1 – 4 of 4) sorted by relevance
11 #define R9A07G043_CLK_I 0 macro
37 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
131 DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
26 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;