Searched refs:Phase (Results 1 – 21 of 21) sorted by relevance
/linux-6.12.1/Documentation/ABI/testing/ |
D | sysfs-driver-zynqmp-fpga | 57 Phase 0 = 000 58 Phase 1 = 001 59 Phase 2 = 011 60 Phase 3 = 010 61 Phase 4 = 110 62 Phase 5 = 111 63 Phase 6 = 101 64 Phase 7 = 100
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D | sysfs-bus-iio-isl29501 | 29 Phase data has to be collected when temperature and
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D | sysfs-bus-iio | 817 Phase in radians of one frequency/clock output Y
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/linux-6.12.1/drivers/iio/frequency/ |
D | Kconfig | 6 # Phase-Locked Loop (PLL) frequency synthesizers 27 # Phase-Locked Loop (PLL) frequency synthesizers 30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
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/linux-6.12.1/Documentation/hwmon/ |
D | tps40422.rst | 20 This driver supports TI TPS40422 Dual-Output or Two-Phase Synchronous Buck
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D | mp2888.rst | 25 - Programmable Multi-Phase up to 10 Phases.
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/linux-6.12.1/drivers/hwmon/pmbus/ |
D | Kconfig | 326 MP2856 MP2857 Dual Loop Digital Multi-Phase Controller. 335 MP2888 Digital, Multi-Phase, Pulse-Width Modulation Controller. 344 MP2891 Dual Loop Digital Multi-Phase Controller. 353 MP2975 Dual Loop Digital Multi-Phase Controller. 362 MP2993 Dual Loop Digital Multi-Phase Controller. 372 Dual Loop Digital Multi-Phase Controller.
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/linux-6.12.1/drivers/staging/iio/Documentation/ |
D | sysfs-bus-iio-dds | 38 allows for pin controlled PSK Phase Shift Keying
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/linux-6.12.1/Documentation/driver-api/ |
D | dpll.rst | 10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock 14 DPLL - Digital Phase Locked Loop is an integrated circuit which in 176 Phase offset measurement and adjustment 212 Phase adjust (also min and max) values are integers, but measured phase
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/linux-6.12.1/drivers/scsi/aic7xxx/ |
D | aic79xx.reg | 1804 * SCSI Phase 2747 * 960MHz Phase-Locked Loop Control 0 2774 * 960MHz Phase-Locked Loop Control 1 2815 * 960-MHz Phase-Locked Loop Test Count 2825 * 400-MHz Phase-Locked Loop Control 0 2851 * 400-MHz Phase-Locked Loop Control 1 2873 * 400-MHz Phase-Locked Loop Test Count
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/linux-6.12.1/Documentation/input/devices/ |
D | iforce-protocol.rst | 172 04 Phase. Val 00 = 0 deg, Val 40 = 90 degs.
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/linux-6.12.1/drivers/scsi/pcmcia/ |
D | sym53c500_cs.c | 201 enum Phase { enum
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/linux-6.12.1/Documentation/sound/cards/ |
D | cmipci.rst | 180 IEC958 In Phase Inverse
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/linux-6.12.1/drivers/zorro/ |
D | zorro.ids | 414 2140 Phase 5
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/linux-6.12.1/sound/pci/ |
D | Kconfig | 648 TerraTec EWX 24/96, EWS 88MT/D, DMX 6Fire, Phase 88; 667 7.1 Space/Universe, Phase 22/28; Onkyo SE-90PCI, SE-200PCI;
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/linux-6.12.1/Documentation/networking/dsa/ |
D | sja1105.rst | 161 # Phase-align the base time to the start of the next second.
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/linux-6.12.1/drivers/regulator/ |
D | Kconfig | 1338 Buck converters including Dual-Phase Buck converter, Buck-Boost 1477 The TPS51632 is 3-2-1 Phase D-Cap+ Step Down Driverless Controller
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/linux-6.12.1/Documentation/sound/ |
D | alsa-configuration.rst | 1189 * TerraTec Phase 88 1232 * TerraTec Phase 22 1233 * TerraTec Phase 28
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/linux-6.12.1/Documentation/scsi/ |
D | ChangeLog.sym53c8xx | 552 - Disable by default Phase Mismatch handling from SCRIPTS, since
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D | ChangeLog.lpfc | 325 * Phase II of GFP_ATOMIC effort. Replaced iocb_mem_pool and
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/linux-6.12.1/Documentation/filesystems/xfs/ |
D | xfs-online-fsck-design.rst | 5033 - Phase 1 checks that the provided path maps to an XFS filesystem and detect 5036 - Phase 2 scrubs groups (g) and (h) in parallel using a threaded workqueue. 5038 - Phase 3 scans inodes in parallel. 5041 - Phase 4 repairs everything in groups (i) through (d) so that phases 5 and 6 5044 - Phase 5 starts by checking groups (b) and (c) in parallel before moving on 5047 - Phase 6 depends on groups (i) through (b) to find file data blocks to verify, 5050 - Phase 7 checks group (a), having validated everything else. 5130 Phase 4 is responsible for scheduling a lot of repair work in as quick a
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