| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| D | smu9_driver_if.h | 238 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ member
|
| D | smu7_discrete.h | 212 uint8_t PcieLaneCount; member
|
| D | smu71_discrete.h | 154 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
|
| D | smu72_discrete.h | 145 uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ member
|
| D | smu74_discrete.h | 158 uint8_t PcieLaneCount; member
|
| D | smu11_driver_if.h | 454 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; member
|
| D | smu73_discrete.h | 126 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
|
| D | smu75_discrete.h | 168 uint8_t PcieLaneCount; member
|
| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | smu7_discrete.h | 205 uint8_t PcieLaneCount; member
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 533 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : in vega12_override_pcie_parameters()
534 pp_table->PcieLaneCount[i]; in vega12_override_pcie_parameters()
537 pp_table->PcieLaneCount[i]) { in vega12_override_pcie_parameters()
549 pp_table->PcieLaneCount[i] = pcie_width_arg; in vega12_override_pcie_parameters()
564 pp_table->PcieLaneCount[i] = pcie_width; in vega12_override_pcie_parameters()
|
| D | vega20_hwmgr.c | 879 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : in vega20_override_pcie_parameters()
880 pp_table->PcieLaneCount[i]; in vega20_override_pcie_parameters()
883 pp_table->PcieLaneCount[i]) { in vega20_override_pcie_parameters()
895 pp_table->PcieLaneCount[i] = pcie_width_arg; in vega20_override_pcie_parameters()
910 pp_table->PcieLaneCount[i] = pcie_width; in vega20_override_pcie_parameters()
3474 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
|
| D | vega10_hwmgr.c | 1552 if (pp_table->PcieLaneCount[i] > pcie_width) in vega10_override_pcie_parameters()
1553 pp_table->PcieLaneCount[i] = pcie_width; in vega10_override_pcie_parameters()
1559 pp_table->PcieLaneCount[i] = pcie_width; in vega10_override_pcie_parameters()
1577 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; in vega10_populate_smc_link_levels()
1590 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; in vega10_populate_smc_link_levels()
4765 lane_width = pptable->PcieLaneCount[i]; in vega10_emit_clock_levels()
4909 lane_width = pptable->PcieLaneCount[i]; in vega10_print_clock_levels()
|
| D | vega20_processpptables.c | 403 pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]);
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu11_driver_if_sienna_cichlid.h | 757 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
1117 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
|
| D | smu11_driver_if_navi10.h | 627 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
|
| D | smu13_driver_if_v13_0_0.h | 1137 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
|
| D | smu13_driver_if_v13_0_7.h | 1139 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
|
| D | smu14_driver_if_v14_0.h | 1232 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/ |
| D | smu9_driver_if.h | 342 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; member
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | navi10_ppt.c | 2415 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; in navi10_update_pcie_parameters()
2421 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? in navi10_update_pcie_parameters()
2422 pptable->PcieLaneCount[i] : pcie_width_cap); in navi10_update_pcie_parameters()
2433 if (pptable->PcieLaneCount[i] > pcie_width_cap) in navi10_update_pcie_parameters()
|
| D | sienna_cichlid_ppt.c | 2117 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); in sienna_cichlid_update_pcie_parameters()
2855 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); in beige_goby_dump_pptable()
3494 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); in sienna_cichlid_dump_pptable()
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | smu_v13_0_7_ppt.c | 693 !skutable->PcieLaneCount[link_level] && in smu_v13_0_7_set_default_dpm_table()
700 skutable->PcieLaneCount[link_level]; in smu_v13_0_7_set_default_dpm_table()
|
| D | smu_v13_0_0_ppt.c | 695 !skutable->PcieLaneCount[link_level] && in smu_v13_0_0_set_default_dpm_table()
702 skutable->PcieLaneCount[link_level]; in smu_v13_0_0_set_default_dpm_table()
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| D | smu_v14_0_2_ppt.c | 626 !skutable->PcieLaneCount[link_level] && in smu_v14_0_2_set_default_dpm_table()
633 skutable->PcieLaneCount[link_level]; in smu_v14_0_2_set_default_dpm_table()
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | vegam_smumgr.c | 582 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in vegam_populate_smc_link_level()
|