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Searched refs:PSR_I_BIT (Results 1 – 25 of 31) sorted by relevance

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/linux-6.12.1/arch/arm64/include/asm/
Ddaifflags.h16 #define DAIF_PROCCTX_NOIRQ (PSR_I_BIT | PSR_F_BIT)
17 #define DAIF_ERRCTX (PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
18 #define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
50 flags |= PSR_I_BIT | PSR_F_BIT; in local_daif_save_flags()
69 bool irq_disabled = flags & PSR_I_BIT; in local_daif_restore()
72 (read_sysreg(daif) & (PSR_I_BIT | PSR_F_BIT)) != (PSR_I_BIT | PSR_F_BIT)); in local_daif_restore()
89 flags &= ~(PSR_I_BIT | PSR_F_BIT); in local_daif_restore()
Dptrace.h20 (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
22 (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h)
220 (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
Dcpuidle.h20 write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \
Defi.h51 #define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
Dirqflags.h104 return flags & PSR_I_BIT; in __daif_irqs_disabled_flags()
/linux-6.12.1/arch/arm/kernel/
Dfiqasm.S26 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
39 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
Dentry-armv.S322 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
323 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
327 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
328 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
336 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
337 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
341 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
342 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
Diwmmxt.S192 orr r2, ip, #PSR_I_BIT @ disable interrupts
239 orr r2, ip, #PSR_I_BIT @ disable interrupts
277 orr r2, ip, #PSR_I_BIT @ disable interrupts
340 orr ip, r2, #PSR_I_BIT @ disable interrupts
Dsetup.c581 PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), in cpu_init()
583 PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE), in cpu_init()
585 PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE), in cpu_init()
587 PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), in cpu_init()
589 PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE) in cpu_init()
/linux-6.12.1/arch/arm/include/asm/
Dptrace.h50 (!((regs)->ARM_cpsr & PSR_I_BIT))
68 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { in valid_user_regs()
Dirqflags.h19 #define IRQMASK_I_BIT PSR_I_BIT
Defi.h42 (PSR_J_BIT | PSR_E_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | \
Dassembler.h107 msr cpsr_c, #PSR_I_BIT | SVC_MODE
197 tst \oldcpsr, #PSR_I_BIT
446 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
461 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
/linux-6.12.1/arch/arm/mach-s3c/
Dsleep-s3c64xx.S40 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
/linux-6.12.1/tools/testing/selftests/arm64/signal/testcases/
Dmangle_pstate_invalid_daif_bits.c23 uc->uc_mcontext.pstate |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT; in mangle_invalid_pstate_run()
/linux-6.12.1/arch/arm64/kvm/
Dreset.c40 #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \
43 #define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \
/linux-6.12.1/arch/arm/mach-rockchip/
Dsleep.S20 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
/linux-6.12.1/arch/arm/include/uapi/asm/
Dptrace.h79 #define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */ macro
/linux-6.12.1/arch/arm/mm/
Dproc-feroceon.S264 orr r3, r2, #PSR_I_BIT
311 orr r3, r2, #PSR_I_BIT
343 orr r3, r2, #PSR_I_BIT
375 orr r3, r2, #PSR_I_BIT
Dproc-xsc3.S110 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
457 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
/linux-6.12.1/arch/arm64/include/uapi/asm/
Dptrace.h46 #define PSR_I_BIT 0x00000080 macro
/linux-6.12.1/arch/arm64/kvm/hyp/nvhe/
Dhyp-init.S234 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL2h)
Dhost.S114 mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
/linux-6.12.1/arch/arm64/kvm/hyp/
Dexception.c165 new |= PSR_I_BIT; in enter_exception64()
/linux-6.12.1/arch/arm/probes/kprobes/
Dtest-core.c1147 regs->ARM_cpsr |= PSR_I_BIT; in setup_test_context()
1235 regs->ARM_cpsr &= ~PSR_I_BIT; in test_after_pre_handler()

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