| /linux-6.12.1/include/dt-bindings/clock/ |
| D | rk3188-cru-common.h | 13 #define PLL_CPLL 3 macro
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| D | rk3128-cru.h | 13 #define PLL_CPLL 3 macro
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| D | rk3228-cru.h | 13 #define PLL_CPLL 3 macro
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| D | rk3368-cru.h | 13 #define PLL_CPLL 4 macro
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| D | rk3288-cru.h | 13 #define PLL_CPLL 3 macro
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| D | rk3328-cru.h | 13 #define PLL_CPLL 3 macro
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| D | px30-cru.h | 9 #define PLL_CPLL 3 macro
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| D | rockchip,rk3576-cru.h | 20 #define PLL_CPLL 4 macro
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| D | rockchip,rv1126-cru.h | 67 #define PLL_CPLL 3 macro
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| D | rk3399-cru.h | 14 #define PLL_CPLL 4 macro
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| D | rockchip,rk3588-cru.h | 20 #define PLL_CPLL 5 macro
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| D | rk3568-cru.h | 72 #define PLL_CPLL 3 macro
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-rk3188.c | 220 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
231 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| D | clk-rk3128.c | 163 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| D | clk-rk3228.c | 173 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
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| D | clk-rk3328.c | 221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| D | clk-rk3368.c | 136 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
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| D | clk-rk3288.c | 230 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
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| D | clk-px30.c | 191 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| D | clk-rv1126.c | 203 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3368-r88.dts | 216 assigned-clock-parents = <&cru PLL_CPLL>;
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| D | rk3368-lba3368.dts | 558 assigned-clock-parents = <&cru PLL_CPLL>;
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| D | rk3399-gru-scarlet.dtsi | 368 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| /linux-6.12.1/arch/arm/boot/dts/rockchip/ |
| D | rk3188-bqedison2qc.dts | 227 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| D | rk3066a.dtsi | 232 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
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