Searched refs:PLANE_CTL_YUV422_ORDER_MASK (Results 1 – 2 of 2) sorted by relevance
74 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) macro75 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)76 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)77 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)78 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
231 val & PLANE_CTL_YUV422_ORDER_MASK); in intel_vgpu_decode_primary_plane()